From 8e6bb80e9a71cf07be8310fc8ce582e700f69c6d Mon Sep 17 00:00:00 2001
From: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date: Sun, 25 Jun 2017 05:46:56 +0200
Subject: vendorcode/amd: Satisfy clang's bracing requirements

src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h:3688:7: error:
suggest braces around initialization of subobject

Change-Id: Id086a64205dfffa2d1324993f4164508b57b6993
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
---
 src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/vendorcode/amd/agesa/f12')

diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h
index 4fd5354d05..0fd8232ead 100644
--- a/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h
+++ b/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h
@@ -4089,7 +4089,7 @@ BOOLEAN MemFS3DefConstructorRet (
       0
     };
     MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
-      0
+      { 0 }
     };
   #endif
   #if OPTION_DDR3
@@ -4097,7 +4097,7 @@ BOOLEAN MemFS3DefConstructorRet (
       0
     };
     MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
-      0
+      { 0 }
     };
   #endif
     /*---------------------------------------------------------------------------------------------------
-- 
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