From 621ca384a7a5efb2cc7597504dc17b741cd2df10 Mon Sep 17 00:00:00 2001 From: efdesign98 Date: Mon, 20 Jun 2011 18:12:43 -0700 Subject: Move existing AMD Ffamily14 code to f14 folder This change moves the AMD Family14 cpu Agesa code to the vendorcode/amd/agesa/f14 folder to complete the transition to the family oriented folder structure. Change-Id: I211e80ee04574cc713f38b4cc1b767dbb2bfaa59 Signed-off-by: Frank Vibrans Signed-off-by: efdesign98 Reviewed-on: http://review.coreboot.org/52 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/vendorcode/amd/agesa/Include/AdvancedApi.h | 168 - src/vendorcode/amd/agesa/Include/BrazosInstall.h | 102 - src/vendorcode/amd/agesa/Include/CommonReturns.h | 125 - src/vendorcode/amd/agesa/Include/DanNiInstall.h | 117 - src/vendorcode/amd/agesa/Include/DanubeInstall.h | 102 - src/vendorcode/amd/agesa/Include/DevTestInstall.h | 111 - src/vendorcode/amd/agesa/Include/DragonInstall.h | 102 - src/vendorcode/amd/agesa/Include/Filecode.h | 849 ---- src/vendorcode/amd/agesa/Include/GeneralServices.h | 203 - src/vendorcode/amd/agesa/Include/GnbInterface.h | 96 - .../amd/agesa/Include/GnbInterfaceStub.h | 232 -- src/vendorcode/amd/agesa/Include/Ids.h | 927 ----- src/vendorcode/amd/agesa/Include/IdsHt.h | 126 - src/vendorcode/amd/agesa/Include/LynxInstall.h | 102 - .../amd/agesa/Include/MaranelloInstall.h | 118 - src/vendorcode/amd/agesa/Include/NileInstall.h | 102 - src/vendorcode/amd/agesa/Include/OptionC6Install.h | 151 - .../amd/agesa/Include/OptionCpbInstall.h | 122 - .../Include/OptionCpuCacheFlushOnHaltInstall.h | 120 - .../agesa/Include/OptionCpuCoreLevelingInstall.h | 115 - .../amd/agesa/Include/OptionCpuFamiliesInstall.h | 406 -- .../amd/agesa/Include/OptionCpuFeaturesInstall.h | 78 - src/vendorcode/amd/agesa/Include/OptionDmi.h | 92 - .../amd/agesa/Include/OptionDmiInstall.h | 194 - .../amd/agesa/Include/OptionFamily10hInstall.h | 1996 ---------- .../amd/agesa/Include/OptionFamily12hEarlySample.h | 138 - .../amd/agesa/Include/OptionFamily12hInstall.h | 665 ---- .../amd/agesa/Include/OptionFamily14hEarlySample.h | 170 - .../amd/agesa/Include/OptionFamily14hInstall.h | 661 ---- .../amd/agesa/Include/OptionFamily15hInstall.h | 717 ---- .../amd/agesa/Include/OptionGfxRecovery.h | 84 - .../amd/agesa/Include/OptionGfxRecoveryInstall.h | 56 - src/vendorcode/amd/agesa/Include/OptionGnb.h | 92 - .../amd/agesa/Include/OptionGnbInstall.h | 449 --- .../amd/agesa/Include/OptionHtAssistInstall.h | 109 - src/vendorcode/amd/agesa/Include/OptionHtInstall.h | 301 -- .../amd/agesa/Include/OptionHwC1eInstall.h | 83 - .../amd/agesa/Include/OptionIdsInstall.h | 417 -- .../amd/agesa/Include/OptionIoCstateInstall.h | 135 - .../amd/agesa/Include/OptionLowPwrPstateInstall.h | 89 - src/vendorcode/amd/agesa/Include/OptionMemory.h | 342 -- .../amd/agesa/Include/OptionMemoryInstall.h | 4051 -------------------- .../amd/agesa/Include/OptionMemoryRecovery.h | 65 - .../agesa/Include/OptionMemoryRecoveryInstall.h | 602 --- .../amd/agesa/Include/OptionMsgBasedC1eInstall.h | 119 - .../amd/agesa/Include/OptionMultiSocket.h | 169 - .../amd/agesa/Include/OptionMultiSocketInstall.h | 92 - .../agesa/Include/OptionPreserveMailboxInstall.h | 107 - src/vendorcode/amd/agesa/Include/OptionPstate.h | 118 - .../amd/agesa/Include/OptionPstateInstall.h | 243 -- .../amd/agesa/Include/OptionS3ScriptInstall.h | 94 - src/vendorcode/amd/agesa/Include/OptionSlit.h | 99 - .../amd/agesa/Include/OptionSlitInstall.h | 82 - src/vendorcode/amd/agesa/Include/OptionSrat.h | 85 - .../amd/agesa/Include/OptionSratInstall.h | 76 - .../amd/agesa/Include/OptionSwC1eInstall.h | 83 - src/vendorcode/amd/agesa/Include/OptionWhea.h | 86 - .../amd/agesa/Include/OptionWheaInstall.h | 77 - src/vendorcode/amd/agesa/Include/Options.h | 94 - src/vendorcode/amd/agesa/Include/OptionsHt.h | 103 - src/vendorcode/amd/agesa/Include/OptionsPage.h | 375 -- src/vendorcode/amd/agesa/Include/PlatformInstall.h | 2599 ------------- .../agesa/Include/PlatformMemoryConfiguration.h | 314 -- src/vendorcode/amd/agesa/Include/SabineInstall.h | 117 - .../amd/agesa/Include/SanMarinoInstall.h | 118 - src/vendorcode/amd/agesa/Include/ScorpiusInstall.h | 117 - src/vendorcode/amd/agesa/Include/TigrisInstall.h | 102 - src/vendorcode/amd/agesa/Include/Topology.h | 165 - src/vendorcode/amd/agesa/Include/gcc-intrin.h | 630 --- 69 files changed, 22346 deletions(-) delete mode 100644 src/vendorcode/amd/agesa/Include/AdvancedApi.h delete mode 100644 src/vendorcode/amd/agesa/Include/BrazosInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/CommonReturns.h delete mode 100644 src/vendorcode/amd/agesa/Include/DanNiInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/DanubeInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/DevTestInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/DragonInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/Filecode.h delete mode 100644 src/vendorcode/amd/agesa/Include/GeneralServices.h delete mode 100644 src/vendorcode/amd/agesa/Include/GnbInterface.h delete mode 100644 src/vendorcode/amd/agesa/Include/GnbInterfaceStub.h delete mode 100644 src/vendorcode/amd/agesa/Include/Ids.h delete mode 100644 src/vendorcode/amd/agesa/Include/IdsHt.h delete mode 100644 src/vendorcode/amd/agesa/Include/LynxInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/MaranelloInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/NileInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionC6Install.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionCpbInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionCpuCacheFlushOnHaltInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionCpuCoreLevelingInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionCpuFamiliesInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionCpuFeaturesInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionDmi.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionDmiInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionFamily10hInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionFamily12hEarlySample.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionFamily12hInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionFamily14hEarlySample.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionFamily14hInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionFamily15hInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionGfxRecovery.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionGfxRecoveryInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionGnb.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionGnbInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionHtAssistInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionHtInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionHwC1eInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionIdsInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionIoCstateInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionLowPwrPstateInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionMemory.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionMemoryInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionMemoryRecovery.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionMemoryRecoveryInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionMsgBasedC1eInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionMultiSocket.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionMultiSocketInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionPreserveMailboxInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionPstate.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionPstateInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionS3ScriptInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionSlit.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionSlitInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionSrat.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionSratInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionSwC1eInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionWhea.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionWheaInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/Options.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionsHt.h delete mode 100644 src/vendorcode/amd/agesa/Include/OptionsPage.h delete mode 100644 src/vendorcode/amd/agesa/Include/PlatformInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/PlatformMemoryConfiguration.h delete mode 100644 src/vendorcode/amd/agesa/Include/SabineInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/SanMarinoInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/ScorpiusInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/TigrisInstall.h delete mode 100644 src/vendorcode/amd/agesa/Include/Topology.h delete mode 100644 src/vendorcode/amd/agesa/Include/gcc-intrin.h (limited to 'src/vendorcode/amd/agesa/Include') diff --git a/src/vendorcode/amd/agesa/Include/AdvancedApi.h b/src/vendorcode/amd/agesa/Include/AdvancedApi.h deleted file mode 100644 index 573650a739..0000000000 --- a/src/vendorcode/amd/agesa/Include/AdvancedApi.h +++ /dev/null @@ -1,168 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Advanced API Interface for HT, Memory and CPU - * - * Contains additional declarations need to use HT, Memory and CPU Advanced interface, such as - * would be required by the basic interface implementations. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Include - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - -#ifndef _ADVANCED_API_H_ -#define _ADVANCED_API_H_ - -/*---------------------------------------------------------------------------- - * HT FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -/** - * A constructor for the HyperTransport input structure. - * - * Sets inputs to valid, basic level, defaults. - * - * @param[in] StdHeader Opaque handle to standard config header - * @param[in] AmdHtInterface HT Interface structure to initialize. - * - * @retval AGESA_SUCCESS Constructors are not allowed to fail -*/ -AGESA_STATUS -AmdHtInterfaceConstructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_HT_INTERFACE *AmdHtInterface - ); - -/** - * The top level external interface for Hypertransport Initialization. - * - * Create our initial internal state, initialize the coherent fabric, - * initialize the non-coherent chains, and perform any required fabric tuning or - * optimization. - * - * @param[in] StdHeader Opaque handle to standard config header - * @param[in] PlatformConfiguration The platform configuration options. - * @param[in] AmdHtInterface HT Interface structure. - * - * @retval AGESA_SUCCESS Only information events logged. - * @retval AGESA_ALERT Sync Flood or CRC error logged. - * @retval AGESA_WARNING Example: expected capability not found - * @retval AGESA_ERROR logged events indicating some devices may not be available - * @retval AGESA_FATAL Mixed Family or MP capability mismatch - * - */ -AGESA_STATUS -AmdHtInitialize ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfiguration, - IN AMD_HT_INTERFACE *AmdHtInterface - ); - -/*---------------------------------------------------------------------------- - * HT Recovery FUNCTIONS PROTOTYPE - * - *---------------------------------------------------------------------------- - */ - -/** - * A constructor for the HyperTransport input structure. - * - */ -AGESA_STATUS -AmdHtResetConstructor ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface - ); - -/** - * Initialize HT at Reset for both Normal and Recovery. - * - */ -AGESA_STATUS -AmdHtInitReset ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface - ); - -/** - * Initialize the Node and Socket maps for an AP Core. - * - */ -AGESA_STATUS -AmdHtInitRecovery ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -///---------------------------------------------------------------------------- -/// MEMORY FUNCTIONS PROTOTYPE -/// -///---------------------------------------------------------------------------- - -AGESA_STATUS -AmdMemRecovery ( - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -AGESA_STATUS -AmdMemAuto ( - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -VOID -AmdMemInitDataStructDef ( - IN OUT MEM_DATA_STRUCT *MemPtr, - IN OUT PLATFORM_CONFIGURATION *PlatFormConfig - ); - -VOID -memDefRet ( - VOID - ); - -BOOLEAN -memDefTrue ( - VOID - ); - -BOOLEAN -memDefFalse ( - VOID - ); -#endif // _ADVANCED_API_H_ diff --git a/src/vendorcode/amd/agesa/Include/BrazosInstall.h b/src/vendorcode/amd/agesa/Include/BrazosInstall.h deleted file mode 100644 index 67539655ce..0000000000 --- a/src/vendorcode/amd/agesa/Include/BrazosInstall.h +++ /dev/null @@ -1,102 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build options for a Brazos platform solution - * - * This file generates the defaults tables for the "Brazos" platform solution - * set of processors. The documented build options are imported from a user - * controlled file for processing. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 40817 $ @e \$Date: 2010-10-28 03:28:12 +0800 (Thu, 28 Oct 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "CommonReturns.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'O', 'n', 't', 'a', 'r', 'o', 'P', 'I'} - - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '1', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} - - -// The Brazos solution is defined to be family 0x14 in the FT1 socket. -#define INSTALL_FT1_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_14_SUPPORT TRUE - - -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - - -// Instantiate all solution relevant data. -#include "PlatformInstall.h" - diff --git a/src/vendorcode/amd/agesa/Include/CommonReturns.h b/src/vendorcode/amd/agesa/Include/CommonReturns.h deleted file mode 100644 index 9912edc1cc..0000000000 --- a/src/vendorcode/amd/agesa/Include/CommonReturns.h +++ /dev/null @@ -1,125 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Common Return routines. - * - * Routines which do nothing, returning a result (preferably some version of zero) which - * is consistent with "do nothing" or "default". Useful for function pointer tables. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Common - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _COMMON_RETURNS_H_ -#define _COMMON_RETURNS_H_ - - -/** -* Return True -* -* @retval True Default case, no special action -*/ -BOOLEAN -CommonReturnTrue (void); - -/** -* Return False. -* -* @retval FALSE Default case, no special action -*/ -BOOLEAN -CommonReturnFalse (void); - -/** - * Return (UINT8)zero. - * - * - * @retval zero None, or only case zero. - */ -UINT8 -CommonReturnZero8 (void); - -/** - * Return (UINT32)zero. - * - * - * @retval zero None, or only case zero. - */ -UINT32 -CommonReturnZero32 (void); - -/** - * Return (UINT64)zero. - * - * - * @retval zero None, or only case zero. - */ -UINT64 -CommonReturnZero64 (void); - -/** - * Return NULL - * - * @retval NULL pointer to nothing - */ -VOID * -CommonReturnNULL (void); - -/** -* Return AGESA_SUCCESS. -* -* @retval AGESA_SUCCESS Success. -*/ -AGESA_STATUS -CommonReturnAgesaSuccess (void); - -/** - * Do Nothing. - * - */ -VOID -CommonVoid (void); - -/** - * ASSERT if this routine is called. - * - */ -VOID -CommonAssert (void); - -#endif // _COMMON_RETURNS_H_ diff --git a/src/vendorcode/amd/agesa/Include/DanNiInstall.h b/src/vendorcode/amd/agesa/Include/DanNiInstall.h deleted file mode 100644 index c56f90c1e9..0000000000 --- a/src/vendorcode/amd/agesa/Include/DanNiInstall.h +++ /dev/null @@ -1,117 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build options for a Danube + Nile platform solution - * - * This file generates the defaults tables for the "DanNi" platform solution - * set of processors. The documented build options are imported from a user - * controlled file for processing. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "CommonReturns.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterfaceStub.h" - -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ - // This is the delivery package title, "DanNiPI " - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'D', 'a', 'n', 'N', 'i', 'P', 'I', ' '} - - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '5', '.', '0', 'X', ' ', ' ', ' '} - - -// The DanNi solution is defined to be family 0x10 in the S1g4 and ASB2 sockets. -#define INSTALL_S1G4_SOCKET_SUPPORT TRUE -#define INSTALL_ASB2_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_10_SUPPORT TRUE - -#ifdef BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT - #if BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT == TRUE - #undef INSTALL_S1G4_SOCKET_SUPPORT - #define INSTALL_S1G4_SOCKET_SUPPORT FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT - #if BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT == TRUE - #undef INSTALL_ASB2_SOCKET_SUPPORT - #define INSTALL_ASB2_SOCKET_SUPPORT FALSE - #endif -#endif - - -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0x10) -#define DFLT_SCRUB_L3_RATE (0x10) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0x12) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED -#define DFLT_VRM_SLEW_RATE (5000) - - -// Instantiate all solution relevant data. -#include "PlatformInstall.h" - diff --git a/src/vendorcode/amd/agesa/Include/DanubeInstall.h b/src/vendorcode/amd/agesa/Include/DanubeInstall.h deleted file mode 100644 index f2c91c42a8..0000000000 --- a/src/vendorcode/amd/agesa/Include/DanubeInstall.h +++ /dev/null @@ -1,102 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build options for a Danube platform solution - * - * This file generates the defaults tables for the "Danube" platform solution - * set of processors. The documented build options are imported from a user - * controlled file for processing. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "CommonReturns.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterfaceStub.h" - -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ - // This is the delivery package title, "DanNiPI " - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'D', 'a', 'n', 'N', 'i', 'P', 'I', ' '} - - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '5', '.', '0', 'X', ' ', ' ', ' '} - - -// The Danube solution is defined to be family 0x10 in the S1g4 socket. -#define INSTALL_S1G4_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_10_SUPPORT TRUE - - -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0x10) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0x12) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED -#define DFLT_VRM_SLEW_RATE (5000) - - -// Instantiate all solution relevant data. -#include "PlatformInstall.h" - diff --git a/src/vendorcode/amd/agesa/Include/DevTestInstall.h b/src/vendorcode/amd/agesa/Include/DevTestInstall.h deleted file mode 100644 index 9874551ae1..0000000000 --- a/src/vendorcode/amd/agesa/Include/DevTestInstall.h +++ /dev/null @@ -1,111 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build options for a DevTest platform solution - * - * This file generates the defaults tables for the "DevTest" platform solution - * set of processors. The documented build options are imported from a user - * controlled file for processing. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "CommonReturns.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterfaceStub.h" - -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ - // This is the delivery package title, "DevTest " - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'D', 'e', 'v', 'T', 'e', 's', 't', ' '} - - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '1', '.', '2', '.', '3', 'X', ' ', ' ', ' '} - - -// The DevTest solution is defined to be everything that AGESA supports. -#define INSTALL_C32_SOCKET_SUPPORT TRUE -#define INSTALL_G34_SOCKET_SUPPORT TRUE -#define INSTALL_S1G4_SOCKET_SUPPORT TRUE -#define INSTALL_ASB2_SOCKET_SUPPORT TRUE -#define INSTALL_FS1_SOCKET_SUPPORT TRUE -#define INSTALL_FM1_SOCKET_SUPPORT TRUE -#define INSTALL_FT1_SOCKET_SUPPORT TRUE -#define INSTALL_AM3_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_10_SUPPORT TRUE -#define INSTALL_FAMILY_12_SUPPORT TRUE -#define INSTALL_FAMILY_14_SUPPORT TRUE -#define INSTALL_FAMILY_15_SUPPORT TRUE - -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0xFF) -#define DFLT_SCRUB_L2_RATE (0x10) -#define DFLT_SCRUB_L3_RATE (0x10) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0x12) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED -#define DFLT_VRM_SLEW_RATE (2500) - - -// Instantiate all solution relevant data. -#include "PlatformInstall.h" - diff --git a/src/vendorcode/amd/agesa/Include/DragonInstall.h b/src/vendorcode/amd/agesa/Include/DragonInstall.h deleted file mode 100644 index ee45b72299..0000000000 --- a/src/vendorcode/amd/agesa/Include/DragonInstall.h +++ /dev/null @@ -1,102 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build options for a Dragon platform solution - * - * This file generates the defaults tables for the "Dragon" platform solution - * set of processors. The documented build options are imported from a user - * controlled file for processing. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "CommonReturns.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterfaceStub.h" - -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ - // This is the delivery package title, "DragonPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'D', 'r', 'a', 'g', 'o', 'n', 'P', 'I'} - - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '1', '.', '2', '.', '3', 'X', ' ', ' ', ' '} - - -// The Danube solution is defined to be family 0x10 in the AM3 socket. -#define INSTALL_AM3_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_10_SUPPORT TRUE - - -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED -#define DFLT_VRM_SLEW_RATE (2500) - - -// Instantiate all solution relevant data. -#include "PlatformInstall.h" - diff --git a/src/vendorcode/amd/agesa/Include/Filecode.h b/src/vendorcode/amd/agesa/Include/Filecode.h deleted file mode 100644 index 9ba1b29f8f..0000000000 --- a/src/vendorcode/amd/agesa/Include/Filecode.h +++ /dev/null @@ -1,849 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Collectively assign unique filecodes for assert and debug to each source file. - * - * Publish values for decorated filenames, which can be used for - * ASSERT and debug support using a preprocessor define like: - * @n \#define FILECODE MY_C_FILENAME_FILECODE @n - * This file serves as a reference for debugging to associate the code and filename. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Include - * @e \$Revision: 40742 $ @e \$Date: 2010-10-27 04:04:08 +0800 (Wed, 27 Oct 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _FILECODE_H_ -#define _FILECODE_H_ - -#define UNASSIGNED_FILE_FILECODE (0xFFFF) - -/// For debug use in any Platform's options C file. -/// Can be reused for platforms and image builds, since only one options file can be built. -#define PLATFORM_SPECIFIC_OPTIONS_FILECODE (0xBBBB) - - -#define PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE (0xA001) -#define PROC_GNB_GFX_FAMILY_0X12_F12GFXSERVICES_FILECODE (0xA002) -#define PROC_GNB_GFX_FAMILY_0X14_F14GFXSERVICES_FILECODE (0xA003) -#define PROC_GNB_GFX_GFXCONFIGDATA_FILECODE (0xA004) -#define PROC_GNB_GFX_GFXDEBUGBAR_FILECODE (0xA005) -#define PROC_GNB_GFX_GFXGMCINIT_FILECODE (0xA006) -#define PROC_GNB_GFX_GFXINITATENVPOST_FILECODE (0xA010) -#define PROC_GNB_GFX_GFXINITATMIDPOST_FILECODE (0xA011) -#define PROC_GNB_GFX_GFXINITATPOST_FILECODE (0xA012) -#define PROC_GNB_GFX_GFXINTEGRATEDINFOTABLEINIT_FILECODE (0xA013) -#define PROC_GNB_GFX_GFXLIB_FILECODE (0xA014) -#define PROC_GNB_GFX_GFXREGISTERACC_FILECODE (0xA015) -#define PROC_GNB_GFX_GFXSTRAPSINIT_FILECODE (0xA016) -#define PROC_GNB_GNBINITATEARLY_FILECODE (0xA017) -#define PROC_GNB_GNBINITATENV_FILECODE (0xA020) -#define PROC_GNB_GNBINITATLATE_FILECODE (0xA021) -#define PROC_GNB_GNBINITATMID_FILECODE (0xA022) -#define PROC_GNB_GNBINITATPOST_FILECODE (0xA023) -#define PROC_GNB_GNBINITATRESET_FILECODE (0xA024) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE (0xA025) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE (0xA026) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE (0xA027) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE (0xA028) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE (0xA029) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE (0xA02A) -#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE (0xA030) -#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE (0xA031) -#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE (0xA032) -#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXPOWERPLAYTABLE_FILECODE (0xA033) -#define PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE (0xA034) -#define PROC_GNB_MODULES_GNBPCIEALIBV1_PCIEALIB_FILECODE (0xA035) -#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE (0xA036) -#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE (0xA037) -#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE (0xA038) -#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE (0xA039) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPM_FILECODE (0xA03A) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE (0xA03B) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE (0xA03C) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE (0xA03D) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE (0xA03E) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE (0xA03F) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE (0xA041) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE (0xA043) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESBLINK_FILECODE (0xA044) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE (0xA045) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE (0xA046) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE (0xA047) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE (0xA048) -#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE (0xA049) -#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIETRAINING_FILECODE (0xA04A) -#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIEWORKAROUNDS_FILECODE (0xA04B) -#define PROC_GNB_NB_FAMILY_0X12_F12NBPOWERGATE_FILECODE (0xA04C) -#define PROC_GNB_NB_FAMILY_0X12_F12NBSERVICES_FILECODE (0xA04D) -#define PROC_GNB_NB_FAMILY_0X12_F12NBSMU_FILECODE (0xA04E) -#define PROC_GNB_NB_FAMILY_0X14_F14NBLCLKNCLKRATIO_FILECODE (0xA04F) -#define PROC_GNB_NB_FAMILY_0X14_F14NBPOWERGATE_FILECODE (0xA050) -#define PROC_GNB_NB_FAMILY_0X14_F14NBSERVICES_FILECODE (0xA051) -#define PROC_GNB_NB_FAMILY_0X14_F14NBSMU_FILECODE (0xA052) -#define PROC_GNB_NB_FEATURE_NBFUSETABLE_FILECODE (0xA053) -#define PROC_GNB_NB_FEATURE_NBLCLKDPM_FILECODE (0xA054) -#define PROC_GNB_NB_FAMILY_0X12_F12NBLCLKDPM_FILECODE (0xA055) -#define PROC_GNB_NB_FAMILY_0X14_F14NBLCLKDPM_FILECODE (0xA056) -#define PROC_GNB_NB_NBCONFIGDATA_FILECODE (0xA060) -#define PROC_GNB_NB_NBINIT_FILECODE (0xA061) -#define PROC_GNB_NB_NBINITATEARLY_FILECODE (0xA062) -#define PROC_GNB_NB_NBINITATENV_FILECODE (0xA063) -#define PROC_GNB_NB_NBINITATLATEPOST_FILECODE (0xA070) -#define PROC_GNB_NB_NBINITATPOST_FILECODE (0xA071) -#define PROC_GNB_NB_NBINITATRESET_FILECODE (0xA072) -#define PROC_GNB_NB_NBPOWERMGMT_FILECODE (0xA073) -#define PROC_GNB_NB_NBSMULIB_FILECODE (0xA074) -#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEALIB_FILECODE (0xA075) -#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE (0xA076) -#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXSERVICES_FILECODE (0xA077) -#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEPHYSERVICES_FILECODE (0xA078) -#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEPIFSERVICES_FILECODE (0xA079) -#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEWRAPPERSERVICES_FILECODE (0xA07A) -#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEALIB_FILECODE (0xA07D) -#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIECOMPLEXCONFIG_FILECODE (0xA07E) -#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIECOMPLEXSERVICES_FILECODE (0xA07F) -#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEPHYSERVICES_FILECODE (0xA080) -#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEPIFSERVICES_FILECODE (0xA081) -#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEWRAPPERSERVICES_FILECODE (0xA082) -#define PROC_GNB_PCIE_FEATURE_PCIEPOWERGATE_FILECODE (0xA083) -#define PROC_GNB_PCIE_PCIEINIT_FILECODE (0xA084) -#define PROC_GNB_PCIE_PCIEINITATEARLYPOST_FILECODE (0xA085) -#define PROC_GNB_PCIE_PCIEINITATENV_FILECODE (0xA086) -#define PROC_GNB_PCIE_PCIEINITATLATEPOST_FILECODE (0xA087) -#define PROC_GNB_PCIE_PCIEINITATPOST_FILECODE (0xA088) -#define PROC_GNB_PCIE_PCIELATEINIT_FILECODE (0xA089) -#define PROC_GNB_PCIE_PCIEMISCLIB_FILECODE (0xA08A) -#define PROC_GNB_PCIE_PCIEPORTINIT_FILECODE (0xA08B) -#define PROC_GNB_PCIE_PCIEPORTLATEINIT_FILECODE (0xA08C) -#define PROC_GNB_MODULES_GNBCABLESAFE_GNBCABLESAFE_FILECODE (0xA08D) -#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE (0xA08E) -#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE (0xA08F) - -#define PROC_RECOVERY_GNB_GNBRECOVERY_FILECODE (0xAE01) -#define PROC_RECOVERY_GNB_NBINITRECOVERY_FILECODE (0xAE02) - -// FCH -#define PROC_COMMON_AMDFCH_FILECODE (0xB000) -#define PROC_FCH_AZALIA_AZALIA_FILECODE (0xB001) -#define PROC_FCH_AZALIA_AZALIARESET_FILECODE (0xB002) -#define PROC_FCH_COMMON_ACPILIB_FILECODE (0xB010) -#define PROC_FCH_COMMON_AMDSBLIB_FILECODE (0xB011) -#define PROC_FCH_COMMON_FCHCOMMON_FILECODE (0xB012) -#define PROC_FCH_COMMON_FCHCOMMONSMM_FILECODE (0xB013) -#define PROC_FCH_COMMON_MEMLIB_FILECODE (0xB014) -#define PROC_FCH_COMMON_PCILIB_FILECODE (0xB015) -#define PROC_FCH_COMMON_SBPELIB_FILECODE (0xB016) -#define PROC_FCH_GEC_FAMILY_HUDSON2_GEC_FILECODE (0xB020) -#define PROC_FCH_GEC_FAMILY_HUDSON2_GECRESET_FILECODE (0xB021) -#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HWACPI_FILECODE (0xB030) -#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HWACPIRESET_FILECODE (0xB031) -#define PROC_FCH_HWM_FAMILY_HUDSON2_HWM_FILECODE (0xB032) -#define PROC_FCH_HWM_FAMILY_HUDSON2_HWMRESET_FILECODE (0xB033) -#define PROC_FCH_IDE_IDE_FILECODE (0xB040) -#define PROC_FCH_IMC_FAMILY_HUDSON2_IMC_FILECODE (0xB050) -#define PROC_FCH_IMC_FAMILY_HUDSON2_IMCLIB_FILECODE (0xB051) -#define PROC_FCH_IMC_FAMILY_HUDSON2_IMCRESET_FILECODE (0xB052) -#define PROC_FCH_IMC_FAMILY_HUDSON2_SBEC_FILECODE (0xB053) -#define PROC_FCH_IMC_FAMILY_HUDSON2_SBECRESET_FILECODE (0xB054) -#define PROC_FCH_INTERFACE_INITRESETDEF_FILECODE (0xB060) -#define PROC_FCH_INTERFACE_INITENVDEF_FILECODE (0xB061) -#define PROC_FCH_INTERFACE_FCHINITRESET_FILECODE (0xB062) -#define PROC_FCH_INTERFACE_FCHINITENV_FILECODE (0xB063) -#define PROC_FCH_INTERFACE_FCHINITLATE_FILECODE (0xB064) -#define PROC_FCH_INTERFACE_FCHINITMID_FILECODE (0xB065) -#define PROC_FCH_INTERFACE_FCHINITS3_FILECODE (0xB066) -#define PROC_FCH_INTERFACE_FCHTASKLAUNCHER_FILECODE (0xB067) -#define PROC_FCH_IR_IR_FILECODE (0xB070) -#define PROC_FCH_PCIB_PCIB_FILECODE (0xB080) -#define PROC_FCH_PCIB_PCIBRESET_FILECODE (0xB081) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_AB_FILECODE (0xB090) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_ABRESET_FILECODE (0xB091) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_GPP_FILECODE (0xB092) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_GPPHP_FILECODE (0xB093) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_GPPLIB_FILECODE (0xB094) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_GPPRESET_FILECODE (0xB095) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_PCIE_FILECODE (0xB096) -#define PROC_FCH_PCIE_FAMILY_HUDSON2_PCIERESET_FILECODE (0xB097) -#define PROC_FCH_SATA_FAMILY_HUDSON2_AHCI_FILECODE (0xB0A0) -#define PROC_FCH_SATA_FAMILY_HUDSON2_AHCILIB_FILECODE (0xB0A1) -#define PROC_FCH_SATA_FAMILY_HUDSON2_IDE2AHCI_FILECODE (0xB0A2) -#define PROC_FCH_SATA_FAMILY_HUDSON2_IDE2AHCILIB_FILECODE (0xB0A3) -#define PROC_FCH_SATA_FAMILY_HUDSON2_RAID_FILECODE (0xB0A4) -#define PROC_FCH_SATA_FAMILY_HUDSON2_RAIDLIB_FILECODE (0xB0A5) -#define PROC_FCH_SATA_FAMILY_HUDSON2_SATA_FILECODE (0xB0A6) -#define PROC_FCH_SATA_FAMILY_HUDSON2_SATAIDE_FILECODE (0xB0A7) -#define PROC_FCH_SATA_FAMILY_HUDSON2_SATAIDELIB_FILECODE (0xB0A8) -#define PROC_FCH_SATA_FAMILY_HUDSON2_SATALIB_FILECODE (0xB0A9) -#define PROC_FCH_SATA_FAMILY_HUDSON2_SATARESET_FILECODE (0xB0AA) -#define PROC_FCH_SBUSB_FAMILY_HUDSON2_EHCI_FILECODE (0xB0B0) -#define PROC_FCH_SBUSB_FAMILY_HUDSON2_EHCIRESET_FILECODE (0xB0B1) -#define PROC_FCH_SBUSB_FAMILY_HUDSON2_OHCI_FILECODE (0xB0B2) -#define PROC_FCH_SBUSB_FAMILY_HUDSON2_OHCIRESET_FILECODE (0xB0B3) -#define PROC_FCH_SBUSB_FAMILY_HUDSON2_USB_FILECODE (0xB0B4) -#define PROC_FCH_SBUSB_FAMILY_HUDSON2_USBRESET_FILECODE (0xB0B5) -#define PROC_FCH_SBUSB_FAMILY_HUDSON2_XHCI_FILECODE (0xB0B6) -#define PROC_FCH_SBUSB_FAMILY_HUDSON2_XHCIRESET_FILECODE (0xB0B7) -#define PROC_FCH_SD_SD_FILECODE (0xB0C0) -#define PROC_FCH_SPI_LPC_FILECODE (0xB0D0) -#define PROC_FCH_SPI_LPCRESET_FILECODE (0xB0D1) -#define PROC_FCH_SPI_SPI_FILECODE (0xB0D2) -#define PROC_FCH_SPI_SPIRESET_FILECODE (0xB0D3) - -#define UEFI_DXE_AMDSBDXE_AMDSBDXE_FILECODE (0xB200) -#define UEFI_DXE_AMDSBWHEA_AMDSBWHEA_FILECODE (0xB210) -#define UEFI_DXE_AMDSBWHEA_BERTTABLE_FILECODE (0xB211) -#define UEFI_DXE_AMDSBWHEA_EINJTABLE_FILECODE (0xB212) -#define UEFI_DXE_AMDSBWHEA_ERSTTABLE_FILECODE (0xB213) -#define UEFI_DXE_AMDSBWHEA_HESTTABLE_FILECODE (0xB214) -#define UEFI_DXE_CF9RESET_CF9RESET_FILECODE (0xB220) -#define UEFI_DXE_CF9RESET_IA32_IA32CF9RESET_FILECODE (0xB221) -#define UEFI_DXE_CF9RESET_X64_X64CF9RESET_FILECODE (0xB222) -#define UEFI_DXE_LEGACYINTERRUPT_LEGACYINTERRUPT_FILECODE (0xB230) -#define UEFI_DXE_SMMCONTROL_SMMCONTROL_FILECODE (0xB240) -#define UEFI_LIBRARY_DECCAN_FCHSMMLIB_FCHDXECOMMON_FILECODE (0xB250) -#define UEFI_LIBRARY_DECCAN_FCHSMMLIB_FCHSMMLIB_FILECODE (0xB251) -#define UEFI_LIBRARY_DECCAN_FCHDXELIB_FCHDXELIB_FILECODE (0xB252) -#define UEFI_PEI_AMDSBPEI_AMDSBPEI_FILECODE (0xB260) -#define UEFI_PEI_AMDSBPEI_SBRESET_FILECODE (0xB261) -#define UEFI_PEI_AMDSBPEI_SBSTALL_FILECODE (0xB262) -#define UEFI_PEI_SMBUS_SMBUS_FILECODE (0xB270) -#define UEFI_SMM_AMDSBSMM_AMDSBSMM_FILECODE (0xB280) -#define UEFI_SMM_AMDSBSMM_GECSMI_FILECODE (0xB281) -#define UEFI_SMM_AMDSBSMM_GPESMI_FILECODE (0xB282) -#define UEFI_SMM_AMDSBSMM_IOTRAPSMI_FILECODE (0xB283) -#define UEFI_SMM_AMDSBSMM_MISCSMI_FILECODE (0xB284) -#define UEFI_SMM_AMDSBSMM_PERIODICTIMERSMI_FILECODE (0xB285) -#define UEFI_SMM_AMDSBSMM_POWERBUTTONSMI_FILECODE (0xB286) -#define UEFI_SMM_AMDSBSMM_SWSMI_FILECODE (0xB287) -#define UEFI_SMM_AMDSBSMM_SXSMI_FILECODE (0xB288) -#define UEFI_DXE_SMBUS_SMBUSLIGHT_FILECODE (0xB2A0) -#define UEFI_SMM_AMDSBSMMDISPATCHER_AMDSBSMMDISPATCHER_FILECODE (0xB290) -#define UEFI_SMM_AMDSBSMMGECROMDISPATCHER_AMDSBSMMGECROMDISPATCHER_FILECODE (0xB291) -#define UEFI_SMM_AMDSBSMMGPEDISPATCHER_AMDSBSMMGPEDISPATCHER_FILECODE (0xB292) -#define UEFI_SMM_AMDSBSMMIOTRAPDISPATCHER_AMDSBSMMIOTRAPDISPATCHER_FILECODE (0xB293) -#define UEFI_SMM_AMDSBSMMMISCDISPATCHER_AMDSBSMMMISCDISPATCHER_FILECODE (0xB294) -#define UEFI_SMM_AMDSBSMMPERIODICALDISPATCHER_AMDSBSMMPERIODICALDISPATCHER_FILECODE (0xB295) -#define UEFI_SMM_AMDSBSMMPWRBTNDISPATCHER_AMDSBSMMPWRBTNDISPATCHER_FILECODE (0xB296) -#define UEFI_SMM_AMDSBSMMSWDISPATCHER_AMDSBSMMSWDISPATCHER_FILECODE (0xB297) -#define UEFI_SMM_AMDSBSMMSXDISPATCHER_AMDSBSMMSXDISPATCHER_FILECODE (0xB298) -#define UEFI_SMM_AMDSBSMMUSBDISPATCHER_AMDSBSMMUSBDISPATCHER_FILECODE (0xB299) - -#define LIB_AMDLIB_FILECODE (0xC001) - -#define LEGACY_PROC_AGESACALLOUTS_FILECODE (0xC010) -#define LEGACY_PROC_HOBTRANSFER_FILECODE (0xC011) -#define LEGACY_PROC_DISPATCHER_FILECODE (0xC012) - -#define UEFI_DXE_AMDAGESADXEDRIVER_AMDAGESADXEDRIVER_FILECODE (0xC120) - -#define UEFI_PEI_AMDINITPOSTPEIM_AMDINITPOSTPEIM_FILECODE (0xC140) -#define UEFI_PEI_AMDPROCESSORINITPEIM_AMDPROCESSORINITPEIM_FILECODE (0xC141) -#define UEFI_PEI_AMDRESETMANAGER_AMDRESETMANAGER_FILECODE (0xC142) -#define UEFI_PROC_HOBTRANSFERUEFI_FILECODE (0xC162) - -#define PROC_COMMON_AMDINITEARLY_FILECODE (0xC020) -#define PROC_COMMON_AMDINITENV_FILECODE (0xC021) -#define PROC_COMMON_AMDINITLATE_FILECODE (0xC022) -#define PROC_COMMON_AMDINITMID_FILECODE (0xC023) -#define PROC_COMMON_AMDINITPOST_FILECODE (0xC024) -#define PROC_COMMON_AMDINITRECOVERY_FILECODE (0xC025) -#define PROC_COMMON_AMDINITRESET_FILECODE (0xC026) -#define PROC_COMMON_AMDINITRESUME_FILECODE (0xC027) -#define PROC_COMMON_AMDS3LATERESTORE_FILECODE (0xC028) -#define PROC_COMMON_AMDS3SAVE_FILECODE (0xC029) -#define PROC_COMMON_AMDLATERUNAPTASK_FILECODE (0xC02A) - -#define PROC_COMMON_COMMONRETURNS_FILECODE (0xC0C0) -#define PROC_COMMON_CREATESTRUCT_FILECODE (0xC0D0) -#define PROC_COMMON_COMMONINITS_FILECODE (0xC0F0) -#define PROC_COMMON_S3RESTORESTATE_FILECODE (0xC0F8) -#define PROC_COMMON_S3SAVESTATE_FILECODE (0xC0F9) - -#define PROC_CPU_CPUAPICUTILITIES_FILECODE (0xC401) -#define PROC_CPU_CPUBRANDID_FILECODE (0xC402) -#define PROC_CPU_TABLE_FILECODE (0xC403) -#define PROC_CPU_CPUEARLYINIT_FILECODE (0xC405) -#define PROC_CPU_CPUEVENTLOG_FILECODE (0xC406) -#define PROC_CPU_CPUFAMILYTRANSLATION_FILECODE (0xC407) -#define PROC_CPU_CPUGENERALSERVICES_FILECODE (0xC408) -#define PROC_CPU_CPUINITEARLYTABLE_FILECODE (0xC409) -#define PROC_CPU_CPULATEINIT_FILECODE (0xC40A) -#define PROC_CPU_CPUMICROCODEPATCH_FILECODE (0xC40B) -#define PROC_CPU_CPUWARMRESET_FILECODE (0xC40C) -#define PROC_CPU_HEAPMANAGER_FILECODE (0xC40D) -#define PROC_CPU_CPUBIST_FILECODE (0xC40E) - -#define PROC_CPU_CPUPOSTINIT_FILECODE (0xC420) -#define PROC_CPU_CPUPOWERMGMT_FILECODE (0xC430) -#define PROC_CPU_CPUPOWERMGMTMULTISOCKET_FILECODE (0xC431) -#define PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE (0xC432) -#define PROC_CPU_S3_FILECODE (0xC460) - -// Family 10h -#define PROC_CPU_FAMILY_0X10_CPUCOMMONF10UTILITIES_FILECODE (0xC801) -#define PROC_CPU_FAMILY_0X10_CPUF10BRANDID_FILECODE (0xC802) -#define PROC_CPU_FAMILY_0X10_CPUF10CACHEDEFAULTS_FILECODE (0xC803) -#define PROC_CPU_FAMILY_0X10_CPUF10CACHEFLUSHONHALT_FILECODE (0xC804) -#define PROC_CPU_FAMILY_0X10_CPUF10DMI_FILECODE (0xC805) -#define PROC_CPU_FAMILY_0X10_CPUF10EARLYINIT_FILECODE (0xC806) -#define PROC_CPU_FAMILY_0X10_CPUF10FEATURELEVELING_FILECODE (0xC807) -#define PROC_CPU_FAMILY_0X10_CPUF10HTPHYTABLES_FILECODE (0xC808) -#define PROC_CPU_FAMILY_0X10_CPUF10MSRTABLES_FILECODE (0xC809) -#define PROC_CPU_FAMILY_0X10_CPUF10PCITABLES_FILECODE (0xC80A) -#define PROC_CPU_FAMILY_0X10_CPUF10POWERCHECK_FILECODE (0xC80B) -#define PROC_CPU_FAMILY_0X10_CPUF10POWERMGMTSYSTEMTABLES_FILECODE (0xC80C) -#define PROC_CPU_FAMILY_0X10_CPUF10POWERPLANE_FILECODE (0xC80D) -#define PROC_CPU_FAMILY_0X10_CPUF10SOFTWARETHERMAL_FILECODE (0xC80E) -#define PROC_CPU_FAMILY_0X10_CPUF10UTILITIES_FILECODE (0xC80F) -#define PROC_CPU_FAMILY_0X10_CPUF10WHEAINITDATATABLES_FILECODE (0xC810) -#define PROC_CPU_FAMILY_0X10_CPUF10PSTATE_FILECODE (0xC811) -#define PROC_CPU_FAMILY_0X10_CPUF10CPB_FILECODE (0xC812) -#define PROC_CPU_FAMILY_0X10_CPUF10WORKAROUNDSTABLE_FILECODE (0xC813) -#define PROC_CPU_FAMILY_0X10_F10PMNBCOFVIDINIT_FILECODE (0xC820) -#define PROC_CPU_FAMILY_0X10_F10SINGLELINKPCITABLES_FILECODE (0xC821) -#define PROC_CPU_FAMILY_0X10_F10MULTILINKPCITABLES_FILECODE (0xC822) -#define PROC_CPU_FAMILY_0X10_F10PMNBPSTATEINIT_FILECODE (0xC823) -#define PROC_CPU_FAMILY_0X10_F10PMASYMBOOSTINIT_FILECODE (0xC824) -#define PROC_CPU_FAMILY_0X10_F10INITEARLYTABLE_FILECODE (0xC825) -#define PROC_CPU_FAMILY_0X10_F10PMDUALPLANEONLYSUPPORT_FILECODE (0xC826) -#define PROC_CPU_FAMILY_0X10_F10IOCSTATE_FILECODE (0xC827) -#define PROC_CPU_FAMILY_0X10_REVC_F10REVCUTILITIES_FILECODE (0xC830) -#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHWC1E_FILECODE (0xC831) -#define PROC_CPU_FAMILY_0X10_REVC_F10REVCSWC1E_FILECODE (0xC832) -#define PROC_CPU_FAMILY_0X10_REVC_F10REVCPCITABLES_FILECODE (0xC833) -#define PROC_CPU_FAMILY_0X10_REVC_F10REVCMSRTABLES_FILECODE (0xC834) -#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHTPHYTABLES_FILECODE (0xC835) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLHTPHYTABLES_FILECODE (0xC836) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLLOGICALIDTABLES_FILECODE (0xC837) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMICROCODEPATCHTABLES_FILECODE (0xC838) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMSRTABLES_FILECODE (0xC839) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLEQUIVALENCETABLE_FILECODE (0xC83A) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLPCITABLES_FILECODE (0xC83B) -#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLCACHEFLUSHONHALT_FILECODE (0xC83C) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAHTPHYTABLES_FILECODE (0xC83D) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DALOGICALIDTABLES_FILECODE (0xC83E) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMICROCODEPATCHTABLES_FILECODE (0xC83F) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMSRTABLES_FILECODE (0xC840) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAEQUIVALENCETABLE_FILECODE (0xC841) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAPCITABLES_FILECODE (0xC842) -#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DACACHEFLUSHONHALT_FILECODE (0xC843) -#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBHTPHYTABLES_FILECODE (0xC844) -#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBLOGICALIDTABLES_FILECODE (0xC845) -#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMICROCODEPATCHTABLES_FILECODE (0xC846) -#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMSRTABLES_FILECODE (0xC847) -#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBEQUIVALENCETABLE_FILECODE (0xC848) -#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBPCITABLES_FILECODE (0xC849) -#define PROC_CPU_FAMILY_0X10_REVD_F10REVDUTILITIES_FILECODE (0xC850) -#define PROC_CPU_FAMILY_0X10_REVD_F10REVDMSGBASEDC1E_FILECODE (0xC851) -#define PROC_CPU_FAMILY_0X10_REVD_F10REVDHTASSIST_FILECODE (0xC852) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYHTPHYTABLES_FILECODE (0xC853) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYINITEARLYTABLE_FILECODE (0xC854) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYLOGICALIDTABLES_FILECODE (0xC855) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMICROCODEPATCHTABLES_FILECODE (0xC856) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMSRTABLES_FILECODE (0xC857) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYEQUIVALENCETABLE_FILECODE (0xC858) -#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYPCITABLES_FILECODE (0xC859) -#define PROC_CPU_FAMILY_0X10_REVE_F10REVEUTILITIES_FILECODE (0xC860) -#define PROC_CPU_FAMILY_0X10_REVE_F10REVEMSRTABLES_FILECODE (0xC861) -#define PROC_CPU_FAMILY_0X10_REVE_F10REVEPCITABLES_FILECODE (0xC862) -#define PROC_CPU_FAMILY_0X10_REVE_F10REVEHTPHYTABLES_FILECODE (0xC863) -#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHEQUIVALENCETABLE_FILECODE (0xC864) -#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHHTPHYTABLES_FILECODE (0xC865) -#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHLOGICALIDTABLES_FILECODE (0xC866) -#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHMICROCODEPATCHTABLES_FILECODE (0xC867) - -// Family 12h -#define PROC_CPU_FAMILY_0X12_CPUCOMMONF12UTILITIES_FILECODE (0xC901) -#define PROC_CPU_FAMILY_0X12_CPUF12BRANDID_FILECODE (0xC902) -#define PROC_CPU_FAMILY_0X12_CPUF12CACHEDEFAULTS_FILECODE (0xC903) -#define PROC_CPU_FAMILY_0X12_CPUF12DMI_FILECODE (0xC904) -#define PROC_CPU_FAMILY_0X12_CPUF12MSRTABLES_FILECODE (0xC905) -#define PROC_CPU_FAMILY_0X12_CPUF12EARLYNBPSTATEINIT_FILECODE (0xC906) -#define PROC_CPU_FAMILY_0X12_CPUF12PCITABLES_FILECODE (0xC907) -#define PROC_CPU_FAMILY_0X12_CPUF12POWERCHECK_FILECODE (0xC908) -#define PROC_CPU_FAMILY_0X12_CPUF12POWERMGMTSYSTEMTABLES_FILECODE (0xC909) -#define PROC_CPU_FAMILY_0X12_CPUF12POWERPLANE_FILECODE (0xC90A) -#define PROC_CPU_FAMILY_0X12_CPUF12SOFTWARETHERMAL_FILECODE (0xC90B) -#define PROC_CPU_FAMILY_0X12_CPUF12UTILITIES_FILECODE (0xC90C) -#define PROC_CPU_FAMILY_0X12_CPUF12WHEAINITDATATABLES_FILECODE (0xC90D) -#define PROC_CPU_FAMILY_0X12_CPUF12PSTATE_FILECODE (0xC90E) -#define PROC_CPU_FAMILY_0X12_F12C6STATE_FILECODE (0xC90F) -#define PROC_CPU_FAMILY_0X12_F12CPB_FILECODE (0xC910) -#define PROC_CPU_FAMILY_0X12_F12IOCSTATE_FILECODE (0xC911) -#define PROC_CPU_FAMILY_0X12_LN_F12LNLOGICALIDTABLES_FILECODE (0xC921) -#define PROC_CPU_FAMILY_0X12_LN_F12LNMICROCODEPATCHTABLES_FILECODE (0xC922) -#define PROC_CPU_FAMILY_0X12_LN_F12LNEQUIVALENCETABLE_FILECODE (0xC923) -#define PROC_CPU_FAMILY_0X12_CPUF12PERCOREPCITABLES_FILECODE (0xC924) -#define PROC_CPU_FAMILY_0X12_LN_F12LNEARLYSAMPLES_FILECODE (0xC925) - -// Family 14h -#define PROC_CPU_FAMILY_0X14_CPUCOMMONF14UTILITIES_FILECODE (0xCA01) -#define PROC_CPU_FAMILY_0X14_CPUF14BRANDID_FILECODE (0xCA02) -#define PROC_CPU_FAMILY_0X14_CPUF14CACHEDEFAULTS_FILECODE (0xCA03) -#define PROC_CPU_FAMILY_0X14_CPUF14DMI_FILECODE (0xCA04) -#define PROC_CPU_FAMILY_0X14_CPUF14MSRTABLES_FILECODE (0xCA05) -#define PROC_CPU_FAMILY_0X14_CPUF14PCITABLES_FILECODE (0xCA06) -#define PROC_CPU_FAMILY_0X14_CPUF14POWERCHECK_FILECODE (0xCA07) -#define PROC_CPU_FAMILY_0X14_CPUF14POWERMGMTSYSTEMTABLES_FILECODE (0xCA08) -#define PROC_CPU_FAMILY_0X14_CPUF14POWERPLANE_FILECODE (0xCA09) -#define PROC_CPU_FAMILY_0X14_CPUF14SOFTWARETHERMAL_FILECODE (0xCA0A) -#define PROC_CPU_FAMILY_0X14_CPUF14UTILITIES_FILECODE (0xCA0B) -#define PROC_CPU_FAMILY_0X14_CPUF14WHEAINITDATATABLES_FILECODE (0xCA0C) -#define PROC_CPU_FAMILY_0X14_CPUF14PSTATE_FILECODE (0xCA0D) -#define PROC_CPU_FAMILY_0X14_F14C6STATE_FILECODE (0xCA0E) -#define PROC_CPU_FAMILY_0X14_F14IOCSTATE_FILECODE (0xCA0F) -#define PROC_CPU_FAMILY_0X14_ON_F14ONLOGICALIDTABLES_FILECODE (0xCA21) -#define PROC_CPU_FAMILY_0X14_ON_F14ONMICROCODEPATCHTABLES_FILECODE (0xCA22) -#define PROC_CPU_FAMILY_0X14_ON_F14ONEQUIVALENCETABLE_FILECODE (0xCA23) -#define PROC_CPU_FAMILY_0X14_ON_F14ONINITEARLYTABLE_FILECODE (0xCA24) -#define PROC_CPU_FAMILY_0X14_CPUF14PERCOREPCITABLES_FILECODE (0xCA25) -#define PROC_CPU_FAMILY_0X14_ON_F14ONEARLYSAMPLES_FILECODE (0xCA26) - -// Family 15h -#define PROC_CPU_FAMILY_0X15_CPUCOMMONF15UTILITIES_FILECODE (0xCB01) -#define PROC_CPU_FAMILY_0X15_CPUF15BRANDID_FILECODE (0xCB02) -#define PROC_CPU_FAMILY_0X15_CPUF15CACHEDEFAULTS_FILECODE (0xCB03) -#define PROC_CPU_FAMILY_0X15_CPUF15CACHEFLUSHONHALT_FILECODE (0xCB04) -#define PROC_CPU_FAMILY_0X15_CPUF15COREAFTERRESET_FILECODE (0xCB05) -#define PROC_CPU_FAMILY_0X15_CPUF15DMI_FILECODE (0xCB06) -#define PROC_CPU_FAMILY_0X15_CPUF15FEATURELEVELING_FILECODE (0xCB07) -#define PROC_CPU_FAMILY_0X15_CPUF15HTPHYTABLES_FILECODE (0xCB08) -#define PROC_CPU_FAMILY_0X15_CPUF15MSRTABLES_FILECODE (0xCB09) -#define PROC_CPU_FAMILY_0X15_CPUF15NBAFTERRESET_FILECODE (0xCB0A) -#define PROC_CPU_FAMILY_0X15_CPUF15PCITABLES_FILECODE (0xCB0B) -#define PROC_CPU_FAMILY_0X15_CPUF15POWERCHECK_FILECODE (0xCB0C) -#define PROC_CPU_FAMILY_0X15_CPUF15POWERMGMTSYSTEMTABLES_FILECODE (0xCB0D) -#define PROC_CPU_FAMILY_0X15_CPUF15POWERPLANE_FILECODE (0xCB0E) -#define PROC_CPU_FAMILY_0X15_CPUF15SOFTWARETHERMAL_FILECODE (0xCB0F) -#define PROC_CPU_FAMILY_0X15_CPUF15UTILITIES_FILECODE (0xCB10) -#define PROC_CPU_FAMILY_0X15_CPUF15WHEAINITDATATABLES_FILECODE (0xCB11) -#define PROC_CPU_FAMILY_0X15_CPUF15PSTATE_FILECODE (0xCB12) -#define PROC_CPU_FAMILY_0X15_F15PMNBCOFVIDINIT_FILECODE (0xCB13) -#define PROC_CPU_FAMILY_0X15_F15SINGLELINKPCITABLES_FILECODE (0xCB14) -#define PROC_CPU_FAMILY_0X15_F15MULTILINKPCITABLES_FILECODE (0xCB15) -#define PROC_CPU_FAMILY_0X15_F15C6STATE_FILECODE (0xCB16) -#define PROC_CPU_FAMILY_0X15_F15CPB_FILECODE (0xCB17) -#define PROC_CPU_FAMILY_0X15_F15INITEARLYTABLE_FILECODE (0xCB18) -#define PROC_CPU_FAMILY_0X15_F15LOWPWRPSTATE_FILECODE (0xCB19) -#define PROC_CPU_FAMILY_0X15_CPUF15WORKAROUNDSTABLE_FILECODE (0xCB1A) -#define PROC_CPU_FAMILY_0X15_F15IOCSTATE_FILECODE (0xCB1B) -#define PROC_CPU_FAMILY_0X15_OR_F15ORHTASSIST_FILECODE (0xCB30) -#define PROC_CPU_FAMILY_0X15_OR_F15ORMSGBASEDC1E_FILECODE (0xCB31) -#define PROC_CPU_FAMILY_0X15_OR_F15ORLOGICALIDTABLES_FILECODE (0xCB32) -#define PROC_CPU_FAMILY_0X15_OR_F15ORMICROCODEPATCHTABLES_FILECODE (0xCB33) -#define PROC_CPU_FAMILY_0X15_OR_F15ORMSRTABLES_FILECODE (0xCB34) -#define PROC_CPU_FAMILY_0X15_OR_F15ORSHAREDMSRTABLE_FILECODE (0xCB35) -#define PROC_CPU_FAMILY_0X15_OR_F15OREQUIVALENCETABLE_FILECODE (0xCB36) -#define PROC_CPU_FAMILY_0X15_OR_F15ORPCITABLES_FILECODE (0xCB37) - - - -#define PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE (0xDC01) -#define PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE (0xDC02) -#define PROC_CPU_FEATURE_CPUDMI_FILECODE (0xDC10) -#define PROC_CPU_FEATURE_CPUFEATURELEVELING_FILECODE (0xDC20) -#define PROC_CPU_FEATURE_CPUHTASSIST_FILECODE (0xDC30) -#define PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE (0xDC41) -#define PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE (0xDC42) -#define PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE (0xDC43) -#define PROC_CPU_FEATURE_CPUSLIT_FILECODE (0xDC50) -#define PROC_CPU_FEATURE_CPUSRAT_FILECODE (0xDC60) -#define PROC_CPU_FEATURE_CPUWHEA_FILECODE (0xDC70) -#define PROC_CPU_FEATURE_CPUHWC1E_FILECODE (0xDC80) -#define PROC_CPU_FEATURE_CPUSWC1E_FILECODE (0xDC81) -#define PROC_CPU_FEATURE_CPUC6STATE_FILECODE (0xDC82) -#define PROC_CPU_FEATURE_CPUCPB_FILECODE (0xDC83) -#define PROC_CPU_FEATURE_CPULOWPWRPSTATE_FILECODE (0xDC84) -#define PROC_CPU_FEATURE_CPUIOCSTATE_FILECODE (0xDC85) -#define PROC_CPU_FEATURE_CPUFEATURES_FILECODE (0xDC90) -#define PROC_CPU_FEATURE_CPUMSGBASEDC1E_FILECODE (0xDCA0) -#define PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE (0xDCB0) -#define PROC_CPU_FEATURE_PRESERVEMAILBOX_FILECODE (0xDCC0) - -#define PROC_RECOVERY_CPU_CPURECOVERY_FILECODE (0xDE01) - -#define PROC_HT_FEATURES_HTFEATSETS_FILECODE (0xE001) -#define PROC_HT_FEATURES_HTFEATDYNAMICDISCOVERY_FILECODE (0xE002) -#define PROC_HT_FEATURES_HTFEATGANGING_FILECODE (0xE003) -#define PROC_HT_FEATURES_HTFEATNONCOHERENT_FILECODE (0xE004) -#define PROC_HT_FEATURES_HTFEATOPTIMIZATION_FILECODE (0xE005) -#define PROC_HT_FEATURES_HTFEATROUTING_FILECODE (0xE006) -#define PROC_HT_FEATURES_HTFEATSUBLINKS_FILECODE (0xE007) -#define PROC_HT_FEATURES_HTFEATTRAFFICDISTRIBUTION_FILECODE (0xE008) -#define PROC_HT_FEATURES_HTIDS_FILECODE (0xE009) -#define PROC_HT_HTFEAT_FILECODE (0xE021) -#define PROC_HT_HTINTERFACE_FILECODE (0xE022) -#define PROC_HT_HTINTERFACECOHERENT_FILECODE (0xE023) -#define PROC_HT_HTINTERFACEGENERAL_FILECODE (0xE024) -#define PROC_HT_HTINTERFACENONCOHERENT_FILECODE (0xE025) -#define PROC_HT_HTMAIN_FILECODE (0xE026) -#define PROC_HT_HTNOTIFY_FILECODE (0xE027) -#define PROC_HT_HTGRAPH_HTGRAPH_FILECODE (0xE028) -#define PROC_HT_HTNB_FILECODE (0xE081) -#define PROC_HT_NBCOMMON_HTNBCOHERENT_FILECODE (0xE082) -#define PROC_HT_NBCOMMON_HTNBNONCOHERENT_FILECODE (0xE083) -#define PROC_HT_NBCOMMON_HTNBOPTIMIZATION_FILECODE (0xE084) -#define PROC_HT_NBCOMMON_HTNBUTILITIES_FILECODE (0xE085) -#define PROC_HT_FAM10_HTNBFAM10_FILECODE (0xE0C1) -#define PROC_HT_FAM10_HTNBCOHERENTFAM10_FILECODE (0xE0C2) -#define PROC_HT_FAM10_HTNBNONCOHERENTFAM10_FILECODE (0xE0C3) -#define PROC_HT_FAM10_HTNBOPTIMIZATIONFAM10_FILECODE (0xE0C4) -#define PROC_HT_FAM10_HTNBSYSTEMFAM10_FILECODE (0xE0C5) -#define PROC_HT_FAM10_HTNBUTILITIESFAM10_FILECODE (0xE0C6) -#define PROC_HT_FAM12_HTNBFAM12_FILECODE (0xE101) -#define PROC_HT_FAM12_HTNBUTILITIESFAM12_FILECODE (0xE102) -#define PROC_HT_FAM14_HTNBFAM14_FILECODE (0xE141) -#define PROC_HT_FAM14_HTNBUTILITIESFAM14_FILECODE (0xE142) -#define PROC_HT_FAM15_HTNBFAM15_FILECODE (0xE181) -#define PROC_HT_FAM15_HTNBCOHERENTFAM15_FILECODE (0xE182) -#define PROC_HT_FAM15_HTNBNONCOHERENTFAM15_FILECODE (0xE183) -#define PROC_HT_FAM15_HTNBOPTIMIZATIONFAM15_FILECODE (0xE184) -#define PROC_HT_FAM15_HTNBSYSTEMFAM15_FILECODE (0xE185) -#define PROC_HT_FAM15_HTNBUTILITIESFAM15_FILECODE (0xE186) - -#define PROC_RECOVERY_HT_HTINITRECOVERY_FILECODE (0xE302) -#define PROC_RECOVERY_HT_HTINITRESET_FILECODE (0xE301) - -#define PROC_IDS_CONTROL_IDSCTRL_FILECODE (0xE801) -#define PROC_IDS_CONTROL_IDSLIB_FILECODE (0xE802) -#define PROC_IDS_DEBUG_IDSDEBUG_FILECODE (0xE803) -#define PROC_IDS_PERF_IDSPERF_FILECODE (0xE804) -#define PROC_IDS_FAMILY_0X10_IDSF10ALLSERVICE_FILECODE (0xE805) -#define PROC_IDS_FAMILY_0X10_BL_IDSF10BLSERVICE_FILECODE (0xE806) -#define PROC_IDS_FAMILY_0X10_DA_IDSF10DASERVICE_FILECODE (0xE807) -#define PROC_IDS_FAMILY_0X10_HY_IDSF10HYSERVICE_FILECODE (0xE808) -#define PROC_IDS_FAMILY_0X10_RB_IDSF10RBSERVICE_FILECODE (0xE809) -#define PROC_IDS_FAMILY_0X12_IDSF12ALLSERVICE_FILECODE (0xE80A) -#define PROC_IDS_FAMILY_0X14_IDSF14ALLSERVICE_FILECODE (0xE80B) -#define PROC_IDS_FAMILY_0X15_IDSF15ALLSERVICE_FILECODE (0xE80C) - -#define PROC_IDS_DEBUG_IDSIDTTABLE_FILECODE (0xE80D) -#define PROC_IDS_CONTROL_IDSNVTOCMOS_FILECODE (0xE80E) - -///0xE820 ~ 0xE840 is reserved for ids extend module - -#define PROC_MEM_ARDK_MA_FILECODE (0xF001) -#define PROC_MEM_ARDK_DR_MARDR2_FILECODE (0xF002) -#define PROC_MEM_ARDK_DR_MARDR3_FILECODE (0xF003) -#define PROC_MEM_ARDK_HY_MARHY3_FILECODE (0xF004) -#define PROC_MEM_ARDK_LN_MASLN3_FILECODE (0xF005) -#define PROC_MEM_ARDK_DR_MAUDR3_FILECODE (0xF006) -#define PROC_MEM_ARDK_HY_MAUHY3_FILECODE (0xF007) -#define PROC_MEM_ARDK_LN_MAULN3_FILECODE (0xF008) -#define PROC_MEM_ARDK_DA_MAUDA3_FILECODE (0xF009) -#define PROC_MEM_ARDK_DA_MASDA2_FILECODE (0xF00A) -#define PROC_MEM_ARDK_DA_MASDA3_FILECODE (0xF00B) -#define PROC_MEM_ARDK_NI_MASNI3_FILECODE (0xF00C) -#define PROC_MEM_ARDK_C32_MARC32_3_FILECODE (0xF00D) -#define PROC_MEM_ARDK_C32_MAUC32_3_FILECODE (0xF00E) -#define PROC_MEM_ARDK_NI_MAUNI3_FILECODE (0xF00F) -#define PROC_MEM_ARDK_ON_MASON3_FILECODE (0xF010) -#define PROC_MEM_ARDK_ON_MAUON3_FILECODE (0xF011) -#define PROC_MEM_ARDK_PH_MASPH3_FILECODE (0xF012) -#define PROC_MEM_ARDK_PH_MAUPH3_FILECODE (0xF013) -#define PROC_MEM_ARDK_OR_MAROR3_FILECODE (0xF014) -#define PROC_MEM_ARDK_OR_MAUOR3_FILECODE (0xF017) -#define PROC_MEM_ARDK_RB_MASRB3_FILECODE (0xF018) -#define PROC_MEM_ARDK_RB_MAURB3_FILECODE (0xF019) - -#define PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE (0xF081) -#define PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE (0xF082) -#define PROC_MEM_FEAT_ECC_MFECC_FILECODE (0xF083) -#define PROC_MEM_FEAT_ECC_MFEMP_FILECODE (0xF085) -#define PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE (0xF086) -#define PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE (0xF088) -#define PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE (0xF089) -#define PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE (0xF08A) -#define PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE (0xF08B) -#define PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE (0xF08C) -#define PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE (0xF08D) -#define PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE (0xF08E) -#define PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE (0xF08F) -#define PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE (0xF091) -#define PROC_MEM_FEAT_S3_MFS3_FILECODE (0xF092) -#define PROC_MEM_FEAT_TABLE_MFTDS_FILECODE (0xF093) - -#define PROC_MEM_MAIN_MDEF_FILECODE (0xF101) -#define PROC_MEM_MAIN_MINIT_FILECODE (0xF102) -#define PROC_MEM_MAIN_MM_FILECODE (0xF103) -#define PROC_MEM_FEAT_DMI_MFDMI_FILECODE (0xF104) -#define PROC_MEM_MAIN_MMECC_FILECODE (0xF105) -#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE (0xF106) -#define PROC_MEM_MAIN_DR_MMFLOWDR_FILECODE (0xF107) -#define PROC_MEM_MAIN_HY_MMFLOWHY_FILECODE (0xF108) -#define PROC_MEM_MAIN_LN_MMFLOWLN_FILECODE (0xF109) -#define PROC_MEM_MAIN_ON_MMFLOWON_FILECODE (0xF10A) -#define PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE (0xF10B) -#define PROC_MEM_MAIN_MMONLINESPARE_FILECODE (0xF10C) -#define PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE (0xF10D) -#define PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE (0xF10E) -#define PROC_MEM_MAIN_MUC_FILECODE (0xF10F) -#define PROC_MEM_MAIN_MMMEMCLR_FILECODE (0xF110) -#define PROC_MEM_MAIN_DA_MMFLOWDA_FILECODE (0xF111) -#define PROC_MEM_MAIN_MMFLOW_FILECODE (0xF112) -#define PROC_MEM_MAIN_MERRHDL_FILECODE (0xF113) -#define PROC_MEM_MAIN_C32_MMFLOWC32_FILECODE (0xF114) -#define PROC_MEM_MAIN_MMLVDDR3_FILECODE (0xF115) -#define PROC_MEM_MAIN_MMUMAALLOC_FILECODE (0xF116) -#define PROC_MEM_MAIN_MMMEMRESTORE_FILECODE (0xF117) -#define PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE (0xF118) -#define PROC_MEM_MAIN_OR_MMFLOWOR_FILECODE (0xF119) -#define PROC_MEM_MAIN_RB_MMFLOWRB_FILECODE (0xF11A) -#define PROC_MEM_MAIN_PH_MMFLOWPH_FILECODE (0xF11B) - -#define PROC_MEM_NB_DR_MNDR_FILECODE (0XF213) -#define PROC_MEM_NB_DR_MNFLOWDR_FILECODE (0XF214) -#define PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE (0XF216) -#define PROC_MEM_NB_DR_MNMCTDR_FILECODE (0XF217) -#define PROC_MEM_NB_DR_MNDCTDR_FILECODE (0XF218) -#define PROC_MEM_NB_DR_MNOTDR_FILECODE (0XF219) -#define PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE (0XF21A) -#define PROC_MEM_NB_DR_MNPROTODR_FILECODE (0XF21C) -#define PROC_MEM_NB_DR_MNS3DR_FILECODE (0XF21D) -#define PROC_MEM_NB_DR_MNREGDR_FILECODE (0XF21E) -#define PROC_MEM_NB_RB_MNRB_FILECODE (0XF220) -#define PROC_MEM_NB_RB_MNFLOWRB_FILECODE (0XF221) -#define PROC_MEM_NB_RB_MNS3RB_FILECODE (0XF222) -#define PROC_MEM_NB_RB_MNIDENDIMMRB_FILECODE (0XF223) -#define PROC_MEM_NB_HY_MNFLOWHY_FILECODE (0XF233) -#define PROC_MEM_NB_HY_MNHY_FILECODE (0XF235) -#define PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE (0XF236) -#define PROC_MEM_NB_HY_MNMCTHY_FILECODE (0XF237) -#define PROC_MEM_NB_HY_MNDCTHY_FILECODE (0XF238) -#define PROC_MEM_NB_HY_MNOTHY_FILECODE (0XF239) -#define PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE (0XF23A) -#define PROC_MEM_NB_HY_MNPHYHY_FILECODE (0XF23B) -#define PROC_MEM_NB_HY_MNPROTOHY_FILECODE (0XF23C) -#define PROC_MEM_NB_HY_MNS3HY_FILECODE (0XF23D) -#define PROC_MEM_NB_HY_MNREGHY_FILECODE (0XF23E) -#define PROC_MEM_NB_ON_MNON_FILECODE (0xF240) -#define PROC_MEM_NB_ON_MNREGON_FILECODE (0xF241) -#define PROC_MEM_NB_ON_MNDCTON_FILECODE (0xF242) -#define PROC_MEM_NB_ON_MNIDENDIMMON_FILECODE (0xF244) -#define PROC_MEM_NB_ON_MNMCTON_FILECODE (0xF245) -#define PROC_MEM_NB_ON_MNOTON_FILECODE (0xF246) -#define PROC_MEM_NB_ON_MNPHYON_FILECODE (0xF247) -#define PROC_MEM_NB_ON_MNS3ON_FILECODE (0xF248) -#define PROC_MEM_NB_ON_MNFLOWON_FILECODE (0xF249) -#define PROC_MEM_NB_ON_MNPROTOON_FILECODE (0xF24A) -#define PROC_MEM_NB_LN_MNDCTLN_FILECODE (0XF252) -#define PROC_MEM_NB_LN_MNFLOWLN_FILECODE (0XF253) -#define PROC_MEM_NB_LN_MNIDENDIMMLN_FILECODE (0XF254) -#define PROC_MEM_NB_LN_MNMCTLN_FILECODE (0XF255) -#define PROC_MEM_NB_LN_MNOTLN_FILECODE (0XF256) -#define PROC_MEM_NB_LN_MNPHYLN_FILECODE (0XF257) -#define PROC_MEM_NB_LN_MNPROTOLN_FILECODE (0XF258) -#define PROC_MEM_NB_LN_MNLN_FILECODE (0XF259) -#define PROC_MEM_NB_LN_MNS3LN_FILECODE (0XF25A) -#define PROC_MEM_NB_LN_MNREGLN_FILECODE (0XF25B) -#define PROC_MEM_NB_DA_MNDA_FILECODE (0XF260) -#define PROC_MEM_NB_DA_MNFLOWDA_FILECODE (0XF261) -#define PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE (0XF263) -#define PROC_MEM_NB_DA_MNMCTDA_FILECODE (0XF264) -#define PROC_MEM_NB_DA_MNDCTDA_FILECODE (0XF265) -#define PROC_MEM_NB_DA_MNOTDA_FILECODE (0XF266) -#define PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE (0XF267) -#define PROC_MEM_NB_DA_MNPROTODA_FILECODE (0XF269) -#define PROC_MEM_NB_DA_MNS3DA_FILECODE (0XF26A) -#define PROC_MEM_NB_DA_MNREGDA_FILECODE (0XF26B) -#define PROC_MEM_NB_C32_MNC32_FILECODE (0XF26C) -#define PROC_MEM_NB_C32_MNDCTC32_FILECODE (0XF26D) -#define PROC_MEM_NB_C32_MNFLOWC32_FILECODE (0XF26E) -#define PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE (0XF26F) -#define PROC_MEM_NB_C32_MNMCTC32_FILECODE (0XF270) -#define PROC_MEM_NB_C32_MNOTC32_FILECODE (0XF271) -#define PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE (0XF272) -#define PROC_MEM_NB_C32_MNPHYC32_FILECODE (0XF273) -#define PROC_MEM_NB_C32_MNPROTOC32_FILECODE (0XF274) -#define PROC_MEM_NB_C32_MNS3C32_FILECODE (0XF275) -#define PROC_MEM_NB_C32_MNREGC32_FILECODE (0XF277) -#define PROC_MEM_NB_MN_FILECODE (0XF27C) -#define PROC_MEM_NB_MNDCT_FILECODE (0XF27D) -#define PROC_MEM_NB_MNPHY_FILECODE (0XF27E) -#define PROC_MEM_NB_MNMCT_FILECODE (0XF27F) -#define PROC_MEM_NB_MNS3_FILECODE (0XF280) -#define PROC_MEM_NB_MNFLOW_FILECODE (0XF281) -#define PROC_MEM_NB_MNFEAT_FILECODE (0XF282) -#define PROC_MEM_NB_MNTRAIN2_FILECODE (0XF283) -#define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284) -#define PROC_MEM_NB_MNREG_FILECODE (0XF285) -#define PROC_MEM_NB_NI_MNNI_FILECODE (0XF286) -#define PROC_MEM_NB_NI_MNS3NI_FILECODE (0XF287) -#define PROC_MEM_NB_NI_MNFLOWNI_FILECODE (0XF288) -#define PROC_MEM_NB_PH_MNFLOWPH_FILECODE (0XF289) -#define PROC_MEM_NB_PH_MNPH_FILECODE (0XF28A) -#define PROC_MEM_NB_PH_MNS3PH_FILECODE (0XF28B) -#define PROC_MEM_NB_PH_MNIDENDIMMPH_FILECODE (0XF28C) -#define PROC_MEM_NB_OR_MNFLOWOR_FILECODE (0XF290) -#define PROC_MEM_NB_OR_MNOR_FILECODE (0XF291) -#define PROC_MEM_NB_OR_MNIDENDIMMOR_FILECODE (0XF292) -#define PROC_MEM_NB_OR_MNMCTOR_FILECODE (0XF293) -#define PROC_MEM_NB_OR_MNDCTOR_FILECODE (0XF294) -#define PROC_MEM_NB_OR_MNOTOR_FILECODE (0XF295) -#define PROC_MEM_NB_OR_MNPARTRAINOR_FILECODE (0XF296) -#define PROC_MEM_NB_OR_MNPHYOR_FILECODE (0XF297) -#define PROC_MEM_NB_OR_MNPROTOOR_FILECODE (0XF298) -#define PROC_MEM_NB_OR_MNS3OR_FILECODE (0XF299) -#define PROC_MEM_NB_OR_MNREGOR_FILECODE (0XF29A) - -#define PROC_MEM_PS_MP_FILECODE (0XF401) -#define PROC_MEM_PS_DR_MPRDR3_FILECODE (0XF402) -#define PROC_MEM_PS_HY_MPRHY3_FILECODE (0XF403) -#define PROC_MEM_PS_LN_MPRLN3_FILECODE (0XF404) -#define PROC_MEM_PS_DR_MPSDR3_FILECODE (0XF405) -#define PROC_MEM_PS_HY_MPSHY3_FILECODE (0XF406) -#define PROC_MEM_PS_LN_MPSLN3_FILECODE (0XF407) -#define PROC_MEM_PS_DR_MPUDR3_FILECODE (0XF408) -#define PROC_MEM_PS_HY_MPUHY3_FILECODE (0XF409) -#define PROC_MEM_PS_LN_MPULN3_FILECODE (0XF40A) -#define PROC_MEM_PS_DA_MPUDA3_FILECODE (0XF40B) -#define PROC_MEM_PS_DA_MPSDA2_FILECODE (0XF40C) -#define PROC_MEM_PS_DA_MPSDA3_FILECODE (0XF40D) -#define PROC_MEM_PS_DR_MPRDR2_FILECODE (0XF40E) -#define PROC_MEM_PS_DR_MPUDR2_FILECODE (0XF40F) -#define PROC_MEM_PS_C32_MPRC32_3_FILECODE (0XF410) -#define PROC_MEM_PS_C32_MPUC32_3_FILECODE (0XF411) -#define PROC_MEM_PS_NI_MPSNI3_FILECODE (0XF412) -#define PROC_MEM_PS_NI_MPUNI3_FILECODE (0XF413) -#define PROC_MEM_PS_ON_MPSON3_FILECODE (0XF414) -#define PROC_MEM_PS_ON_MPUON3_FILECODE (0XF415) -#define PROC_MEM_PS_PH_MPSPH3_FILECODE (0XF416) -#define PROC_MEM_PS_PH_MPUPH3_FILECODE (0XF417) -#define PROC_MEM_PS_RB_MPSRB3_FILECODE (0XF418) -#define PROC_MEM_PS_RB_MPURB3_FILECODE (0XF419) -#define PROC_MEM_PS_OR_AM3_MPUORA3_FILECODE (0XF41A) -#define PROC_MEM_PS_OR_AM3_MPSORA3_FILECODE (0XF41B) -#define PROC_MEM_PS_OR_C32_MPRORC3_FILECODE (0XF41C) -#define PROC_MEM_PS_OR_C32_MPUORC3_FILECODE (0XF41D) -#define PROC_MEM_PS_OR_C32_MPLORC3_FILECODE (0XF41E) -#define PROC_MEM_PS_OR_G34_MPRORG3_FILECODE (0XF41F) -#define PROC_MEM_PS_OR_G34_MPUORG3_FILECODE (0XF420) -#define PROC_MEM_PS_OR_G34_MPLORG3_FILECODE (0XF421) -#define PROC_MEM_PS_MPRTT_FILECODE (0XF422) -#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0XF423) -#define PROC_MEM_PS_MPODTPAT_FILECODE (0XF424) -#define PROC_MEM_PS_MPSAO_FILECODE (0XF425) -#define PROC_MEM_PS_MPMR0_FILECODE (0XF426) -#define PROC_MEM_PS_MPRC2IBT_FILECODE (0XF427) -#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0XF428) -#define PROC_MEM_PS_MPLRIBT_FILECODE (0XF429) -#define PROC_MEM_PS_MPLRNPR_FILECODE (0XF42A) -#define PROC_MEM_PS_MPLRNLR_FILECODE (0XF42B) -#define PROC_MEM_PS_OR_MPOR3_FILECODE (0XF42C) - -#define PROC_MEM_TECH_MT_FILECODE (0XF501) -#define PROC_MEM_TECH_MTHDI_FILECODE (0XF502) -#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0XF504) -#define PROC_MEM_TECH_MTTECC_FILECODE (0XF505) -#define PROC_MEM_TECH_MTTHRC_FILECODE (0XF506) -#define PROC_MEM_TECH_MTTML_FILECODE (0XF507) -#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0XF509) -#define PROC_MEM_TECH_MTTSRC_FILECODE (0XF50B) -#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0XF50C) -#define PROC_MEM_TECH_DDR2_MT2_FILECODE (0XF541) -#define PROC_MEM_TECH_DDR2_MTOT2_FILECODE (0XF543) -#define PROC_MEM_TECH_DDR2_MTSPD2_FILECODE (0XF544) -#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0XF581) -#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0XF583) -#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0XF584) -#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0XF585) -#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0XF586) -#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0XF587) -#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588) -#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589) - -#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0XF801) -#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0XF802) -#define PROC_RECOVERY_MEM_MRM_FILECODE (0XF803) -#define PROC_RECOVERY_MEM_MRUC_FILECODE (0XF804) -#define PROC_RECOVERY_MEM_NB_DR_MRNDR_FILECODE (0XF812) -#define PROC_RECOVERY_MEM_NB_DR_MRNMCTDR_FILECODE (0XF813) -#define PROC_RECOVERY_MEM_NB_HY_MRNDCTHY_FILECODE (0XF821) -#define PROC_RECOVERY_MEM_NB_HY_MRNHY_FILECODE (0XF822) -#define PROC_RECOVERY_MEM_NB_HY_MRNMCTHY_FILECODE (0XF823) -#define PROC_RECOVERY_MEM_NB_HY_MRNPROTOHY_FILECODE (0XF825) -#define PROC_RECOVERY_MEM_NB_LN_MRNDCTLN_FILECODE (0XF831) -#define PROC_RECOVERY_MEM_NB_LN_MRNMCTLN_FILECODE (0XF832) -#define PROC_RECOVERY_MEM_NB_LN_MRNLN_FILECODE (0XF833) -#define PROC_RECOVERY_MEM_NB_DA_MRNDA_FILECODE (0XF842) -#define PROC_RECOVERY_MEM_NB_DA_MRNMCTDA_FILECODE (0XF843) -#define PROC_RECOVERY_MEM_NB_NI_MRNNI_FILECODE (0XF845) -#define PROC_RECOVERY_MEM_NB_C32_MRNC32_FILECODE (0XF851) -#define PROC_RECOVERY_MEM_NB_C32_MRNMCTC32_FILECODE (0XF852) -#define PROC_RECOVERY_MEM_NB_C32_MRNPROTOC32_FILECODE (0XF853) -#define PROC_RECOVERY_MEM_NB_ON_MRNDCTON_FILECODE (0xF861) -#define PROC_RECOVERY_MEM_NB_ON_MRNMCTON_FILECODE (0xF862) -#define PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE (0xF863) -#define PROC_RECOVERY_MEM_NB_PH_MRNPH_FILECODE (0xF871) -#define PROC_RECOVERY_MEM_NB_RB_MRNRB_FILECODE (0xF881) -#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0XF8C1) -#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0XF8C2) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0XF8C3) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0XF8C4) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0XF8C5) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0XF8C6) -#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0XF8C7) -#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0XF8C8) -#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0XF8C9) -#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0XF8CA) -#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0XF8CB) -#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0XF8CC) -#define PROC_RECOVERY_MEM_NB_OR_MRNDCTOR_FILECODE (0XF8CD) -#define PROC_RECOVERY_MEM_NB_OR_MRNOR_FILECODE (0XF8CE) -#define PROC_RECOVERY_MEM_NB_OR_MRNMCTOR_FILECODE (0XF8CF) -#define PROC_RECOVERY_MEM_NB_OR_MRNPROTOOR_FILECODE (0XF8D0) -#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0XF8E0) -#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0XF8E1) -#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0XF8E2) -#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0XF8E3) -#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0XF8E4) -#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0XF8E5) -#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0XF8E6) -#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0XF8E7) -#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0XF8E8) -#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0XF8E9) -#define PROC_RECOVERY_MEM_PS_OR_MRPOR3_FILECODE (0XF8EA) -#define PROC_RECOVERY_MEM_PS_OR_AM3_MRPSORA3_FILECODE (0XF8EB) -#define PROC_RECOVERY_MEM_PS_OR_AM3_MRPUORA3_FILECODE (0XF8EC) -#define PROC_RECOVERY_MEM_PS_OR_C32_MRPUORC3_FILECODE (0XF8ED) -#define PROC_RECOVERY_MEM_PS_OR_C32_MRPRORC3_FILECODE (0XF8EE) -#define PROC_RECOVERY_MEM_PS_OR_C32_MRPLORC3_FILECODE (0XF8EF) -#define PROC_RECOVERY_MEM_PS_OR_G34_MRPUORG3_FILECODE (0XF8F0) -#define PROC_RECOVERY_MEM_PS_OR_G34_MRPRORG3_FILECODE (0XF8F1) -#define PROC_RECOVERY_MEM_PS_OR_G34_MRPLORG3_FILECODE (0XF8F2) - -#endif // _FILECODE_H_ diff --git a/src/vendorcode/amd/agesa/Include/GeneralServices.h b/src/vendorcode/amd/agesa/Include/GeneralServices.h deleted file mode 100644 index 14ba10ebb4..0000000000 --- a/src/vendorcode/amd/agesa/Include/GeneralServices.h +++ /dev/null @@ -1,203 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * General Services - * - * Provides Services similar to the external General Services API, except - * suited to use within AGESA components. Socket, Core and PCI identification. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Common - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _GENERAL_SERVICES_H_ -#define _GENERAL_SERVICES_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -#define NUMBER_OF_EVENT_DATA_PARAMS 4 - -/** - * AMD Device id for MMIO check. - */ -#define AMD_DEV_VEN_ID 0x1022 -#define AMD_DEV_VEN_ID_ADDRESS 0 - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ - -/** - * An AGESA Event Log entry. - */ -typedef struct { - AGESA_STATUS EventClass; ///< The severity of the event, its associated AGESA_STATUS. - UINT32 EventInfo; ///< Uniquely identifies the event. - UINT32 DataParam1; ///< Event specific additional data - UINT32 DataParam2; ///< Event specific additional data - UINT32 DataParam3; ///< Event specific additional data - UINT32 DataParam4; ///< Event specific additional data -} AGESA_EVENT; - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -/** - * Get a specified Core's APIC ID. - * - * @param[in] StdHeader Header for library and services. - * @param[in] Socket The Core's Socket. - * @param[in] Core The Core id. - * @param[out] ApicAddress The Core's APIC ID. - * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. - * - * @retval TRUE The core is present, APIC Id valid - * @retval FALSE The core is not present, APIC Id not valid. - */ -BOOLEAN -GetApicId ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT32 Socket, - IN UINT32 Core, - OUT UINT8 *ApicAddress, - OUT AGESA_STATUS *AgesaStatus -); - -/** - * Get Processor Module's PCI Config Space address. - * - * @param[in] StdHeader Header for library and services. - * @param[in] Socket The Core's Socket. - * @param[in] Module The Module in that Processor - * @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0) - * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. - * - * @retval TRUE The core is present, PCI Address valid - * @retval FALSE The core is not present, PCI Address not valid. - */ -BOOLEAN -GetPciAddress ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN UINT32 Socket, - IN UINT32 Module, - OUT PCI_ADDR *PciAddress, - OUT AGESA_STATUS *AgesaStatus -); - -/** - * "Who am I" for the current running core. - * - * @param[in] StdHeader Header for library and services. - * @param[out] Socket The current Core's Socket - * @param[out] Module The current Core's Processor Module - * @param[out] Core The current Core's core id. - * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds. - * - */ -VOID -IdentifyCore ( - IN AMD_CONFIG_PARAMS *StdHeader, - OUT UINT32 *Socket, - OUT UINT32 *Module, - OUT UINT32 *Core, - OUT AGESA_STATUS *AgesaStatus -); - -/** - * A boolean function determine executed CPU is BSP core. - */ -BOOLEAN -IsBsp ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - OUT AGESA_STATUS *AgesaStatus - ); - -/** - * This function logs AGESA events into the event log. - */ -VOID -PutEventLog ( - IN AGESA_STATUS EventClass, - IN UINT32 EventInfo, - IN UINT32 DataParam1, - IN UINT32 DataParam2, - IN UINT32 DataParam3, - IN UINT32 DataParam4, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * This function gets event logs from the circular buffer. - */ -AGESA_STATUS -GetEventLog ( - OUT AGESA_EVENT *EventRecord, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * This function gets event logs from the circular buffer without flushing the entry. - */ -BOOLEAN -PeekEventLog ( - OUT AGESA_EVENT *EventRecord, - IN UINT16 Index, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/*---------------------------------------------------------------------------------------*/ -/** - * This routine programs the registers necessary to get the PCI MMIO mechanism - * up and functioning. - */ -VOID -InitializePciMmio ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif // _GENERAL_SERVICES_H_ diff --git a/src/vendorcode/amd/agesa/Include/GnbInterface.h b/src/vendorcode/amd/agesa/Include/GnbInterface.h deleted file mode 100644 index 761cf3af7e..0000000000 --- a/src/vendorcode/amd/agesa/Include/GnbInterface.h +++ /dev/null @@ -1,96 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * GNB API definition. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 37658 $ @e \$Date: 2010-09-09 15:25:38 +0800 (Thu, 09 Sep 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _GNBINTERFACE_H_ -#define _GNBINTERFACE_H_ - -AGESA_STATUS -GnbInitAtReset ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -AGESA_STATUS -GnbInitAtEarly ( - IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr - ); - -AGESA_STATUS -GnbInitAtPost ( - IN OUT AMD_POST_PARAMS *PostParamsPtr - ); - -VOID -GnbInitDataStructAtEnvDef ( - IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr, - IN AMD_ENV_PARAMS *EnvParamsPtr - ); - -AGESA_STATUS -GnbInitAtEnv ( - IN AMD_ENV_PARAMS *EnvParamsPtr - ); - -AGESA_STATUS -GnbInitAtMid ( - IN OUT AMD_MID_PARAMS *MidParamsPtr - ); - -AGESA_STATUS -GnbInitAtLate ( - IN OUT AMD_LATE_PARAMS *LateParamsPtr - ); - -AGESA_STATUS -GnbInitAtPostAfterDram ( - IN OUT AMD_POST_PARAMS *PostParamsPtr - ); - -AGESA_STATUS -AmdGnbRecovery ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#endif diff --git a/src/vendorcode/amd/agesa/Include/GnbInterfaceStub.h b/src/vendorcode/amd/agesa/Include/GnbInterfaceStub.h deleted file mode 100644 index 0b3ff08223..0000000000 --- a/src/vendorcode/amd/agesa/Include/GnbInterfaceStub.h +++ /dev/null @@ -1,232 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 37658 $ @e \$Date: 2010-09-09 15:25:38 +0800 (Thu, 09 Sep 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Reset Stub - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS Always succeeds - */ - -AGESA_STATUS -GnbInitAtReset ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Early Stub - * - * - * - * @param[in,out] EarlyParamsPtr Pointer to early configuration params. - * @retval AGESA_STATUS Always succeeds - */ - -AGESA_STATUS -GnbInitAtEarly ( - IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr - ) -{ - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Default constructor of GNB configuration at Env - * - * - * - * @param[in] GnbEnvConfigPtr Pointer to gnb env configuration params. - * @param[in] EnvParamsPtr Pointer to env configuration params. - */ -VOID -GnbInitDataStructAtEnvDef ( - IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr, - IN AMD_ENV_PARAMS *EnvParamsPtr - ) -{ - -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Env - * - * - * - * @param[in] EnvParamsPtr Pointer to env configuration params. -* @retval AGESA_STATUS Always succeeds - */ - -AGESA_STATUS -GnbInitAtEnv ( - IN AMD_ENV_PARAMS *EnvParamsPtr - ) -{ - - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Post - * - * - * - * @param[in,out] PostParamsPtr Pointer to Post configuration params. - * @retval AGESA_STATUS Always succeeds - */ - -AGESA_STATUS -GnbInitAtPost ( - IN OUT AMD_POST_PARAMS *PostParamsPtr - ) -{ - - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Mid post - * - * - * - * @param[in,out] MidParamsPtr Pointer to mid configuration params. - * @retval AGESA_STATUS Always succeeds - */ - -AGESA_STATUS -GnbInitAtMid ( - IN OUT AMD_MID_PARAMS *MidParamsPtr - ) -{ - - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Late post - * - * - * - * @param[in,out] LateParamsPtr Pointer to late configuration params. - * @retval AGESA_STATUS Always succeeds - */ - -AGESA_STATUS -GnbInitAtLate ( - IN OUT AMD_LATE_PARAMS *LateParamsPtr - ) -{ - - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * AmdGnbRecovery - * - * - * - * @param[in] StdHeader Standard configuration header - * @retval AGESA_STATUS Always succeeds - */ -AGESA_STATUS -AmdGnbRecovery ( - IN AMD_CONFIG_PARAMS *StdHeader - ) -{ - return AGESA_SUCCESS; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Init GNB at Post after DRAM init - * - * - * - * @param[in] PostParamsPtr Pointer to post configuration parameters - * @retval Initialization status. - */ - -AGESA_STATUS -GnbInitAtPostAfterDram ( - IN OUT AMD_POST_PARAMS *PostParamsPtr - ) -{ - return AGESA_SUCCESS; -} \ No newline at end of file diff --git a/src/vendorcode/amd/agesa/Include/Ids.h b/src/vendorcode/amd/agesa/Include/Ids.h deleted file mode 100644 index cbd0b131be..0000000000 --- a/src/vendorcode/amd/agesa/Include/Ids.h +++ /dev/null @@ -1,927 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD IDS Routines - * - * Contains AMD AGESA Integrated Debug Macros - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: IDS - * @e \$Revision: 38634 $ @e \$Date: 2010-09-27 21:39:01 +0800 (Mon, 27 Sep 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - /* Macros to aid debugging */ - /* These definitions expand to zero (0) bytes of code when disabled */ - -#ifndef _IDS_H_ -#define _IDS_H_ - -#undef FALSE -#undef TRUE -#define FALSE 0 -#define TRUE 1 -// Proto type for optionsids.h -typedef UINT32 IDS_STATUS; ///< Status of IDS function. -#define IDS_SUCCESS ((IDS_STATUS) 0x00000000) ///< IDS Function is Successful. -#define IDS_UNSUPPORTED ((IDS_STATUS) 0xFFFFFFFF) ///< IDS Function is not existed. - -#define IDS_STRINGIZE(a) #a ///< for define stringize macro -/** - * IDS Option Hook Points - * - * These are the values to indicate hook point in AGESA for IDS Options. - * - */ -typedef enum { //vv- for debug reference only - IDS_INIT_EARLY_BEFORE, ///< 00 Option Hook Point before AGESA function AMD_INIT_EARLY. - ///< IDS Object is initialized. - ///< Override CPU Core Leveling Mode. - ///< Set P-State in Post - IDS_INIT_EARLY_AFTER, ///< 01 Option Hook Point after AGESA function AMD_INIT_EARLY. - IDS_INIT_LATE_BEFORE, ///< 02 Option Hook Point before AGESA function AMD_INIT_LATE. - ///< It will be used to control the following tables. - ///< ACPI P-State Table (_PSS, XPSS, _PCT, _PSD, _PPC) - ///< ACPI SRAT Table - ///< ACPI SLIT Table - ///< ACPI WHEA Table - ///< DMI Table - IDS_INIT_LATE_AFTER, ///< 03 Option Hook Point after AGESA function AMD_INIT_LATE. - IDS_INIT_MID_BEFORE, ///< 04 Option Hook Point before AGESA function AMD_INIT_MID. - IDS_INIT_MID_AFTER, ///< 05 Option Hook Point after AGESA function AMD_INIT_MID. - IDS_INIT_POST_BEFORE, ///< 06 Option Hook Point before AGESA function AMD_INIT_POST. - ///< Control Interleaving and DRAM memory hole - ///< Override the setting of ECC Control - ///< Override the setting of Online Spare Rank - IDS_INIT_POST_AFTER, ///< 07 Option Hook Point after AGESA function AMD_INIT_POST. - IDS_INIT_RESET_BEFORE, ///< 08 Option Hook Point before AGESA function AMD_INIT_RESET. - IDS_INIT_RESET_AFTER, ///< 09 Option Hook Point after AGESA function AMD_INIT_RESET. - IDS_INIT_POST_MID, ///< 0a Option Hook Point after AGESA function AMD_INIT_POST. - IDS_BEFORE_S3_SAVE, ///< 0b override any settings before S3 save. - IDS_BEFORE_S3_RESTORE, ///< 0c override any settings before S3 restore - IDS_AFTER_S3_SAVE, ///< 0d Override any settings after S3 save - IDS_AFTER_S3_RESTORE, ///< 0e Override any settings after S3 restore - IDS_BEFORE_DQS_TRAINING, ///< 0f override any settings before DQS training - IDS_BEFORE_DRAM_INIT, ///< 10 override any settings before Dram initialization - IDS_BEFORE_MEM_FREQ_CHG, ///< 11 override settings before MemClk frequency change - IDS_BEFORE_WARM_RESET , ///< 12 Override PCI or MSR Registers Before Warm Reset - IDS_BEFORE_MEM_INIT, ///< 13 Override PCI or MSR Registers Before Memory Init - IDS_BEFORE_PCI_INIT, ///< 14 Override PCI or MSR Registers Before PCI Init - IDS_BEFORE_OS, ///< 15 Override PCI or MSR Registers Before booting to OS - IDS_UCODE, ///< 16 Enable or Disable microcode patching - IDS_BEFORE_AP_EARLY_HALT, ///< 17 Option Hook Point before AP early halt - - IDS_PLATFORM_RSVD1 = 0x38, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD2 = 0x39, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD3 = 0x3a, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD4 = 0x3b, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD5 = 0x3c, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD6 = 0x3d, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD7 = 0x3e, ///< from 0x38 to 0x3f will reserved for platform used - IDS_PLATFORM_RSVD8 = 0x3f, ///< from 0x38 to 0x3f will reserved for platform used - - // All the above timing point is used by BVM, their value should never be changed - IDS_HT_CONTROL, ///< 40 Override the setting of HT Link Control - IDS_HT_TRISTATE, ///< 41 Enable or Disable HT Tri-state during an LDTSTP# - IDS_INIT_DRAM_TABLE, ///< 42 Generate override table for Dram Timing - ///< Dram Controller, Drive Strength and DQS Timing - IDS_GET_DRAM_TABLE, ///< 43 Generate override table for Dram Timing - IDS_GANGING_MODE, ///< 44 override Memory Mode Unganged - IDS_POWERDOWN_MODE, ///< 45 override Power Down Mode - IDS_BURST_LENGTH32, ///< 46 override Burst Length32 - IDS_ALL_MEMORY_CLOCK, ///< 47 override All Memory Clks Enable - IDS_ECC, ///< 48 override ECC parameter - IDS_ECCSYMBOLSIZE, ///< 49 override ECC symbol size - IDS_CPU_Early_Override, ///< 4a override CPU early parameter - IDS_CACHE_FLUSH_HLT, ///< 4b override Cache Flush Hlt - IDS_CHANNEL_INTERLEAVE, ///< 4c override Channel Interleave - IDS_MEM_ERROR_RECOVERY, ///< 4d override memory error recovery - IDS_MEM_RETRAIN_TIMES, ///< 4e override memory retrain times - IDS_MEM_SIZE_OVERLAY, ///< 4f Override the syslimit - IDS_HT_ASSIST, ///< 50 Override Probe Filter - IDS_CHECK_NEGATIVE_WL, ///< 51 Check for negative write leveling result - IDS_DLL_SHUT_DOWN, ///< 52 Check for Dll Shut Down - IDS_POR_MEM_FREQ, ///< 53 Entry to enable/disable MemClk frequency enforcement - IDS_PHY_DLL_STANDBY_CTRL, ///< 54 Enable/Disable Phy DLL standby feature - IDS_PLATFORMCFG_OVERRIDE, ///< 55 Hook for Override PlatformConfig structure - IDS_LOADCARD_ERROR_RECOVERY, ///< 56 Special error handling for load card support - IDS_MEM_IGNORE_ERROR, ///< 57 Ignore error and do not do fatal exit in memory - IDS_GNB_SMU_SERVICE_CONFIG, ///< 58 Config GNB SMU service - IDS_GNB_ORBDYNAMIC_WAKE, ///< 59 config GNB dynamic wake - IDS_GNB_PLATFORMCFG_OVERRIDE, ///< 5a override ids gnb platform config - IDS_GNB_LCLK_DPM_EN, ///< 5b override GNB LCLK DPM configuration - IDS_GNB_LCLK_DEEP_SLEEP, ///< 5c override GNB LCLK DPM deep sleep - IDS_GNB_CLOCK_GATING, ///< 5d Override GNB Clock gating config - IDS_NB_PSTATE_DIDVID, ///< 5e Override NB P-state settings - IDS_CPB_CTRL, ///< 5f Config the Core peformance boost feature - IDS_HTC_CTRL, ///< 60 Hook for Hardware Thermal Control - IDS_CC6_WORKAROUND, ///< 61 Hook for skip CC6 work around - IDS_MEM_MR0, ///< 62 Hook for override Memory Mr0 register - IDS_REG_TABLE, ///< 63 Hook for add IDS register table to the loop - IDS_NBBUFFERALLOCATIONATEARLY, ///< 64 Hook for override North bridge bufer allocation - IDS_BEFORE_S3_SPECIAL, ///< 65 Hook to bypass S3 special functions - IDS_SET_PCI_REGISTER_ENTRY, ///< 66 Hook to SetRegisterForPciEntry - IDS_ERRATUM463_WORKAROUND, ///< 67 Hook to Erratum 463 workaround - IDS_BEFORE_MEMCLR, ///< 68 Hook before set Memclr bit - IDS_OVERRIDE_IO_CSTATE, ///< 69 Hook for override io C-state setting - IDS_NBPSDIS_OVERRIDE, ///< 6a Hook for override NB pstate disable setting - IDS_NBPS_REG_OVERRIDE, ///< 6b Hook for override Memory NBps reg - IDS_LOW_POWER_PSTATE, ///< 6c Hook for disalbe Low power_Pstates feature - IDS_CST_CREATE, ///< 6d Hook for create _CST - IDS_CST_SIZE, ///< 6e Hook for get _CST size - IDS_ENFORCE_VDDIO, ///< 6f Hook to override VDDIO - IDS_SKIP_PERFORMANCE_OPT, ///< 70 Hook to skip performance optimization - IDS_INIT_MEM_REG_TABLE, ///< 71 Hook for init memory register table - IDS_SKIP_FUSED_MAX_RATE ///< 72 Hook to skip fused max rate cap -} AGESA_IDS_OPTION; - -#include "OptionsIds.h" -#include "Filecode.h" - -/* Initialize IDS controls */ -#ifndef IDSOPT_IDS_ENABLED - #define IDSOPT_IDS_ENABLED FALSE -#endif - -#ifndef IDSOPT_CONTROL_ENABLED - #define IDSOPT_CONTROL_ENABLED FALSE -#endif - -#ifndef IDSOPT_TRACING_ENABLED - #define IDSOPT_TRACING_ENABLED FALSE -#endif - -#ifndef IDSOPT_TRACE_USER_OPTIONS - #define IDSOPT_TRACE_USER_OPTIONS TRUE -#endif - -#ifndef IDSOPT_PERF_ANALYSIS - #define IDSOPT_PERF_ANALYSIS FALSE -#endif - -#ifndef IDSOPT_HEAP_CHECKING - #define IDSOPT_HEAP_CHECKING FALSE -#endif - -#ifndef IDSOPT_ASSERT_ENABLED - #define IDSOPT_ASSERT_ENABLED FALSE -#endif - -#ifndef IDSOPT_ERROR_TRAP_ENABLED - #define IDSOPT_ERROR_TRAP_ENABLED FALSE -#endif - -#ifndef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE -#endif - -#ifndef IDSOPT_DEBUG_CODE_ENABLED - #define IDSOPT_DEBUG_CODE_ENABLED FALSE -#endif - -#ifndef IDSOPT_C_OPTIMIZATION_DISABLED - #define IDSOPT_C_OPTIMIZATION_DISABLED FALSE -#endif - -#if IDSOPT_IDS_ENABLED == FALSE - #undef IDSOPT_CONTROL_ENABLED - #undef IDSOPT_TRACING_ENABLED - #undef IDSOPT_PERF_ANALYSIS - #undef IDSOPT_HEAP_CHECKING - #undef IDSOPT_ASSERT_ENABLED - #undef IDSOPT_ERROR_TRAP_ENABLED - #undef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - #undef IDSOPT_DEBUG_CODE_ENABLED - #undef IDSOPT_TRACE_USER_OPTIONS - - #define IDSOPT_CONTROL_ENABLED FALSE - #define IDSOPT_TRACING_ENABLED FALSE - #define IDSOPT_PERF_ANALYSIS FALSE - #define IDSOPT_HEAP_CHECKING FALSE - #define IDSOPT_ASSERT_ENABLED FALSE - #define IDSOPT_ERROR_TRAP_ENABLED FALSE - #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE - #define IDSOPT_DEBUG_CODE_ENABLED FALSE - #define IDSOPT_TRACE_USER_OPTIONS FALSE -#endif - -/** - * Make a Progress Report to the User. - * - * This Macro is always enabled. The default action is to write the TestPoint value - * to an I/O port. The I/O port is 8 bits in size and the default address is 0x80. - * IBVs can change AGESA's default port by defining IDS_DEBUG_PORT to desired port - * in OptionsIds.h in their build tip. - * - * @param[in] TestPoint The value for display indicating progress - * @param[in,out] StdHeader Pointer of AMD_CONFIG_PARAMS - * - **/ - -#define AGESA_TESTPOINT(TestPoint, StdHeader) - -#ifndef IDS_DEBUG_PORT - #define IDS_DEBUG_PORT 0x80 -#endif - -/** - * @def STOP_HERE - * (macro) - Causes program to halt. This is @b only for use during active debugging . - * - * Causes the program to halt and display the file number of the source of the - * halt (displayed in decimal). - * - **/ -#if IDSOPT_IDS_ENABLED == TRUE - #ifdef STOP_CODE - #undef STOP_CODE - #endif - #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \ - ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ - (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) - #define STOP_HERE -#else - #define STOP_HERE -#endif - -/** - * @def ASSERT - * Test an assertion that the given statement is True. - * - * The statement is evaluated to a boolean value. If the statement is True, - * then no action is taken (no error). If the statement is False, a error stop - * is generated to halt the program. Used for testing for fatal errors that - * must be resolved before production. This is used to do parameter checks, - * bounds checking, range checks and 'sanity' checks. - * - * @param[in] conditional Assert that evaluating this conditional results in TRUE. - * - **/ -#ifndef ASSERT - #if IDSOPT_ASSERT_ENABLED == TRUE - #ifdef STOP_CODE - #undef STOP_CODE - #endif - #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \ - ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ - (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) - - #define ASSERT(conditional) - #else - #define ASSERT(conditional) - #endif -#endif - -#if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE - #undef IDSOPT_ERROR_TRAP_ENABLED - #define IDSOPT_ERROR_TRAP_ENABLED TRUE - #define IDS_CAR_CORRUPTION_CHECK(StdHeader) -#else - #define IDS_CAR_CORRUPTION_CHECK(StdHeader) -#endif -/** - * @def DEBUG_CODE - * Make the code active when IDSOPT_DEBUG_CODE_ENABLED enable - * - */ -#ifndef DEBUG_CODE - #if IDSOPT_DEBUG_CODE_ENABLED == TRUE - #define DEBUG_CODE(Code) - #else - #define DEBUG_CODE(Code) - #endif -#endif - -/** - * @def IDS_ERROR_TRAP - * Trap AGESA Error events with stop code display. - * - * Works similarly to use of "ASSERT (FALSE);" - * - */ -#if IDSOPT_ERROR_TRAP_ENABLED == TRUE - #ifdef STOP_CODE - #undef STOP_CODE - #endif - #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \ - ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \ - (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000)) - - #define IDS_ERROR_TRAP -#else - #define IDS_ERROR_TRAP -#endif - -///give the extended Macro default value -#ifndef __IDS_EXTENDED__ - #define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS - #define IDS_INITIAL_F10_PM_STEP - #define IDS_INITIAL_F12_PM_STEP - #define IDS_INITIAL_F14_PM_STEP - #define IDS_INITIAL_F15_PM_STEP - #define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader) - #define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader) - #define IDS_EXTENDED_HEAP_SIZE 0 - #define IDS_EXT_INCLUDE_F10(file) - #define IDS_EXT_INCLUDE_F12(file) - #define IDS_EXT_INCLUDE_F14(file) - #define IDS_EXT_INCLUDE_F15(file) - #define IDS_EXT_INCLUDE(file) -#endif - -#ifndef IDS_NUM_NV_ITEM - #define IDS_NUM_NV_ITEM (IDS_NUM_EXT_NV_ITEM) -#endif - -#if IDSOPT_CONTROL_ENABLED == TRUE - #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader) - - #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) -#else - #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader) - - #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) -#endif - -/** - * Macro to add a *skip* hook for IDS options - * - * The default minimal action is to do nothing and there is no any code to increase. - * For debug environments, IDS dispatcher function will be called to perform - * the detailed action and to skip AGESA code if necessary. - * - * @param[in] IdsOption IDS Option ID for this hook point - * @param[in, out] DataPtr Data Pointer to override - * @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS - * - * - **/ - -#if IDSOPT_CONTROL_ENABLED == TRUE - #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader) -#else - #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader) -#endif - -/** - * Macro to add a heap manager routine - * - * when memory is allocated the heap manager actually allocates two extra dwords of data, - * one dword buffer before the actual memory, and one dword afterwards. - * a complete heap walk and check to be performed at any time. - * it would ASSERT if the heap is corrupt - * - * @param[in] StdHeader Pointer of AMD_CONFIG_PARAMS - * - * - **/ - -// Heap debug feature -#define SENTINEL_BEFORE_VALUE 0x64616548 // "Head" -#define SENTINEL_AFTER_VALUE 0x6C696154 // "Tail" -#if IDSOPT_IDS_ENABLED == TRUE - #if IDSOPT_HEAP_CHECKING == TRUE - #define SIZE_OF_SENTINEL 0 - #define NUM_OF_SENTINEL 0 - #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) - #define SET_SENTINEL_AFTER(NodePtr) - #define Heap_Check(stdheader) - #else - #define SIZE_OF_SENTINEL 0 - #define NUM_OF_SENTINEL 0 - #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) - #define SET_SENTINEL_AFTER(NodePtr) - #define Heap_Check(stdheader) - #endif -#else - #define SIZE_OF_SENTINEL 0 - #define NUM_OF_SENTINEL 0 - #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) - #define SET_SENTINEL_AFTER(NodePtr) - #define Heap_Check(stdheader) -#endif - - - //Note a is from 0 to 63 -#define DEBUG_PRINT_SHIFT(a) ((UINT64)1 << a) -//If you change the Bitmap definition below, please change the Hash in ParseFilter of hdtout2008.pl accordingly -//Memory Masks -#define MEM_SETREG DEBUG_PRINT_SHIFT (0) -#define MEM_GETREG DEBUG_PRINT_SHIFT (1) -#define MEM_FLOW DEBUG_PRINT_SHIFT (2) -#define MEM_STATUS DEBUG_PRINT_SHIFT (3) -#define MEMORY_TRACE_RSV1 DEBUG_PRINT_SHIFT (4) -#define MEMORY_TRACE_RSV2 DEBUG_PRINT_SHIFT (5) -#define MEMORY_TRACE_RSV3 DEBUG_PRINT_SHIFT (6) -#define MEMORY_TRACE_RSV4 DEBUG_PRINT_SHIFT (7) -#define MEMORY_TRACE_RSV5 DEBUG_PRINT_SHIFT (8) -#define MEMORY_TRACE_RSV6 DEBUG_PRINT_SHIFT (9) - - - -//CPU Masks -#define CPU_TRACE DEBUG_PRINT_SHIFT (10) -#define CPU_TRACE_RSV1 DEBUG_PRINT_SHIFT (11) -#define CPU_TRACE_RSV2 DEBUG_PRINT_SHIFT (12) -#define CPU_TRACE_RSV3 DEBUG_PRINT_SHIFT (13) -#define CPU_TRACE_RSV4 DEBUG_PRINT_SHIFT (14) -#define CPU_TRACE_RSV5 DEBUG_PRINT_SHIFT (15) -#define CPU_TRACE_RSV6 DEBUG_PRINT_SHIFT (16) -#define CPU_TRACE_RSV7 DEBUG_PRINT_SHIFT (17) -#define CPU_TRACE_RSV8 DEBUG_PRINT_SHIFT (18) -#define CPU_TRACE_RSV9 DEBUG_PRINT_SHIFT (19) - -//GNB Masks -#define GNB_TRACE DEBUG_PRINT_SHIFT (20) -#define PCIE_MISC DEBUG_PRINT_SHIFT (21) -#define PCIE_PORTREG_TRACE DEBUG_PRINT_SHIFT (22) -#define PCIE_HOSTREG_TRACE DEBUG_PRINT_SHIFT (23) -#define GNB_TRACE_RSV2 DEBUG_PRINT_SHIFT (24) -#define NB_MISC DEBUG_PRINT_SHIFT (25) -#define GNB_TRACE_RSV3 DEBUG_PRINT_SHIFT (26) -#define GFX_MISC DEBUG_PRINT_SHIFT (27) -#define NB_SMUREG_TRACE DEBUG_PRINT_SHIFT (28) -#define GNB_TRACE_RSV1 DEBUG_PRINT_SHIFT (29) - -//HT Masks -#define HT_TRACE DEBUG_PRINT_SHIFT (30) -#define HT_TRACE_RSV1 DEBUG_PRINT_SHIFT (31) -#define HT_TRACE_RSV2 DEBUG_PRINT_SHIFT (32) -#define HT_TRACE_RSV3 DEBUG_PRINT_SHIFT (33) -#define HT_TRACE_RSV4 DEBUG_PRINT_SHIFT (34) -#define HT_TRACE_RSV5 DEBUG_PRINT_SHIFT (35) -#define HT_TRACE_RSV6 DEBUG_PRINT_SHIFT (36) -#define HT_TRACE_RSV7 DEBUG_PRINT_SHIFT (37) -#define HT_TRACE_RSV8 DEBUG_PRINT_SHIFT (38) -#define HT_TRACE_RSV9 DEBUG_PRINT_SHIFT (39) - -//FCH Masks -#define FCH_TRACE DEBUG_PRINT_SHIFT (40) -#define FCH_TRACE_RSV1 DEBUG_PRINT_SHIFT (41) -#define FCH_TRACE_RSV2 DEBUG_PRINT_SHIFT (42) -#define FCH_TRACE_RSV3 DEBUG_PRINT_SHIFT (43) -#define FCH_TRACE_RSV4 DEBUG_PRINT_SHIFT (44) -#define FCH_TRACE_RSV5 DEBUG_PRINT_SHIFT (45) -#define FCH_TRACE_RSV6 DEBUG_PRINT_SHIFT (46) -#define FCH_TRACE_RSV7 DEBUG_PRINT_SHIFT (47) -#define FCH_TRACE_RSV8 DEBUG_PRINT_SHIFT (48) -#define FCH_TRACE_RSV9 DEBUG_PRINT_SHIFT (49) - -//Other Masks -#define MAIN_FLOW DEBUG_PRINT_SHIFT (50) -#define EVENT_LOG DEBUG_PRINT_SHIFT (51) -#define PERFORMANCE_ANALYSE DEBUG_PRINT_SHIFT (52) - -//Ids Masks -#define IDS_TRACE DEBUG_PRINT_SHIFT (53) -#define IDS_REG DEBUG_PRINT_SHIFT (54) -#define IDS_TRACE_RSV2 DEBUG_PRINT_SHIFT (55) -#define IDS_TRACE_RSV3 DEBUG_PRINT_SHIFT (56) - -//S3 -#define S3_TRACE DEBUG_PRINT_SHIFT (57) - - -//Reserved -#define TRACE_RSV1 DEBUG_PRINT_SHIFT (58) -#define TRACE_RSV2 DEBUG_PRINT_SHIFT (59) -#define TRACE_RSV3 DEBUG_PRINT_SHIFT (60) -#define TRACE_RSV4 DEBUG_PRINT_SHIFT (61) -#define TRACE_RSV5 DEBUG_PRINT_SHIFT (62) -#define TRACE_RSV6 DEBUG_PRINT_SHIFT (63) - -#define GNB_TRACE_DEFAULT 0 - -#define GNB_TRACE_REG 0 - -#define GNB_TRACE_ALL 0 - -#define CPU_TRACE_ALL 0 - -#define MEMORY_TRACE_ALL 0 - -#define HT_TRACE_ALL 0 - -#define FCH_TRACE_ALL 0 - -#define IDS_TRACE_ALL 0 - -#define OTHER_TRACE_ALL 0 - -#define TRACE_MASK_ALL (0ull) -#ifndef IDS_DEBUG_PRINT_MASK - #define IDS_DEBUG_PRINT_MASK 0 -#endif - - -/** - * Macro to add HDT OUT - * - * The default minimal action is to do nothing and there is no any code to increase. - * For debug environments, the debug information can be displayed in HDT or other - * devices. - * - **/ -#if IDSOPT_IDS_ENABLED == TRUE - #if IDSOPT_TRACING_ENABLED == TRUE - #define IDS_HDT_CONSOLE_INIT(x) - #define IDS_HDT_CONSOLE_EXIT(x) - #define IDS_HDT_CONSOLE_S3_EXIT(x) - #define IDS_HDT_CONSOLE_S3_AP_EXIT(x) - - #if IDSOPT_C_OPTIMIZATION_DISABLED == TRUE - #ifdef __GNUC__ - #define IDS_HDT_CONSOLE(f, s, ...) - #else - #define IDS_HDT_CONSOLE(f, s, ...) - #endif - #else - #pragma warning(disable: 4127) - #ifdef __GNUC__ - #define IDS_HDT_CONSOLE(f, s, ...) - #else - #define IDS_HDT_CONSOLE(f, s, ...) - #endif - #endif - - #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) - #define IDS_HDT_CONSOLE_ASSERT(x) - #define IDS_FUNCLIST_ADDR NULL - #define IDS_FUNCLIST_EXTERN() - #define IDS_TIMEOUT_CTL(t) - #define IDS_HDT_CONSOLE_DEBUG_CODE(Code) - #define CONSOLE(s, ...) - #else - #define IDS_HDT_CONSOLE_INIT(x) - #define IDS_HDT_CONSOLE_EXIT(x) - #define IDS_HDT_CONSOLE_S3_EXIT(x) - #define IDS_HDT_CONSOLE_S3_AP_EXIT(x) - #define IDS_HDT_CONSOLE(f, s, ...) - #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) - #define IDS_HDT_CONSOLE_ASSERT(x) - #define IDS_FUNCLIST_ADDR NULL - #define IDS_FUNCLIST_EXTERN() - #define IDS_TIMEOUT_CTL(t) - #define IDS_HDT_CONSOLE_DEBUG_CODE(Code) - #define CONSOLE(s, ...) - #endif -#else - #define IDS_HDT_CONSOLE_INIT(x) - #define IDS_HDT_CONSOLE_EXIT(x) - #define IDS_HDT_CONSOLE_S3_EXIT(x) - #define IDS_HDT_CONSOLE_S3_AP_EXIT(x) - #define IDS_HDT_CONSOLE(f, s, ...) - #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) - #define IDS_HDT_CONSOLE_ASSERT(x) - #define IDS_FUNCLIST_ADDR NULL - #define IDS_FUNCLIST_EXTERN() - #define IDS_TIMEOUT_CTL(t) - #define IDS_HDT_CONSOLE_DEBUG_CODE(Code) - #define CONSOLE(s, ...) -#endif - -#define IDS_TRACE_SHOW_BLD_OPT_CFG IDSOPT_TRACE_USER_OPTIONS - -#if IDSOPT_PERF_ANALYSIS == TRUE - #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint) - #define IDS_PERF_ANALYSE(StdHeader) - #define IDS_PERF_TIME_MEASURE(StdHeader) -#else - #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint) - #define IDS_PERF_ANALYSE(StdHeader) - #define IDS_PERF_TIME_MEASURE(StdHeader) -#endif - -///For IDS feat use -#define IDS_FAMILY_ALL 0x0ull -#define IDS_BSP_ONLY TRUE -#define IDS_ALL_CORES FALSE - -#define IDS_LATE_RUN_AP_TASK_ID PROC_IDS_CONTROL_IDSLIB_FILECODE - -#define IDS_CALLOUT_INIT 0x00 ///< The function data of IDS callout function of initialization. - -#define IDS_CALLOUT_GNB_PPFUSE_OVERRIDE 0x00 ///< The function data of IDS callout function of GNB pp fuse table. -#define IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG 0x00 ///< The function data of IDS callout function of GNB integrated table. -#define IDS_CALLOUT_GNB_NB_POWERGATE_CONFIG 0x00 ///< The function data of IDS callout function of GNB NB power gate config. -#define IDS_CALLOUT_GNB_PCIE_POWERGATE_CONFIG 0x00 ///< The function data of IDS callout function of GNB PCIE power gateconfig. -#define IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG 0x00 ///< The function data of IDS callout function of GNB pcie platform config. -#define IDS_CALLOUT_GNB_PCIE_PHY_CONFIG 0x00 ///< The function data of IDS callout function of GNB pcie PHY config. -#define IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE 0x00 ///< The function data of IDS callout function of GNB GMM register override - -/// Function entry for HDT script to call -typedef struct _SCRIPT_FUNCTION { - UINT32 FuncAddr; ///< Function address in ROM - CHAR8 FuncName[40]; ///< Function name -} SCRIPT_FUNCTION; - -/// Data Structure for Mem ECC parameter override -typedef struct { - IN BOOLEAN CfgEccRedirection; ///< ECC Redirection - IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate - IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate - IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate - IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate - IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate - IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood -} ECC_OVERRIDE_STRUCT; - - - - -/** - * AGESA Test Points - * - * These are the values displayed to the user to indicate progress through boot. - * These can be used in a debug environment to stop the debugger at a specific - * test point: - * For SimNow!, this command - * bi 81 w vb 49 - * will stop the debugger on one of the TracePoints (49 is the TP value in this example). - * - */ -typedef enum { - StartProcessorTestPoints, ///< 00 Entry used for range testing for @b Processor related TPs - - // Memory test points - TpProcMemBeforeMemDataInit, ///< 01 .. Memory structure initialization (Public interface) - TpProcMemBeforeSpdProcessing, ///< 02 .. SPD Data processing (Public interface) - TpProcMemAmdMemAuto, ///< 03 .. Memory configuration (Public interface) - TpProcMemDramInit, ///< 04 .. DRAM initialization - TpProcMemSPDChecking, ///< 05 .. - TpProcMemModeChecking, ///< 06 .. - TpProcMemSpeedTclConfig, ///< 07 .. Speed and TCL configuration - TpProcMemSpdTiming, ///< 08 .. - TpProcMemDramMapping, ///< 09 .. - TpProcMemPlatformSpecificConfig, ///< 0A .. - TPProcMemPhyCompensation, ///< 0B .. - TpProcMemStartDcts, ///< 0C .. - TpProcMemBeforeDramInit, ///< 0D .. (Public interface) - TpProcMemPhyFenceTraining, ///< 0E .. - TpProcMemSynchronizeDcts, ///< 0F .. - TpProcMemSystemMemoryMapping, ///< 10 .. - TpProcMemMtrrConfiguration, ///< 11 .. - TpProcMemDramTraining, ///< 12 .. - TpProcMemBeforeAnyTraining, ///< 13 .. (Public interface) - TpProcMemWriteLevelizationTraining, ///< 14 .. - TpProcMemWlFirstPass, ///< 15 .. Below 800Mhz first pass start - TpProcMemWlSecondPass, ///< 16 .. Above 800Mhz second pass start - TpProcMemWlDimmConfig, ///< 17 .. Target DIMM configured - TpProcMemWlPrepDimms, ///< 18 .. Prepare DIMMS for WL - TpProcMemWlConfigDimms, ///< 19 .. Configure DIMMS for WL - TpProcMemReceiverEnableTraining, ///< 1A .. - TpProcMemRcvrStartSweep, ///< 1B .. Start sweep loop - TpProcMemRcvrSetDelay, ///< 1C .. Set receiver Delay - TpProcMemRcvrWritePattern, ///< 1D .. Write test pattern - TpProcMemRcvrReadPattern, ///< 1E .. Read test pattern - TpProcMemRcvrTestPattern, ///< 1F .. Compare test pattern - TpProcMemRcvrCalcLatency, ///< 20 .. Calculate MaxRdLatency per channel - TpProcMemReceiveDqsTraining, ///< 21 .. - TpProcMemRcvDqsSetDelay, ///< 22 .. Set Write Data delay - TpProcMemRcvDqsWritePattern, ///< 23 .. Write test pattern - TpProcMemRcvDqsStartSweep, ///< 24 .. Start read sweep - TpProcMemRcvDqsSetRcvDelay, ///< 25 .. Set Receive DQS delay - TpProcMemRcvDqsReadPattern, ///< 26 .. Read Test pattern - TpProcMemRcvDqsTstPattern, ///< 27 .. Compare Test pattern - TpProcMemRcvDqsResults, ///< 28 .. Update results - TpProcMemRcvDqsFindWindow, ///< 29 .. Start Find passing window - TpProcMemTransmitDqsTraining, ///< 2A .. - TpProcMemTxDqStartSweep, ///< 2B .. Start write sweep - TpProcMemTxDqSetDelay, ///< 2C .. Set Transmit DQ delay - TpProcMemTxDqWritePattern, ///< 2D .. Write test pattern - TpProcMemTxDqReadPattern, ///< 2E .. Read Test pattern - TpProcMemTxDqTestPattern, ///< 2F .. Compare Test pattern - TpProcMemTxDqResults, ///< 30 .. Update results - TpProcMemTxDqFindWindow, ///< 31 .. Start Find passing window - TpProcMemMaxRdLatencyTraining, ///< 32 .. - TpProcMemMaxRdLatStartSweep, ///< 33 .. Start sweep - TpProcMemMaxRdLatSetDelay, ///< 34 .. Set delay - TpProcMemMaxRdLatWritePattern, ///< 35 .. Write test pattern - TpProcMemMaxRdLatReadPattern, ///< 36 .. Read Test pattern - TpProcMemMaxRdLatTestPattern, ///< 37 .. Compare Test pattern - TpProcMemOnlineSpareInit, ///< 38 .. Online Spare init - TpProcMemBankInterleaveInit, ///< 39 .. Bank Interleave Init - TpProcMemNodeInterleaveInit, ///< 3A .. Node Interleave Init - TpProcMemChannelInterleaveInit, ///< 3B .. Channel Interleave Init - TpProcMemEccInitialization, ///< 3C .. ECC initialization - TpProcMemPlatformSpecificInit, ///< 3D .. Platform Specific Init - TpProcMemBeforeAgesaReadSpd, ///< 3E .. Before callout for "AgesaReadSpd" - TpProcMemAfterAgesaReadSpd, ///< 3F .. After callout for "AgesaReadSpd" - TpProcMemBeforeAgesaHookBeforeDramInit, ///< 40 .. Before optional callout "AgesaHookBeforeDramInit" - TpProcMemAfterAgesaHookBeforeDramInit, ///< 41 .. After optional callout "AgesaHookBeforeDramInit" - TpProcMemBeforeAgesaHookBeforeDQSTraining, ///< 42 .. Before optional callout "AgesaHookBeforeDQSTraining" - TpProcMemAfterAgesaHookBeforeDQSTraining, ///< 43 .. After optional callout "AgesaHookBeforeDQSTraining" - TpProcMemBeforeAgesaHookBeforeExitSelfRef, ///< 44 .. Before optional callout "AgesaHookBeforeDramInit" - TpProcMemAfterAgesaHookBeforeExitSelfRef, ///< 45 .. After optional callout "AgesaHookBeforeDramInit" - TpProcMemAfterMemDataInit, ///< 46 .. After MemDataInit - TpProcMemInitializeMCT, ///< 47 .. Before InitializeMCT - TpProcMemLvDdr3, ///< 48 .. Before LV DDR3 - TpProcMemInitMCT, ///< 49 .. Before InitMCT - TpProcMemOtherTiming, ///< 4A.. Before OtherTiming - TpProcMemUMAMemTyping, ///< 4B .. Before UMAMemTyping - TpProcMemSetDqsEccTmgs, ///< 4C .. Before SetDqsEccTmgs - TpProcMemMemClr, ///< 4D .. Before MemClr - TpProcMemOnDimmThermal, ///< 4E .. Before On DIMM Thermal - TpProcMemDmi, ///< 4F .. Before DMI - TpProcMemEnd, ///< 50 .. End of memory code - - // CPU test points - TpProcCpuEntryDmi, ///< 51 .. Entry point CreateDmiRecords - TpProcCpuEntryPstate, ///< 52 .. Entry point GenerateSsdt - TpProcCpuEntryPstateLeveling, ///< 53 .. Entry point PStateLeveling - TpProcCpuEntryPstateGather, ///< 54 .. Entry point PStateGatherData - TpProcCpuEntryWhea, ///< 55 .. Entry point CreateAcpiWhea - TpProcCpuEntrySrat, ///< 56 .. Entry point CreateAcpiSrat - TpProcCpuEntrySlit, ///< 57 .. Entry point CreateAcpiSlit - TpProcCpuProcessRegisterTables, ///< 58 .. Register table processing - TpProcCpuSetBrandID, ///< 59 .. Set brand ID - TpProcCpuLocalApicInit, ///< 5A .. Initialize local APIC - TpProcCpuLoadUcode, ///< 5B .. Load microcode patch - TpProcCpuBeforePMFeatureInit, ///< 5C .. BeforePM feature dispatch point - TpProcCpuPowerMgmtInit, ///< 5D .. Power Management table processing - TpProcCpuEarlyFeatureInit, ///< 5E .. Early feature dispatch point - TpProcCpuCoreLeveling, ///< 5F .. Core Leveling - TpProcCpuApMtrrSync, ///< 60 .. AP MTRR sync up - TpProcCpuPostFeatureInit, ///< 61 .. POST feature dispatch point - TpProcCpuFeatureLeveling, ///< 62 .. CPU Feature Leveling - TpProcCpuBeforeAllocateWheaBuffer, ///< 63 .. Before the WHEA init code calls out to allocate a buffer - TpProcCpuAfterAllocateWheaBuffer, ///< 64 .. After the WHEA init code calls out to allocate a buffer - TpProcCpuBeforeAllocateSratBuffer, ///< 65 .. Before the SRAT init code calls out to allocate a buffer - TpProcCpuAfterAllocateSratBuffer, ///< 66 .. After the SRAT init code calls out to allocate a buffer - TpProcCpuBeforeLocateSsdtBuffer, ///< 67 .. Before the P-state init code calls out to locate a buffer - TpProcCpuAfterLocateSsdtBuffer, ///< 68 .. After the P-state init code calls out to locate a buffer - TpProcCpuBeforeAllocateSsdtBuffer, ///< 69 .. Before the P-state init code calls out to allocate a buffer - TpProcCpuAfterAllocateSsdtBuffer, ///< 6A .. After the P-state init code calls out to allocate a buffer - - // HT test points - TpProcHtEntry = 0x71, ///< 71 .. Coherent Discovery begin (Public interface) - TpProcHtTopology, ///< 72 .. Topology match, routing, begin - TpProcHtManualNc, ///< 73 .. Manual Non-coherent Init begin - TpProcHtAutoNc, ///< 74 .. Automatic Non-coherent init begin - TpProcHtOptGather, ///< 75 .. Optimization: Gather begin - TpProcHtOptRegang, ///< 76 .. Optimization: Regang begin - TpProcHtOptLinks, ///< 77 .. Optimization: Link Begin - TpProcHtOptSubLinks, ///< 78 .. Optimization: Sublinks begin - TpProcHtOptFinish, ///< 79 .. Optimization: Set begin - TpProcHtTrafficDist, ///< 7A .. Traffic Distribution begin - TpProcHtTuning, ///< 7B .. Misc Tuning Begin - TpProcHtDone, ///< 7C .. HT Init complete - TpProcHtApMapEntry, ///< 7D .. AP HT: Init Maps begin - TpProcHtApMapDone, ///< 7E .. AP HT: Complete - - StartNbTestPoints = 0x90, ///< 90 Entry used for range testing for @b NorthBridge related TPs - TpNbxxx, ///< 91 . - EndNbTestPoints, ///< 92 End of TP range for NB - - StartSbTestPoints = 0xB0, ///< B0 Entry used for range testing for @b SouthBridge related TPs - TpSbxxx, ///< B1 . - EndSbTestPoints, ///< B2 End of TP range for SB - - // Interface test points - TpIfAmdInitResetEntry = 0xC0, ///< C0 .. Entry to AmdInitReset - TpIfAmdInitResetExit, ///< C1 .. Exiting from AmdInitReset - TpIfAmdInitRecoveryEntry, ///< C2 .. Entry to AmdInitRecovery - TpIfAmdInitRecoveryExit, ///< C3 .. Exiting from AmdInitRecovery - TpIfAmdInitEarlyEntry, ///< C4 .. Entry to AmdInitEarly - TpIfAmdInitEarlyExit, ///< C5 .. Exiting from AmdInitEarly - TpIfAmdInitPostEntry, ///< C6 .. Entry to AmdInitPost - TpIfAmdInitPostExit, ///< C7 .. Exiting from AmdInitPost - TpIfAmdInitEnvEntry, ///< C8 .. Entry to AmdInitEnv - TpIfAmdInitEnvExit, ///< C9 .. Exiting from AmdInitEnv - TpIfAmdInitMidEntry, ///< CA .. Entry to AmdInitMid - TpIfAmdInitMidExit, ///< CB .. Exiting from AmdInitMid - TpIfAmdInitLateEntry, ///< CC .. Entry to AmdInitLate - TpIfAmdInitLateExit, ///< CD .. Exiting from AmdInitLate - TpIfAmdS3SaveEntry, ///< CE .. Entry to AmdS3Save - TpIfAmdS3SaveExit, ///< CF .. Exiting from AmdS3Save - TpIfAmdInitResumeEntry, ///< D0 .. Entry to AmdInitResume - TpIfAmdInitResumeExit, ///< D1 .. Exiting from AmdInitResume - TpIfAmdS3LateRestoreEntry, ///< D2 .. Entry to AmdS3LateRestore - TpIfAmdS3LateRestoreExit, ///< D3 .. Exiting from AmdS3LateRestore - TpIfAmdLateRunApTaskEntry, ///< D4 .. Entry to AmdS3LateRestore - TpIfAmdLateRunApTaskExit, ///< D5 .. Exiting from AmdS3LateRestore - TpIfAmdReadEventLogEntry, ///< D6 .. Entry to AmdReadEventLog - TpIfAmdReadEventLogExit, ///< D7 .. Exiting from AmdReadEventLog - TpIfAmdGetApicIdEntry, ///< D8 .. Entry to AmdGetApicId - TpIfAmdGetApicIdExit, ///< D9 .. Exiting from AmdGetApicId - TpIfAmdGetPciAddressEntry, ///< DA .. Entry to AmdGetPciAddress - TpIfAmdGetPciAddressExit, ///< DB .. Exiting from AmdGetPciAddress - TpIfAmdIdentifyCoreEntry, ///< DC .. Entry to AmdIdentifyCore - TpIfAmdIdentifyCoreExit, ///< DD .. Exiting from AmdIdentifyCore - TpIfBeforeRunApFromIds, ///< DE .. After IDS calls out to run code on an AP - TpIfAfterRunApFromIds, ///< DF .. After IDS calls out to run code on an AP - TpIfBeforeGetIdsData, ///< E0 .. Before IDS calls out to get IDS data - TpIfAfterGetIdsData, ///< E1 .. After IDS calls out to get IDS data - TpIfBeforeAllocateHeapBuffer, ///< E2 .. Before the heap manager calls out to allocate a buffer - TpIfAfterAllocateHeapBuffer, ///< E3 .. After the heap manager calls out to allocate a buffer - TpIfBeforeDeallocateHeapBuffer, ///< E4 .. Before the heap manager calls out to deallocate a buffer - TpIfAfterDeallocateHeapBuffer, ///< E5 .. After the heap manager calls out to deallocate a buffer - TpIfBeforeLocateHeapBuffer, ///< E6 .. Before the heap manager calls out to locate a buffer - TpIfAfterLocateHeapBuffer, ///< E7 .. After the heap manager calls out to locate a buffer - TpIfBeforeRunApFromAllAps, ///< E8 .. Before the BSP calls out to run code on an AP - TpIfAfterRunApFromAllAps, ///< E9 .. After the BSP calls out to run code on an AP - TpIfBeforeRunApFromAllCore0s, ///< EA .. Before the BSP calls out to run code on an AP - TpIfAfterRunApFromAllCore0s, ///< EB .. After the BSP calls out to run code on an AP - TpIfBeforeAllocateS3SaveBuffer, ///< EC .. Before the S3 save code calls out to allocate a buffer - TpIfAfterAllocateS3SaveBuffer, ///< ED .. After the S3 save code calls out to allocate a buffer - TpIfBeforeAllocateMemoryS3SaveBuffer, ///< EE .. Before the memory S3 save code calls out to allocate a buffer - TpIfAfterAllocateMemoryS3SaveBuffer, ///< EF .. After the memory S3 save code calls out to allocate a buffer - TpIfBeforeLocateS3PciBuffer, ///< F0 .. Before the memory code calls out to locate a buffer - TpIfAfterLocateS3PciBuffer, ///< F1 .. After the memory code calls out to locate a buffer - TpIfBeforeLocateS3CPciBuffer, ///< F2 .. Before the memory code calls out to locate a buffer - TpIfAfterLocateS3CPciBuffer, ///< F3 .. After the memory code calls out to locate a buffer - TpIfBeforeLocateS3MsrBuffer, ///< F4 .. Before the memory code calls out to locate a buffer - TpIfAfterLocateS3MsrBuffer, ///< F5 .. After the memory code calls out to locate a buffer - TpIfBeforeLocateS3CMsrBuffer, ///< F6 .. Before the memory code calls out to locate a buffer - TpIfAfterLocateS3CMsrBuffer, ///< F7 .. After the memory code calls out to locate a buffer - TpPerfUnit, ///< F8 .. The Unit of performance measure. - EndAgesaTps = 0xFF, ///< Last defined AGESA TP -} AGESA_TP; - -///Ids Feat description -typedef enum { - IDS_FEAT_UCODE_UPDATE = 0x0000, ///< Feat for Ucode Update - IDS_FEAT_TARGET_PSTATE, ///< Feat for Target Pstate - IDS_FEAT_POSTPSTATE, ///< Feat for Post Pstate - IDS_FEAT_ECC_CTRL, ///< Feat for Ecc Control - IDS_FEAT_ECC_SYMBOL_SIZE, ///< Feat for Ecc symbol size - IDS_FEAT_DCT_ALLMEMCLK, ///< Feat for all memory clock - IDS_FEAT_DCT_GANGMODE, ///< Feat for Dct gang mode - IDS_FEAT_DCT_BURSTLENGTH, ///< Feat for dct burst length - IDS_FEAT_DCT_POWERDOWN, ///< Feat for dct power down - IDS_FEAT_DCT_DLLSHUTDOWN, ///< Feat for dct dll shut down - IDS_FEAT_PROBE_FILTER, ///< Feat for probe filter - IDS_FEAT_HDTOUT, ///< Feat for hdt out - IDS_FEAT_HT_SETTING, ///< Feat for Ht setting - IDS_FEAT_GNB_PLATFORMCFG, ///< Feat for override GNB platform config - IDS_FEAT_CPB_CTRL, ///< Feat for Config the Core peformance boost feature - IDS_FEAT_HTC_CTRL, ///< Feat for Hardware Thermal Control - IDS_FEAT_MEMORY_MAPPING, ///< Feat for Memory Mapping - IDS_FEAT_POWER_POLICY, ///< Feat for Power Policy - IDS_FEAT_END = 0xFF ///< End of Common feat -} IDS_FEAT; - -typedef IDS_STATUS IDS_COMMON_FUNC ( - IN OUT VOID *DataPtr, - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN IDS_NV_ITEM *IdsNvPtr - ); - -typedef IDS_COMMON_FUNC *PIDS_COMMON_FUNC; - -/// Data Structure of IDS Feature block -typedef struct _IDS_FEAT_STRUCT { - IDS_FEAT IdsFeat; ///< Ids Feat ID - BOOLEAN IsBsp; ///< swith for Bsp check - AGESA_IDS_OPTION IdsOption; ///< IDS option - UINT64 CpuFamily; ///< - PIDS_COMMON_FUNC pf_idsoption; /// - CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = { - { (UINT32) (UINT64) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"}, - { (UINT32) (UINT64) MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"}, - { (UINT32) (UINT64) MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"} - }; - #elif (AGESA_ENTRY_INIT_RECOVERY == TRUE) - #include - CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = { - { (UINT32) (UINT64) MemRecUWrite1CL, "Write1Cl(PhyAddrLo,BufferAddr)"}, - { (UINT32) (UINT64) MemRecURead1CL, "Read1Cl(BufferAddr,PhyAddrLo)"}, - { (UINT32) (UINT64) MemRecUFlushPattern, "Flush1Cl(PhyAddrLo)"} - }; - #else - CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = { - { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"}, - { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"}, - { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"} - }; - #endif -#endif - - -///Ids Feat Options -#if (IDSOPT_IDS_ENABLED == TRUE) - #if (IDSOPT_CONTROL_ENABLED == TRUE) - - #ifndef OPTION_IDS_EXTEND_FEATS - #define OPTION_IDS_EXTEND_FEATS - #endif - - #define OPTION_IDS_FEAT_ECCCTRL\ - OPTION_IDS_FEAT_ECCCTRL_F10 \ - OPTION_IDS_FEAT_ECCCTRL_F12 \ - OPTION_IDS_FEAT_ECCCTRL_F15 - - #define OPTION_IDS_FEAT_GNB_PLATFORMCFG\ - OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 \ - OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 - - #define OPTION_IDS_FEAT_CPB_CTRL\ - OPTION_IDS_FEAT_CPB_CTRL_F12 - - #define OPTION_IDS_FEAT_HTC_CTRL\ - OPTION_IDS_FEAT_HTC_CTRL_F15 - - #define OPTION_IDS_FEAT_MEMORY_MAPPING\ - OPTION_IDS_FEAT_MEMORY_MAPPING_F15 - - #define OPTION_IDS_FEAT_HT_ASSIST\ - OPTION_IDS_FEAT_HT_ASSIST_F10HY \ - OPTION_IDS_FEAT_HT_ASSIST_F15 - - #define OPTION_IDS_FEAT_ECCSYMBOLSIZE\ - OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 \ - OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15 - -/*---------------------------------------------------------------------------- - * Family 10 feat blocks - * - *---------------------------------------------------------------------------- - */ - #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 - #define OPTION_IDS_FEAT_ECCCTRL_F10 - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE -//Ecc symbol size - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF10; - #undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 - #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 &IdsFeatEccSymbolSizeBlockF10, - -//ECC scrub control - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF10; - #undef OPTION_IDS_FEAT_ECCCTRL_F10 - #define OPTION_IDS_FEAT_ECCCTRL_F10 &IdsFeatEccCtrlBlockF10, - #endif - #endif - - //Misc Features - #define OPTION_IDS_FEAT_HT_ASSIST_F10HY - #ifdef OPTION_FAMILY10H_HY - #if OPTION_FAMILY10H_HY == TRUE - #undef OPTION_IDS_FEAT_HT_ASSIST_F10HY - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF10Hy; - - #define OPTION_IDS_FEAT_HT_ASSIST_F10HY \ - &IdsFeatHtAssistBlockPlatformCfgF10Hy, - #endif - #endif -/*---------------------------------------------------------------------------- - * Family 12 feat blocks - * - *---------------------------------------------------------------------------- - */ - #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 - #define OPTION_IDS_FEAT_ECCCTRL_F12 - #define OPTION_IDS_FEAT_CPB_CTRL_F12 - #ifdef OPTION_FAMILY12H - #if OPTION_FAMILY12H == TRUE - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF12; - #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 - #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 &IdsFeatGnbPlatformCfgBlockF12, - - //ECC scrub control - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF12; - #undef OPTION_IDS_FEAT_ECCCTRL_F12 - #define OPTION_IDS_FEAT_ECCCTRL_F12 &IdsFeatEccCtrlBlockF12, - - #undef OPTION_IDS_FEAT_CPB_CTRL_F12 - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatCpbCtrlBlockF12; - #define OPTION_IDS_FEAT_CPB_CTRL_F12 &IdsFeatCpbCtrlBlockF12, - - #endif - #endif - -/*---------------------------------------------------------------------------- - * Family 14 feat blocks - * - *---------------------------------------------------------------------------- - */ - #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 - #ifdef OPTION_FAMILY14H - #if OPTION_FAMILY14H == TRUE - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF14; - #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 - #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 &IdsFeatGnbPlatformCfgBlockF14, - #endif - #endif - -/*---------------------------------------------------------------------------- - * Family 15 feat blocks - * - *---------------------------------------------------------------------------- - */ - #define OPTION_IDS_FEAT_HTC_CTRL_F15 - #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15 - #define OPTION_IDS_FEAT_HT_ASSIST_F15 - #define OPTION_IDS_FEAT_ECCCTRL_F15 - #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15 - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15; - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtcControlLateBlockF15; - #undef OPTION_IDS_FEAT_HTC_CTRL_F15 - #define OPTION_IDS_FEAT_HTC_CTRL_F15\ - &IdsFeatHtcControlBlockF15,\ - &IdsFeatHtcControlLateBlockF15, - - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15; - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15; - #undef OPTION_IDS_FEAT_MEMORY_MAPPING_F15 - #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15\ - &IdsFeatMemoryMappingPostBeforeBlockF15,\ - &IdsFeatMemoryMappingChIntlvBlockF15, - - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF15; - #undef OPTION_IDS_FEAT_HT_ASSIST_F15 - #define OPTION_IDS_FEAT_HT_ASSIST_F15\ - &IdsFeatHtAssistBlockPlatformCfgF15, - - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF15; - #undef OPTION_IDS_FEAT_ECCCTRL_F15 - #define OPTION_IDS_FEAT_ECCCTRL_F15 &IdsFeatEccCtrlBlockF15, - - extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF15; - #undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15 - #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15 &IdsFeatEccSymbolSizeBlockF15, - - #endif - #endif - - - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatUcodeBlock = - { - IDS_FEAT_UCODE_UPDATE, - IDS_ALL_CORES, - IDS_UCODE, - IDS_FAMILY_ALL, - IdsSubUCode - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatPowerPolicyBlock = - { - IDS_FEAT_POWER_POLICY, - IDS_ALL_CORES, - IDS_PLATFORMCFG_OVERRIDE, - IDS_FAMILY_ALL, - IdsSubPowerPolicyOverride - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatTargetPstateBlock = - { - IDS_FEAT_TARGET_PSTATE, - IDS_BSP_ONLY, - IDS_INIT_LATE_AFTER, - IDS_FAMILY_ALL, - IdsSubTargetPstate - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatPostPstateBlock = - { - IDS_FEAT_POSTPSTATE, - IDS_ALL_CORES, - IDS_CPU_Early_Override, - IDS_FAMILY_ALL, - IdsSubPostPState - }; - - //Dram controller Features - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctAllMemClkBlock = - { - IDS_FEAT_DCT_ALLMEMCLK, - IDS_BSP_ONLY, - IDS_ALL_MEMORY_CLOCK, - IDS_FAMILY_ALL, - IdsSubAllMemClkEn - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctGangModeBlock = - { - IDS_FEAT_DCT_GANGMODE, - IDS_BSP_ONLY, - IDS_GANGING_MODE, - IDS_FAMILY_ALL, - IdsSubGangingMode - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctBurstLengthBlock = - { - IDS_FEAT_DCT_BURSTLENGTH, - IDS_BSP_ONLY, - IDS_BURST_LENGTH32, - AMD_FAMILY_10, - IdsSubBurstLength32 - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownCtrlBlock = - { - IDS_FEAT_DCT_POWERDOWN, - IDS_BSP_ONLY, - IDS_INIT_POST_BEFORE, - IDS_FAMILY_ALL, - IdsSubPowerDownCtrl - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctDllShutDownBlock = - { - IDS_FEAT_DCT_DLLSHUTDOWN, - IDS_BSP_ONLY, - IDS_DLL_SHUT_DOWN, - IDS_FAMILY_ALL, - IdsSubDllShutDownSR - }; - - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownModeBlock = - { - IDS_FEAT_DCT_POWERDOWN, - IDS_BSP_ONLY, - IDS_POWERDOWN_MODE, - IDS_FAMILY_ALL, - IdsSubPowerDownMode - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHdtOutBlock = - { - IDS_FEAT_HDTOUT, - IDS_BSP_ONLY, - IDS_INIT_EARLY_BEFORE, - IDS_FAMILY_ALL, - IdsSubHdtOut - }; - - CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtSettingBlock = - { - IDS_FEAT_HT_SETTING, - IDS_BSP_ONLY, - IDS_HT_CONTROL, - IDS_FAMILY_ALL, - IdsSubHtLinkControl - }; - - CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] = - { - &IdsFeatUcodeBlock, - &IdsFeatPowerPolicyBlock, - - &IdsFeatTargetPstateBlock, - - &IdsFeatPostPstateBlock, - - OPTION_IDS_FEAT_ECCSYMBOLSIZE - - OPTION_IDS_FEAT_ECCCTRL - - &IdsFeatDctAllMemClkBlock, - - &IdsFeatDctGangModeBlock, - - &IdsFeatDctBurstLengthBlock, - - &IdsFeatDctPowerDownCtrlBlock, - - &IdsFeatDctPowerDownModeBlock, - - &IdsFeatDctPowerDownModeBlock, - - OPTION_IDS_FEAT_HT_ASSIST - - &IdsFeatHdtOutBlock, - - &IdsFeatHtSettingBlock, - - OPTION_IDS_FEAT_GNB_PLATFORMCFG - - OPTION_IDS_FEAT_CPB_CTRL - - OPTION_IDS_FEAT_HTC_CTRL - - OPTION_IDS_FEAT_MEMORY_MAPPING - - OPTION_IDS_EXTEND_FEATS - - NULL - }; - #else - CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] = - { - NULL - }; - #endif//IDSOPT_CONTROL_ENABLED -#else - CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] = - { - NULL - }; -#endif// IDSOPT_IDS_ENABLED - - -#endif diff --git a/src/vendorcode/amd/agesa/Include/OptionIoCstateInstall.h b/src/vendorcode/amd/agesa/Include/OptionIoCstateInstall.h deleted file mode 100644 index f15682fe4d..0000000000 --- a/src/vendorcode/amd/agesa/Include/OptionIoCstateInstall.h +++ /dev/null @@ -1,135 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: IO C-state - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _OPTION_IO_CSTATE_INSTALL_H_ -#define _OPTION_IO_CSTATE_INSTALL_H_ - -#include "cpuIoCstate.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ - -#define OPTION_IO_CSTATE_FEAT -#define F10_IO_CSTATE_SUPPORT -#define F12_IO_CSTATE_SUPPORT -#define F14_IO_CSTATE_SUPPORT -#define F15_IO_CSTATE_SUPPORT - -#if OPTION_IO_CSTATE == TRUE - #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #if OPTION_FAMILY10H_PH == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate; - #undef OPTION_IO_CSTATE_FEAT - #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate, - extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F10IoCstateSupport; - #undef F10_IO_CSTATE_SUPPORT - #define F10_IO_CSTATE_SUPPORT {AMD_FAMILY_10_PH, &F10IoCstateSupport}, - #endif - #endif - #endif - - #ifdef OPTION_FAMILY12H - #if OPTION_FAMILY12H == TRUE - #if OPTION_FAMILY12H_LN == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate; - #undef OPTION_IO_CSTATE_FEAT - #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate, - extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F12IoCstateSupport; - #undef F12_IO_CSTATE_SUPPORT - #define F12_IO_CSTATE_SUPPORT {AMD_FAMILY_12_LN, &F12IoCstateSupport}, - #endif - #endif - #endif - - #ifdef OPTION_FAMILY14H - #if OPTION_FAMILY14H == TRUE - #if OPTION_FAMILY14H_ON == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate; - #undef OPTION_IO_CSTATE_FEAT - #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate, - extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F14IoCstateSupport; - #undef F14_IO_CSTATE_SUPPORT - #define F14_IO_CSTATE_SUPPORT {AMD_FAMILY_14_ON, &F14IoCstateSupport}, - #endif - #endif - #endif - - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #if OPTION_FAMILY15H_OR == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate; - #undef OPTION_IO_CSTATE_FEAT - #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate, - extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15IoCstateSupport; - #undef F15_IO_CSTATE_SUPPORT - #define F15_IO_CSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15IoCstateSupport}, - #endif - #endif - #endif - - #endif -#endif - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA IoCstateFamilyServiceArray[] = -{ - F10_IO_CSTATE_SUPPORT - F12_IO_CSTATE_SUPPORT - F14_IO_CSTATE_SUPPORT - F15_IO_CSTATE_SUPPORT - {0, NULL} -}; - -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA IoCstateFamilyServiceTable = -{ - (sizeof (IoCstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &IoCstateFamilyServiceArray[0] -}; - -#endif // _OPTION_IO_CSTATE_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/Include/OptionLowPwrPstateInstall.h b/src/vendorcode/amd/agesa/Include/OptionLowPwrPstateInstall.h deleted file mode 100644 index 6e03fea21d..0000000000 --- a/src/vendorcode/amd/agesa/Include/OptionLowPwrPstateInstall.h +++ /dev/null @@ -1,89 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Low Power Pstate for PROCHOT_L Throttling. - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _OPTION_LOW_PWR_PSTATE_INSTALL_H_ -#define _OPTION_LOW_PWR_PSTATE_INSTALL_H_ - -#include "cpuLowPwrPstate.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT -#define F15_LOW_PWR_PSTATE_SUPPORT - -#if OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT == TRUE - #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) - // Family 15h - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #if OPTION_FAMILY15H_OR == TRUE - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureLowPwrPstate; - #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT - #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT &CpuFeatureLowPwrPstate, - extern CONST LOW_PWR_PSTATE_FAMILY_SERVICES ROMDATA F15LowPwrPstateSupport; - #undef F15_LOW_PWR_PSTATE_SUPPORT - #define F15_LOW_PWR_PSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15LowPwrPstateSupport}, - #endif - #endif - #endif - #endif -#endif - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA LowPwrPstateFamilyServiceArray[] = -{ - F15_LOW_PWR_PSTATE_SUPPORT - {0, NULL} -}; - -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA LowPwrPstateFamilyServiceTable = -{ - (sizeof (LowPwrPstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &LowPwrPstateFamilyServiceArray[0] -}; - -#endif // _OPTION_LOW_PWR_PSTATE_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/Include/OptionMemory.h b/src/vendorcode/amd/agesa/Include/OptionMemory.h deleted file mode 100644 index 1d4c08f68b..0000000000 --- a/src/vendorcode/amd/agesa/Include/OptionMemory.h +++ /dev/null @@ -1,342 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Memory option API. - * - * Contains structures and values used to control the Memory option code. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: OPTION - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _OPTION_MEMORY_H_ -#define _OPTION_MEMORY_H_ - -/* Memory Includes */ -#include "mm.h" -#include "mn.h" -#include "mt.h" -#include "ma.h" -#include "mp.h" -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -#define MAX_FF_TYPES 6 ///< Maximum number of DDR Form factors (UDIMMs, RDIMMMs, SODIMMS) supported - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ - -/* -* STANDARD MEMORY FEATURE FUNCTION POINTER -*/ - -typedef BOOLEAN OPTION_MEM_FEATURE_NB ( - IN OUT MEM_NB_BLOCK *NBPtr - ); - -typedef BOOLEAN MEM_TECH_FEAT ( - IN OUT MEM_TECH_BLOCK *TechPtr - ); - -typedef UINT8 MEM_TABLE_FEAT ( - IN OUT MEM_TABLE_ALIAS **MTPtr - ); - -#define MEM_FEAT_BLOCK_NB_STRUCT_VERSION 0x01 - -/** - * MEMORY FEATURE BLOCK - This structure serves as a vector table for standard - * memory feature implementation functions. It contains vectors for all of the - * features that are supported by the various Northbridge devices supported by - * AGESA. - */ -typedef struct _MEM_FEAT_BLOCK_NB { - UINT16 OptMemFeatVersion; ///< Version of memory feature block. - OPTION_MEM_FEATURE_NB *OnlineSpare; ///< Online spare support. - OPTION_MEM_FEATURE_NB *InterleaveBanks; ///< Bank (Chip select) interleaving support. - OPTION_MEM_FEATURE_NB *UndoInterleaveBanks; ///< Undo Bank (Chip Select) interleaving. - OPTION_MEM_FEATURE_NB *CheckInterleaveNodes; ///< Check for Node interleaving support. - OPTION_MEM_FEATURE_NB *InterleaveNodes; ///< Node interleaving support. - OPTION_MEM_FEATURE_NB *InterleaveChannels; ///< Channel interleaving support. - OPTION_MEM_FEATURE_NB *InterleaveRegion; ///< Interleave Region support. - OPTION_MEM_FEATURE_NB *CheckEcc; ///< Check for ECC support. - OPTION_MEM_FEATURE_NB *InitEcc; ///< ECC support. - OPTION_MEM_FEATURE_NB *Training; ///< Choose the type of training (Parallel, standard or hardcoded). - OPTION_MEM_FEATURE_NB *LvDdr3; ///< Low voltage DDR3 dimm support - OPTION_MEM_FEATURE_NB *OnDimmThermal; ///< On-Dimm thermal management - MEM_TECH_FEAT *DramInit; ///< Choose the type of Dram init (hardware based or software based). - OPTION_MEM_FEATURE_NB *ExcludeDIMM; ///< Exclude a dimm. - OPTION_MEM_FEATURE_NB *InitEarlySampleSupport; ///< Initialize early sample support. - OPTION_MEM_FEATURE_NB *InitCPG; ///< Continuous pattern generation. - OPTION_MEM_FEATURE_NB *InitHwRxEn; ///< Hardware Receiver Enable Training Initilization. -} MEM_FEAT_BLOCK_NB; - -typedef AGESA_STATUS MEM_MAIN_FLOW_CONTROL ( - IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr - ); - -typedef BOOLEAN OPTION_MEM_FEATURE_MAIN ( - IN MEM_MAIN_DATA_BLOCK *MMPtr - ); - -typedef BOOLEAN MEM_NB_CONSTRUCTOR ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN MEM_FEAT_BLOCK_NB *FeatPtr, - IN MEM_SHARED_DATA *mmSharedPtr, ///< Pointer to Memory scratchpad - IN UINT8 NodeID - ); - -typedef BOOLEAN MEM_TECH_CONSTRUCTOR ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT MEM_NB_BLOCK *NBPtr - ); - -typedef VOID MEM_INITIALIZER ( - IN OUT MEM_DATA_STRUCT *MemPtr - ); - -typedef AGESA_STATUS MEM_PLATFORM_CFG ( - IN struct _MEM_DATA_STRUCT *MemData, - IN UINT8 SocketID, - IN CH_DEF_STRUCT *CurrentChannel - ); - -typedef BOOLEAN MEM_IDENDIMM_CONSTRUCTOR ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ); - -typedef VOID MEM_TECH_TRAINING_FEAT ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN UINT8 Pass - ); - -typedef BOOLEAN MEM_RESUME_CONSTRUCTOR ( - IN OUT VOID *S3NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ); - -typedef AGESA_STATUS MEM_PLAT_SPEC_CFG ( - IN struct _MEM_DATA_STRUCT *MemData, - IN OUT CH_DEF_STRUCT *CurrentChannel, - IN OUT MEM_PS_BLOCK *PsPtr - ); - -typedef AGESA_STATUS MEM_FLOW_CFG ( - IN OUT MEM_MAIN_DATA_BLOCK *MemData - ); - -#define MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION 0x01 - -/** - * MAIN FEATURE BLOCK - This structure serves as vector table for memory features - * that shared between all northbridge devices. - */ -typedef struct _MEM_FEAT_BLOCK_MAIN { - UINT16 OptMemFeatVersion; ///< Version of main feature block. - OPTION_MEM_FEATURE_MAIN *Training; ///< Training features. - OPTION_MEM_FEATURE_MAIN *ExcludeDIMM; ///< Exclude a dimm. - OPTION_MEM_FEATURE_MAIN *OnlineSpare; ///< On-line spare. - OPTION_MEM_FEATURE_MAIN *InterleaveNodes; ///< Node interleave. - OPTION_MEM_FEATURE_MAIN *InitEcc; ///< Initialize ECC on all nodes if they all support it. - OPTION_MEM_FEATURE_MAIN *MemClr; ///< Memory Clear. - OPTION_MEM_FEATURE_MAIN *MemDmi; ///< Memory DMI Support. - OPTION_MEM_FEATURE_MAIN *LvDDR3; ///< Low voltage DDR3 support. - OPTION_MEM_FEATURE_MAIN *UmaAllocation; ///< Uma Allocation. - OPTION_MEM_FEATURE_MAIN *MemSave; ///< Memory Context Save - OPTION_MEM_FEATURE_MAIN *MemRestore; ///< Memory Context Restore -} MEM_FEAT_BLOCK_MAIN; - -#define MEM_NB_SUPPORT_STRUCT_VERSION 0x01 -#define MEM_TECH_FEAT_BLOCK_STRUCT_VERSION 0x01 -#define MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION 0x01 -#define MEM_TECH_LRDIMM_STRUCT_VERSION 0x01 -/** - * MEMORY TECHNOLOGY FEATURE BLOCK - This structure serves as a vector table for standard - * memory feature implementation functions. It contains vectors for all of the - * features that are supported by the various Technology features supported by - * AGESA. - */ -typedef struct _MEM_TECH_FEAT_BLOCK { - UINT16 OptMemTechFeatVersion; ///< Version of memory Tech feature block. - MEM_TECH_FEAT *EnterHardwareTraining; /// MAX_PLATFORM_TYPES - #error Size of memPlatformTypeInstalled array larger than MAX_PLATFORM_TYPES - #endif - - /*--------------------------------------------------------------------------------------------------- - * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION - * - * - *--------------------------------------------------------------------------------------------------- - */ - #define MEM_PSC_FLOW_BLOCK_END NULL - #define PSC_TBL_END NULL - #define MEM_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue - - #if OPTION_MEMCTLR_OR - #if OPTION_UDIMMS - #if OPTION_AM3_SOCKET_SUPPORT - extern PSC_TBL_ENTRY MaxFreqTblEntUAM3; - #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 &MaxFreqTblEntUAM3, - extern PSC_TBL_ENTRY DramTermTblEntUAM3; - #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 &DramTermTblEntUAM3, - extern PSC_TBL_ENTRY OdtPat1DTblEntUAM3; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 &OdtPat1DTblEntUAM3, - extern PSC_TBL_ENTRY OdtPat2DTblEntUAM3; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 &OdtPat2DTblEntUAM3, - extern PSC_TBL_ENTRY OdtPat3DTblEntUAM3; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 &OdtPat3DTblEntUAM3, - extern PSC_TBL_ENTRY SAOTblEntUAM3; - #define PSC_TBL_OR_UDIMM3_SAO_AM3 &SAOTblEntUAM3, - extern PSC_TBL_ENTRY ClkDisMapEntUAM3; - #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 &ClkDisMapEntUAM3, - #endif - #if OPTION_C32_SOCKET_SUPPORT - extern PSC_TBL_ENTRY MaxFreqTblEntUC32; - #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 &MaxFreqTblEntUC32, - extern PSC_TBL_ENTRY DramTermTblEntUC32; - #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 &DramTermTblEntUC32, - extern PSC_TBL_ENTRY OdtPat1DTblEntUC32; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntUC32, - extern PSC_TBL_ENTRY OdtPat2DTblEntUC32; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 &OdtPat2DTblEntUC32, - extern PSC_TBL_ENTRY OdtPat3DTblEntUC32; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntUC32, - extern PSC_TBL_ENTRY SAOTblEntUC32; - #define PSC_TBL_OR_UDIMM3_SAO_C32 &SAOTblEntUC32, - extern PSC_TBL_ENTRY ClkDisMapEntUC32; - #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32 &ClkDisMapEntUC32, - extern PSC_TBL_ENTRY ClkDisMap3DEntUC32; - #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 &ClkDisMap3DEntUC32, - #endif - #if OPTION_G34_SOCKET_SUPPORT - extern PSC_TBL_ENTRY MaxFreqTblEntUG34; - #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 &MaxFreqTblEntUG34, - extern PSC_TBL_ENTRY DramTermTblEntUG34; - #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 &DramTermTblEntUG34, - extern PSC_TBL_ENTRY OdtPat1DTblEntUG34; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntUG34, - extern PSC_TBL_ENTRY OdtPat2DTblEntUG34; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 &OdtPat2DTblEntUG34, - extern PSC_TBL_ENTRY OdtPat3DTblEntUG34; - #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntUG34, - extern PSC_TBL_ENTRY SAOTblEntUG34; - #define PSC_TBL_OR_UDIMM3_SAO_G34 &SAOTblEntUG34, - extern PSC_TBL_ENTRY ClkDisMapEntUG34; - #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34 &ClkDisMapEntUG34, - #endif - #endif - #if OPTION_RDIMMS - #if OPTION_C32_SOCKET_SUPPORT - extern PSC_TBL_ENTRY MaxFreqTblEntRC32; - #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 &MaxFreqTblEntRC32, - extern PSC_TBL_ENTRY DramTermTblEntRC32; - #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 &DramTermTblEntRC32, - extern PSC_TBL_ENTRY OdtPat1DTblEntRC32; - #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntRC32, - extern PSC_TBL_ENTRY OdtPat2DTblEntRC32; - #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 &OdtPat2DTblEntRC32, - extern PSC_TBL_ENTRY OdtPat3DTblEntRC32; - #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntRC32, - extern PSC_TBL_ENTRY SAOTblEntRC32; - #define PSC_TBL_OR_RDIMM3_SAO_C32 &SAOTblEntRC32, - extern PSC_TBL_ENTRY RC2IBTTblEntRC32; - #define PSC_TBL_OR_RDIMM3_RC2IBT_C32 &RC2IBTTblEntRC32, - extern PSC_TBL_ENTRY RC10OpSpdTblEntRC32; - #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 &RC10OpSpdTblEntRC32, - extern PSC_TBL_ENTRY ClkDisMapEntRC32; - #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32 &ClkDisMapEntRC32, - #endif - #if OPTION_G34_SOCKET_SUPPORT - extern PSC_TBL_ENTRY MaxFreqTblEntRG34; - #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 &MaxFreqTblEntRG34, - extern PSC_TBL_ENTRY DramTermTblEntRG34; - #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 &DramTermTblEntRG34, - extern PSC_TBL_ENTRY OdtPat1DTblEntRG34; - #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntRG34, - extern PSC_TBL_ENTRY OdtPat2DTblEntRG34; - #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 &OdtPat2DTblEntRG34, - extern PSC_TBL_ENTRY OdtPat3DTblEntRG34; - #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntRG34, - extern PSC_TBL_ENTRY SAOTblEntRG34; - #define PSC_TBL_OR_RDIMM3_SAO_G34 &SAOTblEntRG34, - extern PSC_TBL_ENTRY RC2IBTTblEntRG34; - #define PSC_TBL_OR_RDIMM3_RC2IBT_G34 &RC2IBTTblEntRG34, - extern PSC_TBL_ENTRY RC10OpSpdTblEntRG34; - #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 &RC10OpSpdTblEntRG34, - extern PSC_TBL_ENTRY ClkDisMapEntRG34; - #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34 &ClkDisMapEntRG34, - #endif - #endif - //#if OPTION_SODIMMS - //#endif - //#if OPTION_LRDIMMS - // #if OPTION_C32_SOCKET_SUPPORT - // extern PSC_TBL_ENTRY MaxFreqTblEntLRC32; - // #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 &MaxFreqTblEntLRC32, - // extern PSC_TBL_ENTRY DramTermTblEntLRC32; - // #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 &DramTermTblEntLRC32, - // extern PSC_TBL_ENTRY OdtPat1DTblEntRC32; - // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntLRC32, - // extern PSC_TBL_ENTRY OdtPat2DTblEntRC32; - // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32 &OdtPat2DTblEntLRC32, - // extern PSC_TBL_ENTRY OdtPat3DTblEntRC32; - // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntLRC32, - // extern PSC_TBL_ENTRY SAOTblEntRC32; - // #define PSC_TBL_OR_LRDIMM3_SAO_C32 &SAOTblEntLRC32, - // extern PSC_TBL_ENTRY IBTTblEntLRC32; - // #define PSC_TBL_OR_LRDIMM3_IBT_C32 &IBTTblEntLRC32, - // extern PSC_TBL_ENTRY ClkDisMapEntLRC32; - // #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 &ClkDisMapEntLRC32, - // #endif - // #if OPTION_G34_SOCKET_SUPPORT - // extern PSC_TBL_ENTRY MaxFreqTblEntLRG34; - // #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 &MaxFreqTblEntLRG34, - // extern PSC_TBL_ENTRY DramTermTblEntLRG34; - // #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 &DramTermTblEntLRG34, - // extern PSC_TBL_ENTRY OdtPat1DTblEntRG34; - // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntLRG34, - // extern PSC_TBL_ENTRY OdtPat2DTblEntRG34; - // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34 &OdtPat2DTblEntLRG34, - // extern PSC_TBL_ENTRY OdtPat3DTblEntRG34; - // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntLRG34, - // extern PSC_TBL_ENTRY SAOTblEntRG34; - // #define PSC_TBL_OR_LRDIMM3_SAO_G34 &SAOTblEntLRG34, - // extern PSC_TBL_ENTRY IBTTblEntLRG34; - // #define PSC_TBL_OR_LRDIMM3_IBT_G34 &IBTTblEntLRG34, - // extern PSC_TBL_ENTRY ClkDisMapEntLRG34; - // #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 &ClkDisMapEntLRG34, - // #endif - //#endif - extern PSC_TBL_ENTRY MR0WrTblEntry; - #define PSC_TBL_OR_MR0_WR &MR0WrTblEntry, - extern PSC_TBL_ENTRY MR0CLTblEntry; - #define PSC_TBL_OR_MR0_CL &MR0CLTblEntry, - extern PSC_TBL_ENTRY OrDdr3CKETriEnt; - #define PSC_TBL_OR_CKE_TRI &OrDdr3CKETriEnt, - extern PSC_TBL_ENTRY OrDdr3ODTTri3DEnt; - #define PSC_TBL_OR_ODT_TRI_3D &OrDdr3ODTTri3DEnt, - extern PSC_TBL_ENTRY OrDdr3ODTTriEnt; - #define PSC_TBL_OR_ODT_TRI &OrDdr3ODTTriEnt, - extern PSC_TBL_ENTRY OrUDdr3CSTriEnt; - #define PSC_TBL_OR_UDIMM3_CS_TRI &OrUDdr3CSTriEnt, - extern PSC_TBL_ENTRY OrDdr3CSTriEnt; - #define PSC_TBL_OR_CS_TRI &OrDdr3CSTriEnt, - extern PSC_TBL_ENTRY OrLRDdr3ODTTri3DEnt; - #define PSC_TBL_OR_LRDIMM3_ODT_TRI_3D &OrLRDdr3ODTTri3DEnt, - extern PSC_TBL_ENTRY OrLRDdr3ODTTriEnt; - #define PSC_TBL_OR_LRDIMM3_ODT_TRI &OrLRDdr3ODTTriEnt, - - #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 - #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 - #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 - #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 - #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 - #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 - #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 - #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_SAO_AM3 - #define PSC_TBL_OR_UDIMM3_SAO_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_SAO_C32 - #define PSC_TBL_OR_UDIMM3_SAO_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_SAO_G34 - #define PSC_TBL_OR_UDIMM3_SAO_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3 - #define PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 - #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 - #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3 - #define PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 - #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 - #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 - #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_SAO_AM3 - #define PSC_TBL_OR_RDIMM3_SAO_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_SAO_C32 - #define PSC_TBL_OR_RDIMM3_SAO_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_SAO_G34 - #define PSC_TBL_OR_RDIMM3_SAO_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_AM3 - #define PSC_TBL_OR_RDIMM3_RC2IBT_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_C32 - #define PSC_TBL_OR_RDIMM3_RC2IBT_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_G34 - #define PSC_TBL_OR_RDIMM3_RC2IBT_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3 - #define PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3 - #endif - #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 - #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 - #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 - #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 - #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 - #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 - #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 - #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 - #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32 - #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34 - #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 - #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 - #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_SAO_C32 - #define PSC_TBL_OR_LRDIMM3_SAO_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_SAO_G34 - #define PSC_TBL_OR_LRDIMM3_SAO_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_IBT_C32 - #define PSC_TBL_OR_LRDIMM3_IBT_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_IBT_G34 - #define PSC_TBL_OR_LRDIMM3_IBT_G34 - #endif - #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 - #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 - #endif - #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_C32 - #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 - #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 - #endif - #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_G34 - #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34 - #endif - #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_C32 - #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32 - #endif - #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_G34 - #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 - #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 - #endif - #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 - #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 - #endif - - PSC_TBL_ENTRY* memPSCTblMaxFreqArrayOR[] = { - PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 - PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 - PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 - PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3 - PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 - PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 - PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 - PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblDramTermArrayOR[] = { - PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 - PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 - PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 - PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3 - PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 - PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 - PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 - PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblODTPatArrayOR[] = { - PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 - PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 - PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 - PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 - PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 - PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 - PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 - PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 - PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 - PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 - PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 - PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 - PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 - PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32 - PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 - PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 - PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 - PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 - PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 - PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 - PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 - PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 - PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34 - PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblSAOArrayOR[] = { - PSC_TBL_OR_UDIMM3_SAO_AM3 - PSC_TBL_OR_UDIMM3_SAO_C32 - PSC_TBL_OR_UDIMM3_SAO_G34 - PSC_TBL_OR_RDIMM3_SAO_AM3 - PSC_TBL_OR_RDIMM3_SAO_C32 - PSC_TBL_OR_RDIMM3_SAO_G34 - PSC_TBL_OR_LRDIMM3_SAO_C32 - PSC_TBL_OR_LRDIMM3_SAO_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblMR0WRArrayOR[] = { - PSC_TBL_OR_MR0_WR - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblMR0CLArrayOR[] = { - PSC_TBL_OR_MR0_CL - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblRC2IBTArrayOR[] = { - PSC_TBL_OR_RDIMM3_RC2IBT_AM3 - PSC_TBL_OR_RDIMM3_RC2IBT_C32 - PSC_TBL_OR_RDIMM3_RC2IBT_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblRC10OPSPDArrayOR[] = { - PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3 - PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 - PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblLRIBTArrayOR[] = { - PSC_TBL_OR_LRDIMM3_IBT_C32 - PSC_TBL_OR_LRDIMM3_IBT_G34 - PSC_TBL_END - }; - - PSC_TBL_ENTRY* memPSCTblGenArrayOR[] = { - PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 - PSC_TBL_OR_UDIMM3_CLK_DIS_C32 - PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 - PSC_TBL_OR_UDIMM3_CLK_DIS_G34 - PSC_TBL_OR_RDIMM3_CLK_DIS_C32 - PSC_TBL_OR_RDIMM3_CLK_DIS_G34 - PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 - PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 - PSC_TBL_OR_CKE_TRI - PSC_TBL_OR_ODT_TRI_3D - PSC_TBL_OR_ODT_TRI - PSC_TBL_OR_LRDIMM3_ODT_TRI_3D - PSC_TBL_OR_LRDIMM3_ODT_TRI - PSC_TBL_OR_UDIMM3_CS_TRI - PSC_TBL_OR_CS_TRI - PSC_TBL_END - }; - - MEM_PSC_TABLE_BLOCK memPSCTblBlockOr = { - (PSC_TBL_ENTRY **)&memPSCTblMaxFreqArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblDramTermArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblODTPatArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblSAOArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblMR0WRArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblMR0CLArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblRC2IBTArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblRC10OPSPDArrayOR, - (PSC_TBL_ENTRY **)&memPSCTblLRIBTArrayOR, - NULL, - NULL, - (PSC_TBL_ENTRY **)&memPSCTblGenArrayOR - }; - - extern MEM_PSC_FLOW MemPGetMaxFreqSupported; - #define PSC_FLOW_OR_MAX_FREQ MemPGetMaxFreqSupported - extern MEM_PSC_FLOW MemPGetRttNomWr; - #define PSC_FLOW_OR_DRAM_TERM MemPGetRttNomWr - extern MEM_PSC_FLOW MemPGetODTPattern; - #define PSC_FLOW_OR_ODT_PATTERN MemPGetODTPattern - extern MEM_PSC_FLOW MemPGetSAO; - #define PSC_FLOW_OR_SAO MemPGetSAO - extern MEM_PSC_FLOW MemPGetMR0WrCL; - #define PSC_FLOW_OR_MR0_WRCL MemPGetMR0WrCL - #if OPTION_RDIMMS - extern MEM_PSC_FLOW MemPGetRC2IBT; - #define PSC_FLOW_OR_RC2_IBT MemPGetRC2IBT - extern MEM_PSC_FLOW MemPGetRC10OpSpd; - #define PSC_FLOW_OR_RC10_OPSPD MemPGetRC10OpSpd - #endif - //#if OPTION_LRDIMMS - //extern MEM_PSC_FLOW MemPGetLRIBT; - //#define PSC_FLOW_OR_LR_IBT MemPGetLRIBT - //extern MEM_PSC_FLOW MemPGetLRNPR; - //#define PSC_FLOW_OR_LR_NPR MemPGetLRNPR - //extern MEM_PSC_FLOW MemPGetLRNLR; - //#define PSC_FLOW_OR_LR_NLR MemPGetLRNLR - //#endif - #ifndef PSC_FLOW_OR_MAX_FREQ - #define PSC_FLOW_OR_MAX_FREQ MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_DRAM_TERM - #define PSC_FLOW_OR_DRAM_TERM MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_ODT_PATTERN - #define PSC_FLOW_OR_ODT_PATTERN MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_SAO - #define PSC_FLOW_OR_SAO MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_MR0_WRCL - #define PSC_FLOW_OR_MR0_WRCL MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_RC2_IBT - #define PSC_FLOW_OR_RC2_IBT MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_RC10_OPSPD - #define PSC_FLOW_OR_RC10_OPSPD MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_LR_IBT - #define PSC_FLOW_OR_LR_IBT MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_LR_NPR - #define PSC_FLOW_OR_LR_NPR MEM_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_FLOW_OR_LR_NLR - #define PSC_FLOW_OR_LR_NLR MEM_PSC_FLOW_DEFTRUE - #endif - MEM_PSC_FLOW_BLOCK memPlatSpecFlowOR = { - &memPSCTblBlockOr, - PSC_FLOW_OR_MAX_FREQ, - PSC_FLOW_OR_DRAM_TERM, - PSC_FLOW_OR_ODT_PATTERN, - PSC_FLOW_OR_SAO, - PSC_FLOW_OR_MR0_WRCL, - PSC_FLOW_OR_RC2_IBT, - PSC_FLOW_OR_RC10_OPSPD, - PSC_FLOW_OR_LR_IBT, - PSC_FLOW_OR_LR_NPR, - PSC_FLOW_OR_LR_NLR - }; - #define MEM_PSC_FLOW_BLOCK_OR &memPlatSpecFlowOR, - #else - #define MEM_PSC_FLOW_BLOCK_OR - #endif - - - MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = { - MEM_PSC_FLOW_BLOCK_OR - MEM_PSC_FLOW_BLOCK_END - }; - - /*--------------------------------------------------------------------------------------------------- - * - * LRDIMM CONTROL - * - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_LRDIMMS == TRUE) - #if (OPTION_MEMCTLR_OR == TRUE) - extern MEM_TECH_FEAT MemTLrdimmConstructor3; - #define MEM_TECH_FEATURE_LRDIMM_INIT &MemTLrdimmConstructor3 - #else //#if (OPTION_MEMCTLR_OR == FALSE) - #define MEM_TECH_FEATURE_LRDIMM_INIT MemTFeatDef - #endif - #else //#if (OPTION_LRDIMMS == FALSE) - #define MEM_TECH_FEATURE_LRDIMM_INIT MemTFeatDef - #endif - MEM_TECH_LRDIMM memLrdimmSupported = { - MEM_TECH_LRDIMM_STRUCT_VERSION, - MEM_TECH_FEATURE_LRDIMM_INIT - }; -#else - /*--------------------------------------------------------------------------------------------------- - * MAIN FLOW CONTROL - * - * - *--------------------------------------------------------------------------------------------------- - */ - MEM_FLOW_CFG* memFlowControlInstalled[] = { - NULL - }; - /*--------------------------------------------------------------------------------------------------- - * NB TRAINING FLOW CONTROL - * - * - *--------------------------------------------------------------------------------------------------- - */ - OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = { // Training flow control - NULL - }; - /*--------------------------------------------------------------------------------------------------- - * DEFAULT TECHNOLOGY BLOCK - * - * - *--------------------------------------------------------------------------------------------------- - */ - MEM_TECH_CONSTRUCTOR* memTechInstalled[] = { // Types of technology installed - NULL - }; - - /*--------------------------------------------------------------------------------------------------- - * DEFAULT TECHNOLOGY MAP - * - * - *--------------------------------------------------------------------------------------------------- - */ - UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0}; - - /*--------------------------------------------------------------------------------------------------- - * DEFAULT MAIN FEATURE BLOCK - *--------------------------------------------------------------------------------------------------- - */ - MEM_FEAT_BLOCK_MAIN MemFeatMain = { - NULL - }; - - /*--------------------------------------------------------------------------------------------------- - * DEFAULT NORTHBRIDGE SUPPORT LIST - * - * - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_DR == TRUE) - #undef MEM_NB_SUPPORT_DR - #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR }, - #endif - #if (OPTION_MEMCTLR_RB == TRUE) - #undef MEM_NB_SUPPORT_RB - #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB }, - #endif - #if (OPTION_MEMCTLR_DA == TRUE) - #undef MEM_NB_SUPPORT_DA - #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA }, - #endif - #if (OPTION_MEMCTLR_PH == TRUE) - #undef MEM_NB_SUPPORT_PH - #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH }, - #endif - #if (OPTION_MEMCTLR_HY == TRUE) - #undef MEM_NB_SUPPORT_HY - #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY }, - #endif - #if (OPTION_MEMCTLR_C32 == TRUE) - #undef MEM_NB_SUPPORT_C32 - #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 }, - #endif - #if (OPTION_MEMCTLR_LN == TRUE) - #undef MEM_NB_SUPPORT_LN - #define MEM_NB_SUPPORT_LN { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN, MEM_IDENDIMM_LN }, - #endif - #if (OPTION_MEMCTLR_ON == TRUE) - #undef MEM_NB_SUPPORT_ON - #define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON }, - #endif - #if (OPTION_MEMCTLR_OR == TRUE) - #undef MEM_NB_SUPPORT_OR - #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR }, - #endif - /*--------------------------------------------------------------------------------------------------- - * DEFAULT Technology Training - * - * - *--------------------------------------------------------------------------------------------------- - */ - #if OPTION_DDR2 - MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2 = { - NULL - }; - MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = { - NULL - }; - #endif - #if OPTION_DDR3 - MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR3 = { - NULL - }; - MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { - NULL - }; - #endif - /*--------------------------------------------------------------------------------------------------- - * DEFAULT Platform Specific list - * - * - *--------------------------------------------------------------------------------------------------- - */ - #if (OPTION_MEMCTLR_DR == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDr[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_RB == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_DA == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_Ni == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_PH == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_LN == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledLN[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_HY == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_OR == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledOr[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_C32 == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = { - NULL - }; - #endif - #if (OPTION_MEMCTLR_ON == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[MAX_FF_TYPES] = { - NULL - }; - #endif - /*---------------------------------------------------------------------- - * DEFAULT PSCFG DEFINITIONS - * - *---------------------------------------------------------------------- - */ - MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = { - NULL - }; - - /*---------------------------------------------------------------------- - * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION - * - *---------------------------------------------------------------------- - */ - MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = { - NULL - }; - - MEM_TECH_LRDIMM memLrdimmSupported = { - MEM_TECH_LRDIMM_STRUCT_VERSION, - NULL - }; -#endif - -/*--------------------------------------------------------------------------------------------------- - * NORTHBRIDGE SUPPORT LIST - * - * - *--------------------------------------------------------------------------------------------------- - */ -MEM_NB_SUPPORT memNBInstalled[] = { - MEM_NB_SUPPORT_RB - MEM_NB_SUPPORT_DA - MEM_NB_SUPPORT_Ni - MEM_NB_SUPPORT_PH - MEM_NB_SUPPORT_HY - MEM_NB_SUPPORT_LN - MEM_NB_SUPPORT_OR - MEM_NB_SUPPORT_C32 - MEM_NB_SUPPORT_ON - MEM_NB_SUPPORT_END -}; - -#endif // _OPTION_MEMORY_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/Include/OptionMemoryRecovery.h b/src/vendorcode/amd/agesa/Include/OptionMemoryRecovery.h deleted file mode 100644 index 443a3caecc..0000000000 --- a/src/vendorcode/amd/agesa/Include/OptionMemoryRecovery.h +++ /dev/null @@ -1,65 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Memory option API. - * - * Contains structures and values used to control the Memory option code. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: OPTION - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _OPTION_MEMORY_RECOVERY_H_ -#define _OPTION_MEMORY_RECOVERY_H_ - -#include "mm.h" -#include "mn.h" -#include "mt.h" - -typedef BOOLEAN MEM_REC_NB_CONSTRUCTOR ( - IN OUT MEM_NB_BLOCK *NBPtr, - IN OUT MEM_DATA_STRUCT *MemPtr, - IN UINT8 NodeID - ); - -typedef VOID MEM_REC_TECH_CONSTRUCTOR ( - IN OUT MEM_TECH_BLOCK *TechPtr, - IN OUT MEM_NB_BLOCK *NBPtr - ); - -#endif // _OPTION_MEMORY_H_ diff --git a/src/vendorcode/amd/agesa/Include/OptionMemoryRecoveryInstall.h b/src/vendorcode/amd/agesa/Include/OptionMemoryRecoveryInstall.h deleted file mode 100644 index 20199473c4..0000000000 --- a/src/vendorcode/amd/agesa/Include/OptionMemoryRecoveryInstall.h +++ /dev/null @@ -1,602 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Memory - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _OPTION_MEMORY_RECOVERY_INSTALL_H_ -#define _OPTION_MEMORY_RECOVERY_INSTALL_H_ - -#if (AGESA_ENTRY_INIT_RECOVERY == TRUE) - - #define MEM_REC_NB_SUPPORT_OR - - #if (OPTION_MEMCTLR_DR == TRUE) - extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockDR; - #define MEM_REC_NB_SUPPORT_DR MemRecConstructNBBlockDR, - #else - #define MEM_REC_NB_SUPPORT_DR - #endif - #if (OPTION_MEMCTLR_RB == TRUE) - extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockRb; - #define MEM_REC_NB_SUPPORT_RB MemRecConstructNBBlockRb, - #else - #define MEM_REC_NB_SUPPORT_RB - #endif - #if (OPTION_MEMCTLR_DA == TRUE) - extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockDA; - #define MEM_REC_NB_SUPPORT_DA MemRecConstructNBBlockDA, - #else - #define MEM_REC_NB_SUPPORT_DA - #endif - #if (OPTION_MEMCTLR_NI == TRUE) - extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockNi; - #define MEM_REC_NB_SUPPORT_NI MemRecConstructNBBlockNi, - #else - #define MEM_REC_NB_SUPPORT_NI - #endif - #if (OPTION_MEMCTLR_PH == TRUE) - extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockPh; - #define MEM_REC_NB_SUPPORT_PH MemRecConstructNBBlockPh, - #else - #define MEM_REC_NB_SUPPORT_PH - #endif - #if (OPTION_MEMCTLR_HY == TRUE) - extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockHY; - #define MEM_REC_NB_SUPPORT_HY MemRecConstructNBBlockHY, - #else - #define MEM_REC_NB_SUPPORT_HY - #endif - #if (OPTION_MEMCTLR_C32 == TRUE) - extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockC32; - #define MEM_REC_NB_SUPPORT_C32 MemRecConstructNBBlockC32, - #else - #define MEM_REC_NB_SUPPORT_C32 - #endif - #if (OPTION_MEMCTLR_LN == TRUE) - extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockLN; - #define MEM_REC_NB_SUPPORT_LN MemRecConstructNBBlockLN, - #else - #define MEM_REC_NB_SUPPORT_LN - #endif - #if (OPTION_MEMCTLR_ON == TRUE) - extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockON; - #define MEM_REC_NB_SUPPORT_ON MemRecConstructNBBlockON, - #else - #define MEM_REC_NB_SUPPORT_ON - #endif - - MEM_REC_NB_CONSTRUCTOR* MemRecNBInstalled[] = { - MEM_REC_NB_SUPPORT_DR - MEM_REC_NB_SUPPORT_RB - MEM_REC_NB_SUPPORT_DA - MEM_REC_NB_SUPPORT_PH - MEM_REC_NB_SUPPORT_HY - MEM_REC_NB_SUPPORT_C32 - MEM_REC_NB_SUPPORT_LN - MEM_REC_NB_SUPPORT_OR - MEM_REC_NB_SUPPORT_ON - MEM_REC_NB_SUPPORT_NI - NULL - }; - - #define MEM_REC_TECH_CONSTRUCTOR_DDR2 - #if (OPTION_DDR3 == TRUE) - extern MEM_REC_TECH_CONSTRUCTOR MemRecConstructTechBlock3; - #define MEM_REC_TECH_CONSTRUCTOR_DDR3 MemRecConstructTechBlock3, - #else - #define MEM_REC_TECH_CONSTRUCTOR_DDR3 - #endif - - MEM_REC_TECH_CONSTRUCTOR* MemRecTechInstalled[] = { - MEM_REC_TECH_CONSTRUCTOR_DDR3 - MEM_REC_TECH_CONSTRUCTOR_DDR2 - NULL - }; - - #if OPTION_MEMCTLR_DR - #define PSC_REC_DR_UDIMM_DDR2 - #define PSC_REC_DR_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb, - #define PSC_REC_DR_RDIMM_DDR2 - #define PSC_REC_DR_RDIMM_DDR3 MemRecNGetPsCfgRDIMM3Nb, - #define PSC_REC_DR_SODIMM_DDR2 - #define PSC_REC_DR_SODIMM_DDR3 MemRecNGetPsCfgSODIMM3Nb, - #endif - #if ((OPTION_MEMCTLR_DA == TRUE) || (OPTION_MEMCTLR_Ni == TRUE) || (OPTION_MEMCTLR_PH == TRUE) || (OPTION_MEMCTLR_RB == TRUE)) - #define PSC_REC_DA_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb, - #define PSC_REC_DA_SODIMM_DDR2 - #define PSC_REC_DA_SODIMM_DDR3 MemRecNGetPsCfgSODIMM3Nb, - #endif - #if OPTION_MEMCTLR_HY - #define PSC_REC_HY_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb, - #define PSC_REC_HY_RDIMM_DDR3 MemRecNGetPsCfgRDIMM3Nb, - #endif - #if OPTION_MEMCTLR_C32 - #define PSC_REC_C32_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb, - #define PSC_REC_C32_RDIMM_DDR3 MemRecNGetPsCfgRDIMM3Nb, - #endif - #if OPTION_MEMCTLR_OR - #define PSC_REC_OR_UDIMM_DDR3 //MemRecNGetPsCfgUDIMM3OR, - #define PSC_REC_OR_RDIMM_DDR3 //MemRecNGetPsCfgRDIMM3OR, - #endif - - #ifndef PSC_REC_DR_UDIMM_DDR2 - #define PSC_REC_DR_UDIMM_DDR2 - #endif - #ifndef PSC_REC_DR_UDIMM_DDR3 - #define PSC_REC_DR_UDIMM_DDR3 - #endif - #ifndef PSC_REC_DR_RDIMM_DDR2 - #define PSC_REC_DR_RDIMM_DDR2 - #endif - #ifndef PSC_REC_DR_RDIMM_DDR3 - #define PSC_REC_DR_RDIMM_DDR3 - #endif - #ifndef PSC_REC_DR_SODIMM_DDR2 - #define PSC_REC_DR_SODIMM_DDR2 - #endif - #ifndef PSC_REC_DR_SODIMM_DDR3 - #define PSC_REC_DR_SODIMM_DDR3 - #endif - #ifndef PSC_REC_DA_UDIMM_DDR3 - #define PSC_REC_DA_UDIMM_DDR3 - #endif - #ifndef PSC_REC_DA_SODIMM_DDR2 - #define PSC_REC_DA_SODIMM_DDR2 - #endif - #ifndef PSC_REC_DA_SODIMM_DDR3 - #define PSC_REC_DA_SODIMM_DDR3 - #endif - #ifndef PSC_REC_HY_UDIMM_DDR3 - #define PSC_REC_HY_UDIMM_DDR3 - #endif - #ifndef PSC_REC_HY_RDIMM_DDR3 - #define PSC_REC_HY_RDIMM_DDR3 - #endif - #ifndef PSC_REC_C32_UDIMM_DDR3 - #define PSC_REC_C32_UDIMM_DDR3 - #endif - #ifndef PSC_REC_C32_RDIMM_DDR3 - #define PSC_REC_C32_RDIMM_DDR3 - #endif - #ifndef PSC_REC_OR_UDIMM_DDR3 - #define PSC_REC_OR_UDIMM_DDR3 - #endif - #ifndef PSC_REC_OR_RDIMM_DDR3 - #define PSC_REC_OR_RDIMM_DDR3 - #endif - - MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[] = { - PSC_REC_DR_UDIMM_DDR2 - PSC_REC_DR_RDIMM_DDR2 - PSC_REC_DR_SODIMM_DDR2 - PSC_REC_DR_UDIMM_DDR3 - PSC_REC_DR_RDIMM_DDR3 - PSC_REC_DR_SODIMM_DDR3 - PSC_REC_DA_SODIMM_DDR2 - PSC_REC_DA_UDIMM_DDR3 - PSC_REC_DA_SODIMM_DDR3 - PSC_REC_HY_UDIMM_DDR3 - PSC_REC_HY_RDIMM_DDR3 - PSC_REC_C32_UDIMM_DDR3 - PSC_REC_C32_RDIMM_DDR3 - PSC_REC_OR_UDIMM_DDR3 - PSC_REC_OR_RDIMM_DDR3 - NULL - }; - - /*--------------------------------------------------------------------------------------------------- - * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION - * - * - *--------------------------------------------------------------------------------------------------- - */ - #define MEM_PSC_REC_FLOW_BLOCK_END NULL - #define PSC_REC_TBL_END NULL - #define MEM_REC_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue - - #if OPTION_MEMCTLR_OR - #if OPTION_UDIMMS - #if OPTION_AM3_SOCKET_SUPPORT - extern PSC_TBL_ENTRY RecDramTermTblEntUAM3; - #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3 &RecDramTermTblEntUAM3, - extern PSC_TBL_ENTRY RecOdtPat1DTblEntUAM3; - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 &RecOdtPat1DTblEntUAM3, - extern PSC_TBL_ENTRY RecOdtPat2DTblEntUAM3; - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 &RecOdtPat2DTblEntUAM3, - extern PSC_TBL_ENTRY RecOdtPat3DTblEntUAM3; - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 &RecOdtPat3DTblEntUAM3, - extern PSC_TBL_ENTRY RecSAOTblEntUAM3; - #define PSC_REC_TBL_OR_UDIMM3_SAO_AM3 &RecSAOTblEntUAM3, - #endif - #if OPTION_C32_SOCKET_SUPPORT - extern PSC_TBL_ENTRY RecDramTermTblEntUC32; - #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32 &RecDramTermTblEntUC32, - extern PSC_TBL_ENTRY RecOdtPat1DTblEntUC32; - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 &RecOdtPat1DTblEntUC32, - extern PSC_TBL_ENTRY RecOdtPat2DTblEntUC32; - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 &RecOdtPat2DTblEntUC32, - extern PSC_TBL_ENTRY RecOdtPat3DTblEntUC32; - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 &RecOdtPat3DTblEntUC32, - extern PSC_TBL_ENTRY RecSAOTblEntUC32; - #define PSC_REC_TBL_OR_UDIMM3_SAO_C32 &RecSAOTblEntUC32, - #endif - #if OPTION_G34_SOCKET_SUPPORT - extern PSC_TBL_ENTRY RecDramTermTblEntUG34; - #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34 &RecDramTermTblEntUG34, - extern PSC_TBL_ENTRY RecOdtPat1DTblEntUG34; - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 &RecOdtPat1DTblEntUG34, - extern PSC_TBL_ENTRY RecOdtPat2DTblEntUG34; - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 &RecOdtPat2DTblEntUG34, - extern PSC_TBL_ENTRY RecOdtPat3DTblEntUG34; - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 &RecOdtPat3DTblEntUG34, - extern PSC_TBL_ENTRY RecSAOTblEntUG34; - #define PSC_REC_TBL_OR_UDIMM3_SAO_G34 &RecSAOTblEntUG34, - #endif - #endif - #if OPTION_RDIMMS - #if OPTION_C32_SOCKET_SUPPORT - extern PSC_TBL_ENTRY RecDramTermTblEntRC32; - #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32 &RecDramTermTblEntRC32, - extern PSC_TBL_ENTRY RecOdtPat1DTblEntRC32; - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 &RecOdtPat1DTblEntRC32, - extern PSC_TBL_ENTRY RecOdtPat2DTblEntRC32; - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 &RecOdtPat2DTblEntRC32, - extern PSC_TBL_ENTRY RecOdtPat3DTblEntRC32; - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 &RecOdtPat3DTblEntRC32, - extern PSC_TBL_ENTRY RecSAOTblEntRC32; - #define PSC_REC_TBL_OR_RDIMM3_SAO_C32 &RecSAOTblEntRC32, - extern PSC_TBL_ENTRY RecRC2IBTTblEntRC32; - #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32 &RecRC2IBTTblEntRC32, - #endif - #if OPTION_G34_SOCKET_SUPPORT - extern PSC_TBL_ENTRY RecDramTermTblEntRG34; - #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34 &RecDramTermTblEntRG34, - extern PSC_TBL_ENTRY RecOdtPat1DTblEntRG34; - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 &RecOdtPat1DTblEntRG34, - extern PSC_TBL_ENTRY RecOdtPat2DTblEntRG34; - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 &RecOdtPat2DTblEntRG34, - extern PSC_TBL_ENTRY RecOdtPat3DTblEntRG34; - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 &RecOdtPat3DTblEntRG34, - extern PSC_TBL_ENTRY RecSAOTblEntRG34; - #define PSC_REC_TBL_OR_RDIMM3_SAO_G34 &RecSAOTblEntRG34, - extern PSC_TBL_ENTRY RecRC2IBTTblEntRG34; - #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34 &RecRC2IBTTblEntRG34, - #endif - #endif - //#if OPTION_SODIMMS - //#endif - //#if OPTION_LRDIMMS - //#endif - extern PSC_TBL_ENTRY RecMR0WrTblEntry; - #define PSC_REC_TBL_OR_MR0_WR &RecMR0WrTblEntry, - extern PSC_TBL_ENTRY RecMR0CLTblEntry; - #define PSC_REC_TBL_OR_MR0_CL &RecMR0CLTblEntry, - - #ifndef PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3 - #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32 - #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34 - #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 - #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_SAO_AM3 - #define PSC_REC_TBL_OR_UDIMM3_SAO_AM3 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_SAO_C32 - #define PSC_REC_TBL_OR_UDIMM3_SAO_C32 - #endif - #ifndef PSC_REC_TBL_OR_UDIMM3_SAO_G34 - #define PSC_REC_TBL_OR_UDIMM3_SAO_G34 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_AM3 - #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_AM3 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32 - #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34 - #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 - #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_SAO_AM3 - #define PSC_REC_TBL_OR_RDIMM3_SAO_AM3 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_SAO_C32 - #define PSC_REC_TBL_OR_RDIMM3_SAO_C32 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_SAO_G34 - #define PSC_REC_TBL_OR_RDIMM3_SAO_G34 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_RC2IBT_AM3 - #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_AM3 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32 - #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34 - #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_AM3 - #define PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_AM3 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_C32 - #define PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_C32 - #endif - #ifndef PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_G34 - #define PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_G34 - #endif - - PSC_TBL_ENTRY* memRecPSCTblDramTermArrayOR[] = { - PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3 - PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32 - PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34 - PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_AM3 - PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32 - PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34 - PSC_REC_TBL_END - }; - - PSC_TBL_ENTRY* memRecPSCTblODTPatArrayOR[] = { - PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 - PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 - PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 - PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 - PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 - PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 - PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 - PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 - PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 - PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 - PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 - PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 - PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 - PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 - PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 - PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 - PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 - PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 - PSC_REC_TBL_END - }; - - PSC_TBL_ENTRY* memRecPSCTblSAOArrayOR[] = { - PSC_REC_TBL_OR_UDIMM3_SAO_AM3 - PSC_REC_TBL_OR_UDIMM3_SAO_C32 - PSC_REC_TBL_OR_UDIMM3_SAO_G34 - PSC_REC_TBL_OR_RDIMM3_SAO_AM3 - PSC_REC_TBL_OR_RDIMM3_SAO_C32 - PSC_REC_TBL_OR_RDIMM3_SAO_G34 - PSC_REC_TBL_END - }; - - PSC_TBL_ENTRY* memRecPSCTblMR0WRArrayOR[] = { - PSC_REC_TBL_OR_MR0_WR - PSC_REC_TBL_END - }; - - PSC_TBL_ENTRY* memRecPSCTblMR0CLArrayOR[] = { - PSC_REC_TBL_OR_MR0_CL - PSC_REC_TBL_END - }; - - PSC_TBL_ENTRY* memRecPSCTblRC2IBTArrayOR[] = { - PSC_REC_TBL_OR_RDIMM3_RC2IBT_AM3 - PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32 - PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34 - PSC_REC_TBL_END - }; - - MEM_PSC_TABLE_BLOCK memRecPSCTblBlockOr = { - NULL, - (PSC_TBL_ENTRY **)&memRecPSCTblDramTermArrayOR, - (PSC_TBL_ENTRY **)&memRecPSCTblODTPatArrayOR, - (PSC_TBL_ENTRY **)&memRecPSCTblSAOArrayOR, - (PSC_TBL_ENTRY **)&memRecPSCTblMR0WRArrayOR, - (PSC_TBL_ENTRY **)&memRecPSCTblMR0CLArrayOR, - (PSC_TBL_ENTRY **)&memRecPSCTblRC2IBTArrayOR, - NULL, - NULL, - NULL, - NULL, - NULL - }; - - extern MEM_PSC_FLOW MemPRecGetRttNomWr; - #define PSC_REC_FLOW_OR_DRAM_TERM MemPRecGetRttNomWr - extern MEM_PSC_FLOW MemPRecGetODTPattern; - #define PSC_REC_FLOW_OR_ODT_PATTERN MemPRecGetODTPattern - extern MEM_PSC_FLOW MemPRecGetSAO; - #define PSC_REC_FLOW_OR_SAO MemPRecGetSAO - extern MEM_PSC_FLOW MemPRecGetMR0WrCL; - #define PSC_REC_FLOW_OR_MR0_WRCL MemPRecGetMR0WrCL - #if OPTION_RDIMMS - extern MEM_PSC_FLOW MemPRecGetRC2IBT; - #define PSC_REC_FLOW_OR_RC2_IBT MemPRecGetRC2IBT - #endif - //#if OPTION_LRDIMMS - extern MEM_PSC_FLOW MemPRecGetLRIBT; - #define PSC_REC_FLOW_OR_LR_IBT MemPRecGetLRIBT - extern MEM_PSC_FLOW MemPRecGetLRNPR; - #define PSC_REC_FLOW_OR_LR_NPR MemPRecGetLRNPR - extern MEM_PSC_FLOW MemPRecGetLRNLR; - #define PSC_REC_FLOW_OR_LR_NLR MemPRecGetLRNLR - //#endif - #ifndef PSC_REC_FLOW_OR_DRAM_TERM - #define PSC_REC_FLOW_OR_DRAM_TERM MEM_REC_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_REC_FLOW_OR_ODT_PATTERN - #define PSC_REC_FLOW_OR_ODT_PATTERN MEM_REC_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_REC_FLOW_OR_SAO - #define PSC_REC_FLOW_OR_SAO MEM_REC_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_REC_FLOW_OR_MR0_WRCL - #define PSC_REC_FLOW_OR_MR0_WRCL MEM_REC_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_REC_FLOW_OR_RC2_IBT - #define PSC_REC_FLOW_OR_RC2_IBT MEM_REC_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_REC_FLOW_OR_LR_IBT - #define PSC_REC_FLOW_OR_LR_IBT MEM_REC_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_REC_FLOW_OR_LR_NPR - #define PSC_REC_FLOW_OR_LR_NPR MEM_REC_PSC_FLOW_DEFTRUE - #endif - #ifndef PSC_REC_FLOW_OR_LR_NLR - #define PSC_REC_FLOW_OR_LR_NLR MEM_REC_PSC_FLOW_DEFTRUE - #endif - MEM_PSC_FLOW_BLOCK memRecPlatSpecFlowOR = { - &memRecPSCTblBlockOr, - NULL, - PSC_REC_FLOW_OR_DRAM_TERM, - PSC_REC_FLOW_OR_ODT_PATTERN, - PSC_REC_FLOW_OR_SAO, - PSC_REC_FLOW_OR_MR0_WRCL, - PSC_REC_FLOW_OR_RC2_IBT, - NULL, - PSC_REC_FLOW_OR_LR_IBT, - PSC_REC_FLOW_OR_LR_NPR, - PSC_REC_FLOW_OR_LR_NLR - }; - #define MEM_PSC_REC_FLOW_BLOCK_OR &memRecPlatSpecFlowOR, - #else - #define MEM_PSC_REC_FLOW_BLOCK_OR - #endif - - MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[] = { - MEM_PSC_REC_FLOW_BLOCK_OR - MEM_PSC_REC_FLOW_BLOCK_END - }; - -#else - /*--------------------------------------------------------------------------------------------------- - * DEFAULT TECHNOLOGY BLOCK - * - * - *--------------------------------------------------------------------------------------------------- - */ - MEM_TECH_CONSTRUCTOR* MemRecTechInstalled[] = { // Types of technology installed - NULL - }; - /*--------------------------------------------------------------------------------------------------- - * DEFAULT NORTHBRIDGE SUPPORT LIST - * - * - *--------------------------------------------------------------------------------------------------- - */ - MEM_NB_SUPPORT MemRecNBInstalled[] = { - NULL - }; - /*---------------------------------------------------------------------- - * DEFAULT PSCFG DEFINITIONS - * - *---------------------------------------------------------------------- - */ - MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[] = { - NULL - }; - /*---------------------------------------------------------------------- - * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION - * - *---------------------------------------------------------------------- - */ - MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[] = { - NULL - }; -#endif -#endif // _OPTION_MEMORY_RECOVERY_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/Include/OptionMsgBasedC1eInstall.h b/src/vendorcode/amd/agesa/Include/OptionMsgBasedC1eInstall.h deleted file mode 100644 index b1d91d99cd..0000000000 --- a/src/vendorcode/amd/agesa/Include/OptionMsgBasedC1eInstall.h +++ /dev/null @@ -1,119 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Message-Based C1e - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _OPTION_MSG_BASED_C1E_INSTALL_H_ -#define _OPTION_MSG_BASED_C1E_INSTALL_H_ - -#include "cpuMsgBasedC1e.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_MSG_BASED_C1E_FEAT -#define F10_MSG_BASED_C1E_SUPPORT -#define F15_MSG_BASED_C1E_SUPPORT -#if OPTION_MSG_BASED_C1E == TRUE - #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) - - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #if OPTION_FAMILY10H_HY == TRUE - #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e; - #undef OPTION_MSG_BASED_C1E_FEAT - #define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e, - #endif - #endif - #endif - #endif - - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e; - #undef OPTION_MSG_BASED_C1E_FEAT - #define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e, - #endif - #endif - #endif - - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #if OPTION_FAMILY10H_HY == TRUE - #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE) - extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F10MsgBasedC1e; - #undef F10_MSG_BASED_C1E_SUPPORT - #define F10_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_10_HY, &F10MsgBasedC1e}, - #endif - #endif - #endif - #endif - - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE) - extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F15MsgBasedC1e; - #undef F15_MSG_BASED_C1E_SUPPORT - #define F15_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_15, &F15MsgBasedC1e}, - #endif - #endif - #endif - - CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MsgBasedC1eFamilyServiceArray[] = - { - F10_MSG_BASED_C1E_SUPPORT - F15_MSG_BASED_C1E_SUPPORT - {0, NULL} - }; - CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MsgBasedC1eFamilyServiceTable = - { - (sizeof (MsgBasedC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &MsgBasedC1eFamilyServiceArray[0] - }; - #endif -#endif -#endif // _OPTION_MSG_BASED_C1E_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/Include/OptionMultiSocket.h b/src/vendorcode/amd/agesa/Include/OptionMultiSocket.h deleted file mode 100644 index 1e3fd142b1..0000000000 --- a/src/vendorcode/amd/agesa/Include/OptionMultiSocket.h +++ /dev/null @@ -1,169 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Multi-socket option API. - * - * Contains structures and values used to control the multi-socket option code. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: OPTION - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _OPTION_MULTISOCKET_H_ -#define _OPTION_MULTISOCKET_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ - -/** - * This function loops through all possible socket locations, gathering the number - * of power management steps each populated socket requires, and returns the - * highest number. - * - * @param[out] NumSystemSteps Maximum number of system steps required - * @param[in] StdHeader Config handle for library and services - * - */ -typedef VOID OPTION_MULTISOCKET_PM_STEPS ( - OUT UINT8 *NumSystemSteps, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * This function loops through all possible socket locations, starting core 0 of - * each populated socket to perform the passed in AP_TASK. After starting all - * other core 0s, the BSC will perform the AP_TASK as well. This must be run by - * the system BSC only. - * - * @param[in] TaskPtr Function descriptor - * @param[in] StdHeader Config handle for library and services - * @param[in] ConfigParams AMD entry point's CPU parameter structure - * - */ -typedef VOID OPTION_MULTISOCKET_PM_CORE0_TASK ( - IN VOID *TaskPtr, - IN AMD_CONFIG_PARAMS *StdHeader, - IN VOID *ConfigParams - ); - -/** - * This function loops through all possible socket locations, comparing the - * maximum NB frequencies to determine the slowest. This function also - * determines if all coherent NB frequencies are equivalent. - * - * @param[in] NbPstate NB P-state number to check (0 = fastest) - * @param[in] PlatformConfig Platform profile/build option config structure. - * @param[out] SystemNbCofNumerator NB frequency numerator for the system in MHz - * @param[out] SystemNbCofDenominator NB frequency denominator for the system - * @param[out] SystemNbCofsMatch Whether or not all NB frequencies are equivalent - * @param[out] NbPstateIsEnabledOnAllCPUs Whether or not NbPstate is valid on all CPUs - * @param[in] StdHeader Config handle for library and services - * - * @retval TRUE At least one processor has NbPstate enabled. - * @retval FALSE NbPstate is disabled on all CPUs - */ -typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF ( - IN UINT32 NbPstate, - IN PLATFORM_CONFIGURATION *PlatformConfig, - OUT UINT32 *SystemNbCofNumerator, - OUT UINT32 *SystemNbCofDenominator, - OUT BOOLEAN *SystemNbCofsMatch, - OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * This function loops through all possible socket locations, checking whether - * any populated sockets require NB COF VID programming. - * - * @param[in] StdHeader Config handle for library and services - * - */ -typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF_UPDATE ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -/** - * This function loops through all possible socket locations, collecting any - * power management initialization errors that may have occurred. These errors - * are transferred from the core 0s of the socket in which the errors occurred - * to the BSC's heap. The BSC's heap is then searched for the most severe error - * that occurred, and returns it. This function must be called by the BSC only. - * - * @param[in] StdHeader Config handle for library and services - * - */ -typedef AGESA_STATUS OPTION_MULTISOCKET_PM_GET_EVENTS ( - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#define MULTISOCKET_STRUCT_VERSION 0x01 - -/** - * Provide build configuration of cpu multi-socket or single socket support. - * - */ -typedef struct { - UINT16 OptMultiSocketVersion; ///< Table version - OPTION_MULTISOCKET_PM_STEPS *GetNumberOfSystemPmSteps; ///< Method: Get number of power mgt tasks - OPTION_MULTISOCKET_PM_CORE0_TASK *BscRunCodeOnAllSystemCore0s; ///< Method: Perform tasks on Core 0 of each processor - OPTION_MULTISOCKET_PM_NB_COF *GetSystemNbPstateSettings; ///< Method: Find the limiting Northbridge frequency in the system. - OPTION_MULTISOCKET_PM_NB_COF_UPDATE *GetSystemNbCofVidUpdate; ///< Method: Determine if any Northbridges in the system need to update their COF/VID. - OPTION_MULTISOCKET_PM_GET_EVENTS *BscRetrievePmEarlyInitErrors; ///< Method: Gathers error information from all Core 0s. -} OPTION_MULTISOCKET_CONFIGURATION; - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - - -#endif // _OPTION_MULTISOCKET_H_ diff --git a/src/vendorcode/amd/agesa/Include/OptionMultiSocketInstall.h b/src/vendorcode/amd/agesa/Include/OptionMultiSocketInstall.h deleted file mode 100644 index 188212e838..0000000000 --- a/src/vendorcode/amd/agesa/Include/OptionMultiSocketInstall.h +++ /dev/null @@ -1,92 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Multiple Socket Support - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _OPTION_MULTISOCKET_INSTALL_H_ -#define _OPTION_MULTISOCKET_INSTALL_H_ - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#ifndef OPTION_MULTISOCKET - #error BLDOPT: Option not defined: "OPTION_MULTISOCKET" -#endif - -#if OPTION_MULTISOCKET == TRUE - OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrMulti; - #define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrMulti - OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sMulti; - #define CORE0_PM_TASK RunCodeOnAllSystemCore0sMulti - OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofMulti; - #define GET_SYS_NB_COF GetSystemNbCofMulti - OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti; - #define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti - OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsMulti; - #define GET_EARLY_PM_ERRORS GetEarlyPmErrorsMulti -#else - OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrSingle; - #define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrSingle - OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sSingle; - #define CORE0_PM_TASK RunCodeOnAllSystemCore0sSingle - OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofSingle; - #define GET_SYS_NB_COF GetSystemNbCofSingle - OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle; - #define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle - OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsSingle; - #define GET_EARLY_PM_ERRORS GetEarlyPmErrorsSingle -#endif - -/* Declare the instance of the DMI option configuration structure */ -OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration = { - MULTISOCKET_STRUCT_VERSION, - GET_NUM_PM_STEPS, - CORE0_PM_TASK, - GET_SYS_NB_COF, - GET_SYS_NB_COF_UPDATE, - GET_EARLY_PM_ERRORS -}; - -#endif // _OPTION_MULTISOCKET_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/Include/OptionPreserveMailboxInstall.h b/src/vendorcode/amd/agesa/Include/OptionPreserveMailboxInstall.h deleted file mode 100644 index bd7d3f4fbc..0000000000 --- a/src/vendorcode/amd/agesa/Include/OptionPreserveMailboxInstall.h +++ /dev/null @@ -1,107 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: Preserve Mailbox - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _OPTION_PRESERVE_MAILBOX_INSTALL_H_ -#define _OPTION_PRESERVE_MAILBOX_INSTALL_H_ - -#include "PreserveMailbox.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_PRESERVE_MAILBOX_FEAT -#define F10_PRESERVE_MAILBOX_SUPPORT -#define F15_PRESERVE_MAILBOX_SUPPORT - -#if ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE)) - #if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H == TRUE)) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePreserveAroundMailbox; - #undef OPTION_PRESERVE_MAILBOX_FEAT - #define OPTION_PRESERVE_MAILBOX_FEAT &CpuFeaturePreserveAroundMailbox, - #endif - #if OPTION_FAMILY10H == TRUE - CONST PCI_ADDR ROMDATA F10PreserveMailboxRegisters [] = { - MAKE_SBDFO (0, 0, 0, 3, 0x168), - MAKE_SBDFO (0, 0, 0, 3, 0x170), - ILLEGAL_SBDFO - }; - CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F10PreserveMailboxServices = { - 0, - TRUE, - (PCI_ADDR *)&F10PreserveMailboxRegisters - }; - #undef F10_PRESERVE_MAILBOX_SUPPORT - #define F10_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_10, &F10PreserveMailboxServices}, - #endif - #if OPTION_FAMILY15H == TRUE - CONST PCI_ADDR ROMDATA F15PreserveMailboxRegisters [] = { - MAKE_SBDFO (0, 0, 0, 3, 0x168), - MAKE_SBDFO (0, 0, 0, 3, 0x170), - ILLEGAL_SBDFO - }; - CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F15PreserveMailboxServices = { - 0, - TRUE, - (PCI_ADDR *)&F15PreserveMailboxRegisters - }; - #undef F15_PRESERVE_MAILBOX_SUPPORT - #define F15_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_15, &F15PreserveMailboxServices}, - #endif - CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PreserveMailboxFamilyServiceArray[] = - { - F10_PRESERVE_MAILBOX_SUPPORT - F15_PRESERVE_MAILBOX_SUPPORT - {0, NULL} - }; - CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PreserveMailboxFamilyServiceTable = - { - (sizeof (PreserveMailboxFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &PreserveMailboxFamilyServiceArray[0] - }; -#endif - -#endif // _OPTION_PRESERVE_MAILBOX_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/Include/OptionPstate.h b/src/vendorcode/amd/agesa/Include/OptionPstate.h deleted file mode 100644 index 27e1478f34..0000000000 --- a/src/vendorcode/amd/agesa/Include/OptionPstate.h +++ /dev/null @@ -1,118 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD ACPI PState option API. - * - * Contains structures and values used to control the PStates option code. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: OPTION - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _OPTION_PSTATE_H_ -#define _OPTION_PSTATE_H_ - -#include "cpuPstateTables.h" - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ - -typedef AGESA_STATUS OPTION_SSDT_FEATURE ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT VOID **AcpiPstatePtr - ); - -typedef UINT32 OPTION_ACPI_FEATURE ( - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN PSTATE_LEVELING *PStateLevelingBuffer, - IN OUT VOID **AcpiPStatePtr, - IN UINT8 LocalApicId, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -typedef AGESA_STATUS OPTION_PSTATE_GATHER ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr - ); - -typedef AGESA_STATUS OPTION_PSTATE_LEVELING ( - IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr, - IN AMD_CONFIG_PARAMS *StdHeader - ); - -#define PSTATE_STRUCT_VERSION 0x01 - -/// Indirection vectors for POST/PEI PState code -typedef struct { - UINT16 OptPstateVersion; ///< revision of this structure - OPTION_PSTATE_GATHER *PstateGather; ///< vector for data gathering routine - OPTION_PSTATE_LEVELING *PstateLeveling; ///< vector for leveling routine -} OPTION_PSTATE_POST_CONFIGURATION; - -/// Indirection vectors for LATE/DXE PState code -typedef struct { - UINT16 OptPstateVersion; ///< revision of this structure - OPTION_SSDT_FEATURE *SsdtFeature; ///< vector for routine to generate SSDT - OPTION_ACPI_FEATURE *PstateFeature; ///< vector for routine to generate ACPI PState Objects - OPTION_ACPI_FEATURE *CstateFeature; ///< vector for routine to generate ACPI CState Objects - BOOLEAN CfgPstatePpc; ///< boolean for creating _PPC method - BOOLEAN CfgPstatePct; ///< boolean for creating _PCT method - BOOLEAN CfgPstatePsd; ///< boolean for creating _PSD method - BOOLEAN CfgPstatePss; ///< boolean for creating _PSS method - BOOLEAN CfgPstateXpss; ///< boolean for creating _XPSS method -} OPTION_PSTATE_LATE_CONFIGURATION; - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -#endif // _OPTION_PSTATE_H_ diff --git a/src/vendorcode/amd/agesa/Include/OptionPstateInstall.h b/src/vendorcode/amd/agesa/Include/OptionPstateInstall.h deleted file mode 100644 index 11ae4d3cfe..0000000000 --- a/src/vendorcode/amd/agesa/Include/OptionPstateInstall.h +++ /dev/null @@ -1,243 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: PState - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _OPTION_PSTATE_INSTALL_H_ -#define _OPTION_PSTATE_INSTALL_H_ - -#include "cpuPstateTables.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ - -#define F10_PSTATE_SERVICE_SUPPORT -#define F12_PSTATE_SERVICE_SUPPORT -#define F14_PSTATE_SERVICE_SUPPORT -#define F15_PSTATE_SERVICE_SUPPORT - -#if ((AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE)) - // - //Define Pstate CPU Family service - // - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F10PstateServices; - #undef F10_PSTATE_SERVICE_SUPPORT - #define F10_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_10, &F10PstateServices}, - #endif - #endif - - #ifdef OPTION_FAMILY12H - #if OPTION_FAMILY12H == TRUE - extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F12PstateServices; - #undef F12_PSTATE_SERVICE_SUPPORT - #define F12_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_12, &F12PstateServices}, - #endif - #endif - - #ifdef OPTION_FAMILY14H - #if OPTION_FAMILY14H == TRUE - extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F14PstateServices; - #undef F14_PSTATE_SERVICE_SUPPORT - #define F14_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_14, &F14PstateServices}, - #endif - #endif - - #ifdef OPTION_FAMILY15H - #if OPTION_FAMILY15H == TRUE - extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15PstateServices; - #undef F15_PSTATE_SERVICE_SUPPORT - #define F15_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15, &F15PstateServices}, - #endif - #endif - // - //Define ACPI Pstate objects. - // - #ifndef OPTION_ACPI_PSTATES - #error BLDOPT: Option not defined: "OPTION_ACPI_PSTATES" - #endif - #if (OPTION_ACPI_PSTATES == TRUE) - OPTION_SSDT_FEATURE GenerateSsdt; - #define USER_SSDT_MAIN GenerateSsdt - #ifndef OPTION_MULTISOCKET - #error BLDOPT: Option not defined: "OPTION_MULTISOCKET" - #endif - - OPTION_ACPI_FEATURE CreatePStateAcpiTables; - OPTION_PSTATE_GATHER PStateGatherMain; - #if ((OPTION_MULTISOCKET == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE)) - OPTION_PSTATE_LEVELING PStateLevelingMain; - #define USER_PSTATE_OPTION_LEVEL PStateLevelingMain - #else - OPTION_PSTATE_LEVELING PStateLevelingStub; - #define USER_PSTATE_OPTION_LEVEL PStateLevelingStub - #endif - #if AGESA_ENTRY_INIT_LATE == TRUE - #define USER_PSTATE_OPTION_MAIN CreatePStateAcpiTables - #else - OPTION_ACPI_FEATURE CreateAcpiTablesStub; - #define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub - #endif - #if AGESA_ENTRY_INIT_POST == TRUE - #define USER_PSTATE_OPTION_GATHER PStateGatherMain - #else - OPTION_PSTATE_GATHER PStateGatherStub; - #define USER_PSTATE_OPTION_GATHER PStateGatherStub - #endif - #if CFG_ACPI_PSTATES_PPC == TRUE - #define USER_PSTATE_CFG_PPC TRUE - #else - #define USER_PSTATE_CFG_PPC FALSE - #endif - #if CFG_ACPI_PSTATES_PCT == TRUE - #define USER_PSTATE_CFG_PCT TRUE - #else - #define USER_PSTATE_CFG_PCT FALSE - #endif - #if CFG_ACPI_PSTATES_PSD == TRUE - #define USER_PSTATE_CFG_PSD TRUE - #else - #define USER_PSTATE_CFG_PSD FALSE - #endif - #if CFG_ACPI_PSTATES_PSS == TRUE - #define USER_PSTATE_CFG_PSS TRUE - #else - #define USER_PSTATE_CFG_PSS FALSE - #endif - #if CFG_ACPI_PSTATES_XPSS == TRUE - #define USER_PSTATE_CFG_XPSS TRUE - #else - #define USER_PSTATE_CFG_XPSS FALSE - #endif - - #if OPTION_IO_CSTATE == TRUE - OPTION_ACPI_FEATURE CreateCStateAcpiTables; - #define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables - #else - OPTION_ACPI_FEATURE CreateAcpiTablesStub; - #define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub - #endif - #else - OPTION_SSDT_FEATURE GenerateSsdtStub; - OPTION_ACPI_FEATURE CreateAcpiTablesStub; - OPTION_PSTATE_GATHER PStateGatherStub; - OPTION_PSTATE_LEVELING PStateLevelingStub; - #define USER_SSDT_MAIN GenerateSsdtStub - #define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub - #define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub - #define USER_PSTATE_OPTION_GATHER PStateGatherStub - #define USER_PSTATE_OPTION_LEVEL PStateLevelingStub - #define USER_PSTATE_CFG_PPC FALSE - #define USER_PSTATE_CFG_PCT FALSE - #define USER_PSTATE_CFG_PSD FALSE - #define USER_PSTATE_CFG_PSS FALSE - #define USER_PSTATE_CFG_XPSS FALSE - - // If ACPI Objects are disabled for PStates, we still need to check - // whether ACPI Objects are enabled for CStates - #if OPTION_IO_CSTATE == TRUE - OPTION_SSDT_FEATURE GenerateSsdt; - OPTION_PSTATE_GATHER PStateGatherMain; - OPTION_ACPI_FEATURE CreateCStateAcpiTables; - #undef USER_SSDT_MAIN - #define USER_SSDT_MAIN GenerateSsdt - #undef USER_PSTATE_OPTION_GATHER - #define USER_PSTATE_OPTION_GATHER PStateGatherMain - #undef USER_CSTATE_OPTION_MAIN - #define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables - #endif - #endif -#else - OPTION_SSDT_FEATURE GenerateSsdtStub; - OPTION_ACPI_FEATURE CreateAcpiTablesStub; - OPTION_PSTATE_GATHER PStateGatherStub; - OPTION_PSTATE_LEVELING PStateLevelingStub; - #define USER_SSDT_MAIN GenerateSsdtStub - #define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub - #define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub - #define USER_PSTATE_OPTION_GATHER PStateGatherStub - #define USER_PSTATE_OPTION_LEVEL PStateLevelingStub - #define USER_PSTATE_CFG_PPC FALSE - #define USER_PSTATE_CFG_PCT FALSE - #define USER_PSTATE_CFG_PSD FALSE - #define USER_PSTATE_CFG_PSS FALSE - #define USER_PSTATE_CFG_XPSS FALSE -#endif - -/* Declare the instance of the PSTATE option configuration structure */ -OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration = { - PSTATE_STRUCT_VERSION, - USER_PSTATE_OPTION_GATHER, - USER_PSTATE_OPTION_LEVEL -}; - -OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration = { - PSTATE_STRUCT_VERSION, - USER_SSDT_MAIN, - USER_PSTATE_OPTION_MAIN, - USER_CSTATE_OPTION_MAIN, - USER_PSTATE_CFG_PPC, - USER_PSTATE_CFG_PCT, - USER_PSTATE_CFG_PSD, - USER_PSTATE_CFG_PSS, - USER_PSTATE_CFG_XPSS -}; - -CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateCpuFamilyServiceArray[] = -{ - F10_PSTATE_SERVICE_SUPPORT - F12_PSTATE_SERVICE_SUPPORT - F14_PSTATE_SERVICE_SUPPORT - F15_PSTATE_SERVICE_SUPPORT - {0, NULL} -}; -CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateFamilyServiceTable = -{ - (sizeof (PstateCpuFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &PstateCpuFamilyServiceArray[0] -}; -#endif // _OPTION_PSTATE_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/Include/OptionS3ScriptInstall.h b/src/vendorcode/amd/agesa/Include/OptionS3ScriptInstall.h deleted file mode 100644 index 2804cae976..0000000000 --- a/src/vendorcode/amd/agesa/Include/OptionS3ScriptInstall.h +++ /dev/null @@ -1,94 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: S3SCRIPT - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _OPTION_S3SCRIPT_INSTALL_H_ -#define _OPTION_S3SCRIPT_INSTALL_H_ - -#include "S3SaveState.h" -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#ifndef OPTION_S3SCRIPT - #define OPTION_S3SCRIPT FALSE //if not define assume PI not use script -#endif - -#if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) - #if OPTION_S3SCRIPT == TRUE - #define P_S3_SCRIPT_INIT S3ScriptInitState - #endif -#endif - -#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - #if OPTION_S3SCRIPT == TRUE - #define P_S3_SCRIPT_RESTORE S3ScriptRestoreState - #endif -#endif - -#ifndef P_S3_SCRIPT_INIT - #define P_S3_SCRIPT_INIT S3ScriptInitStateStub -#endif - -#ifndef P_S3_SCRIPT_RESTORE - #define P_S3_SCRIPT_RESTORE S3ScriptInitStateStub - #undef GNB_S3_DISPATCH_FUNCTION_TABLE -#endif - -#ifndef GNB_S3_DISPATCH_FUNCTION_TABLE - #define GNB_S3_DISPATCH_FUNCTION_TABLE -#endif - -/* Declare the instance of the S3SCRIPT option configuration structure */ -S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration = { - P_S3_SCRIPT_INIT, - P_S3_SCRIPT_RESTORE -}; - -S3_DISPATCH_FUNCTION_ENTRY S3DispatchFunctionTable [] = { - GNB_S3_DISPATCH_FUNCTION_TABLE - {0, NULL} -}; -#endif // _OPTION_S3SCRIPT_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/Include/OptionSlit.h b/src/vendorcode/amd/agesa/Include/OptionSlit.h deleted file mode 100644 index b6c2a5b7fd..0000000000 --- a/src/vendorcode/amd/agesa/Include/OptionSlit.h +++ /dev/null @@ -1,99 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD SLIT option API. - * - * Contains structures and values used to control the SLIT option code. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: OPTION - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _OPTION_SLIT_H_ -#define _OPTION_SLIT_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ - -/** - * Create the ACPI System Locality Distance Information Table. - * - */ -typedef AGESA_STATUS OPTION_SLIT_FEATURE ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN PLATFORM_CONFIGURATION *PlatformConfig, - IN OUT VOID **SlitPtr - ); - -/** - * Clean up DRAM used during SLIT creation. - * - */ -typedef AGESA_STATUS OPTION_SLIT_RELEASE_BUFFER ( - IN OUT AMD_CONFIG_PARAMS *StdHeader - ); - -#define SLIT_STRUCT_VERSION 0x01 - -/// The Option Configuration of SLIT -typedef struct { - UINT16 OptSlitVersion; ///< The version number of SLIT - OPTION_SLIT_FEATURE *SlitFeature; ///< The Option Feature of SLIT - OPTION_SLIT_RELEASE_BUFFER *SlitReleaseBuffer; ///< Release buffer -} OPTION_SLIT_CONFIGURATION; - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - - -#endif // _OPTION_SLIT_H_ diff --git a/src/vendorcode/amd/agesa/Include/OptionSlitInstall.h b/src/vendorcode/amd/agesa/Include/OptionSlitInstall.h deleted file mode 100644 index c8d1c3d792..0000000000 --- a/src/vendorcode/amd/agesa/Include/OptionSlitInstall.h +++ /dev/null @@ -1,82 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: SLIT - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _OPTION_SLIT_INSTALL_H_ -#define _OPTION_SLIT_INSTALL_H_ - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#if AGESA_ENTRY_INIT_LATE == TRUE - #ifndef OPTION_SLIT - #error BLDOPT: Option not defined: "OPTION_SLIT" - #endif - #if OPTION_SLIT == TRUE - OPTION_SLIT_FEATURE GetAcpiSlitMain; - OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBuffer; - #define USER_SLIT_OPTION GetAcpiSlitMain - #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBuffer - #else - OPTION_SLIT_FEATURE GetAcpiSlitStub; - OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub; - #define USER_SLIT_OPTION GetAcpiSlitStub - #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub - #endif -#else - OPTION_SLIT_FEATURE GetAcpiSlitStub; - OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub; - #define USER_SLIT_OPTION GetAcpiSlitStub - #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub -#endif -/* Declare the instance of the SLIT option configuration structure */ -OPTION_SLIT_CONFIGURATION OptionSlitConfiguration = { - SLIT_STRUCT_VERSION, - USER_SLIT_OPTION, - USER_SLIT_RELEASE_BUFFER -}; - -#endif // _OPTION_SLIT_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/Include/OptionSrat.h b/src/vendorcode/amd/agesa/Include/OptionSrat.h deleted file mode 100644 index 9d7c2664bb..0000000000 --- a/src/vendorcode/amd/agesa/Include/OptionSrat.h +++ /dev/null @@ -1,85 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD SRAT option API. - * - * Contains structures and values used to control the SRAT option code. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: OPTION - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _OPTION_SRAT_H_ -#define _OPTION_SRAT_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ - -typedef AGESA_STATUS OPTION_SRAT_FEATURE ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **SratPtr - ); - -#define SRAT_STRUCT_VERSION 0x01 - -/// The Option Configuration of SRAT -typedef struct { - UINT16 OptSratVersion; ///< The version number of SRAT - OPTION_SRAT_FEATURE *SratFeature; ///< The Option Feature of SRAT -} OPTION_SRAT_CONFIGURATION; - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - - -#endif // _OPTION_SRAT_H_ diff --git a/src/vendorcode/amd/agesa/Include/OptionSratInstall.h b/src/vendorcode/amd/agesa/Include/OptionSratInstall.h deleted file mode 100644 index adb8b3ca29..0000000000 --- a/src/vendorcode/amd/agesa/Include/OptionSratInstall.h +++ /dev/null @@ -1,76 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: SRAT - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _OPTION_SRAT_INSTALL_H_ -#define _OPTION_SRAT_INSTALL_H_ - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#if AGESA_ENTRY_INIT_LATE == TRUE - #ifndef OPTION_SRAT - #error BLDOPT: Option not defined: "OPTION_SRAT" - #endif - #if OPTION_SRAT == TRUE - OPTION_SRAT_FEATURE GetAcpiSratMain; - #define USER_SRAT_OPTION GetAcpiSratMain - #else - OPTION_SRAT_FEATURE GetAcpiSratStub; - #define USER_SRAT_OPTION GetAcpiSratStub - #endif -#else - OPTION_SRAT_FEATURE GetAcpiSratStub; - #define USER_SRAT_OPTION GetAcpiSratStub -#endif - -/* Declare the instance of the WHEA option configuration structure */ -OPTION_SRAT_CONFIGURATION OptionSratConfiguration = { - SRAT_STRUCT_VERSION, - USER_SRAT_OPTION -}; - -#endif // _OPTION_WHEA_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/Include/OptionSwC1eInstall.h b/src/vendorcode/amd/agesa/Include/OptionSwC1eInstall.h deleted file mode 100644 index f8d8a06f5e..0000000000 --- a/src/vendorcode/amd/agesa/Include/OptionSwC1eInstall.h +++ /dev/null @@ -1,83 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: SW C1e - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 37157 $ @e \$Date: 2010-09-01 03:24:07 +0800 (Wed, 01 Sep 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _OPTION_SW_C1E_INSTALL_H_ -#define _OPTION_SW_C1E_INSTALL_H_ - -#include "cpuSwC1e.h" - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#define OPTION_SW_C1E_FEAT -#define F10_SW_C1E_SUPPORT -#if AGESA_ENTRY_INIT_EARLY == TRUE - #ifdef OPTION_FAMILY10H - #if OPTION_FAMILY10H == TRUE - #if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE) - extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureSwC1e; - #undef OPTION_SW_C1E_FEAT - #define OPTION_SW_C1E_FEAT &CpuFeatureSwC1e, - extern CONST SW_C1E_FAMILY_SERVICES ROMDATA F10SwC1e; - #undef F10_SW_C1E_SUPPORT - #define F10_SW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10SwC1e}, - #endif - #endif - #endif - CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA SwC1eFamilyServiceArray[] = - { - F10_SW_C1E_SUPPORT - {0, NULL} - }; - CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA SwC1eFamilyServiceTable = - { - (sizeof (SwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)), - &SwC1eFamilyServiceArray[0] - }; -#endif - -#endif // _OPTION_SW_C1E_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/Include/OptionWhea.h b/src/vendorcode/amd/agesa/Include/OptionWhea.h deleted file mode 100644 index 24510304b1..0000000000 --- a/src/vendorcode/amd/agesa/Include/OptionWhea.h +++ /dev/null @@ -1,86 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD WHEA option API. - * - * Contains structures and values used to control the WHEA option code. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: OPTION - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _OPTION_WHEA_H_ -#define _OPTION_WHEA_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ - -typedef AGESA_STATUS OPTION_WHEA_FEATURE ( - IN OUT AMD_CONFIG_PARAMS *StdHeader, - IN OUT VOID **WheaMcePtr, - IN OUT VOID **WheaCmcPtr - ); - -#define WHEA_STRUCT_VERSION 0x01 - -/// The Option Configuration of WHEA -typedef struct { - UINT16 OptWheaVersion; ///< The version number of WHEA - OPTION_WHEA_FEATURE *WheaFeature; ///< The Option Feature of WHEA -} OPTION_WHEA_CONFIGURATION; - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - - -#endif // _OPTION_WHEA_H_ diff --git a/src/vendorcode/amd/agesa/Include/OptionWheaInstall.h b/src/vendorcode/amd/agesa/Include/OptionWheaInstall.h deleted file mode 100644 index 3ec55d2582..0000000000 --- a/src/vendorcode/amd/agesa/Include/OptionWheaInstall.h +++ /dev/null @@ -1,77 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build option: WHEA - * - * Contains AMD AGESA install macros and test conditions. Output is the - * defaults tables reflecting the User's build options selection. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Options - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _OPTION_WHEA_INSTALL_H_ -#define _OPTION_WHEA_INSTALL_H_ - -/* This option is designed to be included into the platform solution install - * file. The platform solution install file will define the options status. - * Check to validate the definition - */ -#if AGESA_ENTRY_INIT_LATE == TRUE - #ifndef OPTION_WHEA - #error BLDOPT: Option not defined: "OPTION_WHEA" - #endif - #if OPTION_WHEA == TRUE - OPTION_WHEA_FEATURE GetAcpiWheaMain; - #define USER_WHEA_OPTION GetAcpiWheaMain - #else - OPTION_WHEA_FEATURE GetAcpiWheaStub; - #define USER_WHEA_OPTION GetAcpiWheaStub - #endif - -#else - OPTION_WHEA_FEATURE GetAcpiWheaStub; - #define USER_WHEA_OPTION GetAcpiWheaStub -#endif - -/* Declare the instance of the WHEA option configuration structure */ -OPTION_WHEA_CONFIGURATION OptionWheaConfiguration = { - WHEA_STRUCT_VERSION, - USER_WHEA_OPTION -}; - -#endif // _OPTION_WHEA_INSTALL_H_ diff --git a/src/vendorcode/amd/agesa/Include/Options.h b/src/vendorcode/amd/agesa/Include/Options.h deleted file mode 100644 index c2fddff04d..0000000000 --- a/src/vendorcode/amd/agesa/Include/Options.h +++ /dev/null @@ -1,94 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AGESA options structures - * - * Contains options control structures for the AGESA build options - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - -#ifndef _OPTIONS_H_ -#define _OPTIONS_H_ - -/** - * Provide topology limits for loops and runtime, based on supported families. - */ -typedef struct { - UINT32 PlatformNumberOfSockets; ///< The limit to the number of processors based on - ///< supported families and other build options. - UINT32 PlatformNumberOfModules; ///< The limit to the number of modules in a processor, based - ///< on supported families. -} OPTIONS_CONFIG_TOPOLOGY; - -/** - * Dispatch Table. - * - * The push high dispatcher uses this table to find what entries are currently in the build image. - */ -typedef struct { - UINT32 FunctionId; ///< The function id specified. - IMAGE_ENTRY EntryPoint; ///< The corresponding entry point to call. -} DISPATCH_TABLE; - -#ifdef BLDCFG_PLATFORM_POWER_POLICY_MODE - #define CFG_PLATFORM_POWER_POLICY_MODE (BLDCFG_PLATFORM_POWER_POLICY_MODE) -#else - #define CFG_PLATFORM_POWER_POLICY_MODE (Performance) -#endif - -#ifdef BLDCFG_PCI_MMIO_BASE - #define CFG_PCI_MMIO_BASE (BLDCFG_PCI_MMIO_BASE) -#else - #define CFG_PCI_MMIO_BASE (0) -#endif - -#ifdef BLDCFG_PCI_MMIO_SIZE - #define CFG_PCI_MMIO_SIZE (BLDCFG_PCI_MMIO_SIZE) -#else - #define CFG_PCI_MMIO_SIZE (0) -#endif - -#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST - #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST) -#else - #define CFG_AP_MTRR_SETTINGS_LIST (NULL) -#endif - -#endif // _OPTIONS_H_ diff --git a/src/vendorcode/amd/agesa/Include/OptionsHt.h b/src/vendorcode/amd/agesa/Include/OptionsHt.h deleted file mode 100644 index 25b1684805..0000000000 --- a/src/vendorcode/amd/agesa/Include/OptionsHt.h +++ /dev/null @@ -1,103 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD HyperTransport option API. - * - * Contains option pre-compile logic. This file is used by the options - * installer and internally by the HT code initializers. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: OPTION - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _OPTION_HT_H_ -#define _OPTION_HT_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ - -/** - * Provide HT build option results - */ -typedef struct { - CONST BOOLEAN IsUsingRecoveryHt; ///< Manual BUID Swap List processing should assume that HT Recovery was used. - CONST BOOLEAN IsSetHtCrcFlood; ///< Enable setting of HT CRC Flood. - ///< Build-time only customizable - @BldCfgItem{BLDCFG_SET_HTCRC_SYNC_FLOOD} - CONST BOOLEAN IsUsingUnitIdClumping; ///< Enable automatically HT Spec compliant Unit Id Clumping. - ///< Build-time only customizable - @BldCfgItem{BLDCFG_USE_UNIT_ID_CLUMPING} - CONST AMD_HT_INTERFACE *HtOptionPlatformDefaults; ///< A set of build time options for HT constructor. - CONST VOID *HtOptionInternalInterface; ///< Use this internal interface initializer. - CONST VOID *HtOptionInternalFeatures; ///< Use this internal feature set initializer. - CONST VOID *HtOptionFamilyNorthbridgeList; ///< Use this list of northbridge initializers. - CONST UINT8 *CONST *HtOptionBuiltinTopologies; ///< Use this list of built-in topologies. -} OPTION_HT_CONFIGURATION; - -typedef AGESA_STATUS -F_OPTION_HT_INIT_RESET ( - IN AMD_CONFIG_PARAMS *StdHeader, - IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface - ); - -typedef F_OPTION_HT_INIT_RESET *PF_OPTION_HT_INIT_RESET; - -/** - * Provide HT reset initialization build option results - */ -typedef struct { - PF_OPTION_HT_INIT_RESET HtInitReset; ///< Method: HT reset initialization. -} OPTION_HT_INIT_RESET; - -/*---------------------------------------------------------------------------------------- - * F U N C T I O N P R O T O T Y P E - *---------------------------------------------------------------------------------------- - */ - -#endif // _OPTION_HT_H_ diff --git a/src/vendorcode/amd/agesa/Include/OptionsPage.h b/src/vendorcode/amd/agesa/Include/OptionsPage.h deleted file mode 100644 index 1287e5ba47..0000000000 --- a/src/vendorcode/amd/agesa/Include/OptionsPage.h +++ /dev/null @@ -1,375 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Create outline and references for Build Configuration and Options Component mainpage documentation. - * - * Design guides, maintenance guides, and general documentation, are - * collected using this file onto the documentation mainpage. - * This file contains doxygen comment blocks, only. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Documentation - * @e \$Revision: 35380 $ @e \$Date: 2010-07-22 00:37:18 +0800 (Thu, 22 Jul 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/** - * @page optionmain Build Configuration and Options Documentation - * - * Additional documentation for the Build Configuration and Options component consists of - * - * - Introduction and Overview to Build Options - * - @subpage platforminstall "Platform Build Options" - * - @subpage bldcfg "Build Configuration Item Cross Reference" - * - @subpage examplecustomizations "Customization Examples" - * - Maintenance Guides: - * - For debug of the Options system, use compiler options - * @n /P /EP /C /FAs @n - * PreProcessor output is produced in an .i file in the directory where the project - * file is located. - * - Design Guides: - * - add here >>> - * - */ - -/** - * @page platforminstall Platform Build Options. - * - * Build options are boolean constants. The purpose of build options is to remove code - * from the build to reduce the overall code size present in the ROM image. Unless - * otherwise specified, the default action is to include all options. If a build option is - * not specifically listed as disabled, then it is included into the build. - * - * The documented build options are imported from a user controlled file for - * processing. The build options for all platform solutions are listed below: - * - * @anchor BLDOPT_REMOVE_UDIMMS_SUPPORT - * @li @e BLDOPT_REMOVE_UDIMMS_SUPPORT @n - * If unbuffered DIMMs are NOT expected to be required in the system, the code that - * handles unbuffered DIMMs can be removed from the build. - * - * @anchor BLDOPT_REMOVE_RDIMMS_SUPPORT - * @li @e BLDOPT_REMOVE_RDIMMS_SUPPORT @n - * If registered DIMMs are NOT expected to be required in the system, the code - * that handles registered DIMMs can be removed from the build. - * - * @anchor BLDOPT_REMOVE_LRDIMMS_SUPPORT - * @li @e BLDOPT_REMOVE_LRDIMMS_SUPPORT @n - * If Load Reduced DIMMs are NOT expected to be required in the system, the code - * that handles Load Reduced DIMMs can be removed from the build. - * - * @note The above three options operate independently from each other; however, at - * least one of the unbuffered , registered or load reduced DIMM options must be present in the build. - * - * @anchor BLDOPT_REMOVE_ECC_SUPPORT - * @li @e BLDOPT_REMOVE_ECC_SUPPORT @n - * Use this option to remove the code for Error Checking & Correction. - * - * @anchor BLDOPT_REMOVE_BANK_INTERLEAVE - * @li @e BLDOPT_REMOVE_BANK_INTERLEAVE @n - * Interleaving is a mechanism to do performance fine tuning. This option - * interleaves memory between banks on a DIMM. - * - * @anchor BLDOPT_REMOVE_DCT_INTERLEAVE - * @li @e BLDOPT_REMOVE_DCT_INTERLEAVE @n - * Interleaving is a mechanism to do performance fine tuning. This option - * interleaves memory from two DRAM controllers. - * - * @anchor BLDOPT_REMOVE_NODE_INTERLEAVE - * @li @e BLDOPT_REMOVE_NODE_INTERLEAVE @n - * Interleaving is a mechanism to do performance fine tuning. This option - * interleaves memory from two HyperTransport nodes. - * - * @anchor BLDOPT_REMOVE_PARALLEL_TRAINING - * @li @e BLDOPT_REMOVE_PARALLEL_TRAINING @n - * For multi-socket systems, training memory in parallel can reduce the time - * needed to boot. - * - * @anchor BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT - * @li @e BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT @n - * Online Spare support is removed by this option. - * - * @anchor BLDOPT_REMOVE_MULTISOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_MULTISOCKET_SUPPORT @n - * Many systems use only a single socket and may benefit in code space to remove - * this code. However, certain processors have multiple HyperTransport nodes - * within a single socket. For these processors, the multi-node support is - * required and this option has no effect. - * - * @anchor BLDOPT_REMOVE_ACPI_PSTATES - * @li @e BLDOPT_REMOVE_ACPI_PSTATES @n - * This option removes the code that generates the ACPI tables used in power - * management. - * - * @anchor BLDOPT_REMOVE_SRAT - * @li @e BLDOPT_REMOVE_SRAT @n - * This option removes the code that generates the SRAT tables used in performance - * tuning. - * - * @anchor BLDOPT_REMOVE_SLIT - * @li @e BLDOPT_REMOVE_SLIT @n - * This option removes the code that generates the SLIT tables used in performance - * tuning. - * - * @anchor BLDOPT_REMOVE_WHEA - * @li @e BLDOPT_REMOVE_WHEA @n - * This option removes the code that generates the WHEA tables used in error - * handling and reporting. - * - * @anchor BLDOPT_REMOVE_DMI - * @li @e BLDOPT_REMOVE_DMI @n - * This option removes the code that generates the DMI tables used in system - * management. - * - * @anchor BLDOPT_REMOVE_DQS_TRAINING - * @li @e BLDOPT_REMOVE_DQS_TRAINING @n - * This option removes the code used in memory performance tuning. - * - * @anchor BLDOPT_REMOVE_EARLY_SAMPLES - * @li @e BLDOPT_REMOVE_EARLY_SAMPLES @n - * Special support for Early Samples is included. Default setting is FALSE. - * - * @anchor BLDOPT_REMOVE_HT_ASSIST - * @li @e BLDOPT_REMOVE_HT_ASSIST @n - * This option removes the code which implements the HT Assist feature. - * - * @anchor BLDOPT_REMOVE_ATM_MODE - * @li @e BLDOPT_REMOVE_ATM_MODE @n - * This option removes the code which implements the ATM feature. - * - * @anchor BLDOPT_REMOVE_MSG_BASED_C1E - * @li @e BLDOPT_REMOVE_MSG_BASED_C1E @n - * This option removes the code which implements the Message Based C1e feature. - * - * @anchor BLDOPT_REMOVE_C6_STATE - * @li @e BLDOPT_REMOVE_C6_STATE @n - * This option removes the code which implements the C6 C-state feature. - * - * @anchor BLDOPT_REMOVE_MEM_RESTORE_SUPPORT - * @li @e BLDOPT_REMOVE_MEM_RESTORE_SUPPORT @n - * This option removes the memory context restore feature. - * - * @anchor BLDOPT_REMOVE_FAMILY_10_SUPPORT - * @li @e BLDOPT_REMOVE_FAMILY_10_SUPPORT @n - * If the package contains support for family 10h processors, remove that support. - * - * @anchor BLDOPT_REMOVE_FAMILY_12_SUPPORT - * @li @e BLDOPT_REMOVE_FAMILY_12_SUPPORT @n - * If the package contains support for family 10h processors, remove that support. - * - * @anchor BLDOPT_REMOVE_FAMILY_14_SUPPORT - * @li @e BLDOPT_REMOVE_FAMILY_14_SUPPORT @n - * If the package contains support for family 14h processors, remove that support. - * - * @anchor BLDOPT_REMOVE_FAMILY_15_SUPPORT - * @li @e BLDOPT_REMOVE_FAMILY_15_SUPPORT @n - * If the package contains support for family 15h processors, remove that support. - * - * @anchor BLDOPT_REMOVE_AM3_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_AM3_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for AM3 sockets. - * - * @anchor BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for ASB2 sockets. - * - * @anchor BLDOPT_REMOVE_C32_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_C32_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for C32 sockets. - * - * @anchor BLDOPT_REMOVE_FM1_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_FM1_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for FM1 sockets. - * - * @anchor BLDOPT_REMOVE_FP1_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_FP1_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for FP1 sockets. - * - * @anchor BLDOPT_REMOVE_FS1_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_FS1_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for FS1 sockets. - * - * @anchor BLDOPT_REMOVE_FT1_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_FT1_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for FT1 sockets. - * - * @anchor BLDOPT_REMOVE_G34_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_G34_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for G34 sockets. - * - * @anchor BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for S1G3 sockets. - * - * @anchor BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT - * @li @e BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT @n - * This option removes the code which implements support for processors packaged for S1G4 sockets. - */ - -/** - * @page examplecustomizations Customization Examples - * - * The Addendum \Options.c file for each platform contains the minimum required - * customizations for that platform. That is, it contains settings which would be needed - * to boot a SimNow! bsd for that platform. - * However, each individual product based on that platform will have customizations necessary for - * that hardware. Since the actual customizations needed vary so much, they are not included in - * the \Options.c. This section provides examples of useful customizations that you can use or - * modify to suit your needs. - * - * @par - * - * Source for the examples shown can be found at Addendum\\Examples. @n - * - * - @ref DeemphasisExamples "Deemphasis List Examples" - * - @ref FrequencyLimitExamples "Frequency Limit Examples" - * - @ref PerfPerWattHt "A performance-per-watt optimization Example" - * - * @anchor DeemphasisExamples - * @par Deemphasis List Examples - * - * These examples customize PLATFORM_CONFIGURATION.PlatformDeemphasisList. - * Source for the deemphasis list examples can be found in DeemphasisExamples.c. @n - * @dontinclude DeemphasisExamples.c - *
    - *
  • - * The following deemphasis list provides an example for a 2P MCM Max Performance configuration. - * High Speed HT frequencies are supported. There is only one non-coherent chain. Note the technique of - * putting specified link matches before all uses of match any. It often works well to specify the non-coherent links - * and use match any for the coherent links. - * @skip DinarDeemphasisList - * @until { - * The non-coherent chain can run up to 2600 MHz. The chain is located on Socket 0, package Link 2. - * @until { - * @line } - * @line { - * @line } - * The coherent links can run up to 3200 MHz. - * @until HT_FREQUENCY_MAX - * @line } - * end of list: - * @until } - * Make this list the build time customized deemphasis list. - * @line define - * - *
  • - * - * The following deemphasis list provides an example for a 4P MCM Max Performance configuration. - * This system has a backplane with connectors for CPU cards and an IO board. So trace lengths are long. - * There can be one to four IO Chains, depending on the IO board. - * @skipline DoubloonDeemphasisList - * @until DoubloonDeemphasisList - * - *
  • - * - * The following deemphasis list further illustrates complex coherent system deemphasis. This is the same - * Dinar system as in an earlier example, but this time all the coherent links are explicitly customized (as - * might be needed if each link has unique characterization). For this example, we skip the non-coherent chains. - * (A real system would have to include them, see example above.) - * @skip DinarPerLinkDeemphasisList - * @until { - * Provide deemphasis settings for the 16 bit, ganged, links, Socket 0 links 0, 1 and Socket 1 links 1 and 2. - * Provide entries to customize all HT3 frequencies at which the links may run. This example covers all HT3 speeds. - * @until { - * @until DcvLevelMinus6 - * @until DcvLevelMinus6 - * @until DcvLevelMinus6 - * @until DcvLevelMinus6 - * Link 3 on both sockets connects different internal die: sublink 0 connects the internal node zeroes, and - * sublink 1 connects the internal node ones. So the link is unganged and both sublinks must be specifically - * customized. - * @until { - * @until DcvLevelMinus6 - * @until DcvLevelMinus6 - * @until DcvLevelMinus6 - * @until DcvLevelMinus6 - * end of list: - * @until define - * - *
- * - * @anchor FrequencyLimitExamples - * @par Frequency Limit Examples - * - * These examples customize AMD_HT_INTERFACE.CpuToCpuPcbLimitsList and AMD_HT_INTERFACE.IoPcbLimitsList. - * Source for the frequency limit examples can be found in FrequencyLimitExamples.c. @n - * @dontinclude FrequencyLimitExamples.c - *
    - *
  • - * The following list provides an example for limiting all coherent links to non-extended frequencies, - * that is, to 2600 MHz or less. - * @skipline NonExtendedCpuToCpuLimitList - * @until { - * Provide the limit customization. Match links from any socket, any package link, to any socket, any package link. Width is not limited. - * @until HT_FREQUENCY_LIMIT_2600M - * End of list: - * @until ; - * Customize the build to use this cpu to cpu frequency limit. - * @until NonExtendedCpuToCpuLimitList - * @n
    • - *
  • - * The following list provides an example for limiting all coherent links to HT 1 frequencies, - * that is, to 1000 MHz or less. This is sometimes useful for test and debug. - * @skipline Ht1CpuToCpuLimitList - * @until Ht1CpuToCpuLimitList - * @n
    • - *
  • - * The following list provides an example for limiting all non-coherent links to 2400 MHz or less. - * The chain is matched by host processor Socket and package Link. The depth can be used to select a particular device - * to device link on the chain. In this example, the chain consists of a single cave device and depth can be set to match any. - * @skipline No2600MhzIoLimitList - * @until No2600MhzIoLimitList - * @n
    • - *
  • - * The following list provides an example for limiting all non-coherent links to the minimum HT 3 frequency, - * that is, to 1200 MHz or less. This can be useful for test and debug. - * @skipline MinHt3IoLimitList - * @until MinHt3IoLimitList - * @n
    • - * - *
- * - * @anchor PerfPerWattHt - * @par Performance-per-Watt Optimization Example - * - * This example customizes AMD_HT_INTERFACE.SkipRegangList. - * Source for the Performance-per-watt Optimization example can be found in PerfPerWatt.c. @n - * @dontinclude PerfPerWatt.c - * To implement a performance-per-watt optimization for MCM processors, use the skip regang structure shown. @n - * @skipline PerfPerWatt - * @until PerfPerWatt - * - */ diff --git a/src/vendorcode/amd/agesa/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/Include/PlatformInstall.h deleted file mode 100644 index 31a311b865..0000000000 --- a/src/vendorcode/amd/agesa/Include/PlatformInstall.h +++ /dev/null @@ -1,2599 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build options for a combination of package type, processor, and features. - * - * This file generates the defaults tables for the all platform solution - * combinations. The documented build options are imported from a user - * controlled file for processing. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 41504 $ @e \$Date: 2010-11-05 21:59:13 +0800 (Fri, 05 Nov 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/***************************************************************************** - * - * Start processing the user options: First, set default settings - * - ****************************************************************************/ - -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. Turn these on in your option c file, not - * here. - */ -// #define AGESA_ENTRY_INIT_RESET TRUE -// #define AGESA_ENTRY_INIT_RECOVERY TRUE -// #define AGESA_ENTRY_INIT_EARLY TRUE -// #define AGESA_ENTRY_INIT_POST TRUE -// #define AGESA_ENTRY_INIT_ENV TRUE -// #define AGESA_ENTRY_INIT_MID TRUE -// #define AGESA_ENTRY_INIT_LATE TRUE -// #define AGESA_ENTRY_INIT_S3SAVE TRUE -// #define AGESA_ENTRY_INIT_RESUME TRUE -// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE - -/* Defaults for private/internal build control settings */ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. - */ - -VOLATILE AMD_MODULE_HEADER mCpuModuleID = { - //ModuleHeaderSignature - // Remove 'DOM$' as temp solution before update BinUtil.exe , - '0000', - //ModuleIdentifier[8] - AGESA_ID, - //ModuleVersion[12] - AGESA_VERSION_STRING, - //ModuleDispatcher - NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher), - //NextBlock - NULL -}; - -/* Process user desired AGESA entry points */ -#ifndef AGESA_ENTRY_INIT_RESET - #define AGESA_ENTRY_INIT_RESET FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RECOVERY - #define AGESA_ENTRY_INIT_RECOVERY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_EARLY - #define AGESA_ENTRY_INIT_EARLY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_POST - #define AGESA_ENTRY_INIT_POST FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_ENV - #define AGESA_ENTRY_INIT_ENV FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_MID - #define AGESA_ENTRY_INIT_MID FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE - #define AGESA_ENTRY_INIT_LATE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_S3SAVE - #define AGESA_ENTRY_INIT_S3SAVE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RESUME - #define AGESA_ENTRY_INIT_RESUME FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE_RESTORE - #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES - #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE -#endif - -/* Default the late AP entry point to off. It can be enabled - by any family that may need the late AP functionality, or - by any feature code that may need it. The IBVs no longer - have control over this entry point. */ -#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK - #undef AGESA_ENTRY_LATE_RUN_AP_TASK -#endif -#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE - - - -/* Process solution defined socket / family installations - * - * As part of the release package for each image, define the options below to select the - * AGESA processor support included in that image. - */ - -/* Default sockets to off */ -#define OPTION_G34_SOCKET_SUPPORT FALSE -#define OPTION_C32_SOCKET_SUPPORT FALSE -#define OPTION_S1G3_SOCKET_SUPPORT FALSE -#define OPTION_S1G4_SOCKET_SUPPORT FALSE -#define OPTION_ASB2_SOCKET_SUPPORT FALSE -#define OPTION_FS1_SOCKET_SUPPORT FALSE -#define OPTION_FM1_SOCKET_SUPPORT FALSE -#define OPTION_FP1_SOCKET_SUPPORT FALSE -#define OPTION_FT1_SOCKET_SUPPORT FALSE -#define OPTION_AM3_SOCKET_SUPPORT FALSE - -/* Default families to off */ -#define OPTION_FAMILY10H FALSE -#define OPTION_FAMILY12H FALSE -#define OPTION_FAMILY14H FALSE -#define OPTION_FAMILY15H FALSE - - -/* Enable the appropriate socket support */ -#ifdef INSTALL_G34_SOCKET_SUPPORT - #if INSTALL_G34_SOCKET_SUPPORT == TRUE - #undef OPTION_G34_SOCKET_SUPPORT - #define OPTION_G34_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_C32_SOCKET_SUPPORT - #if INSTALL_C32_SOCKET_SUPPORT == TRUE - #undef OPTION_C32_SOCKET_SUPPORT - #define OPTION_C32_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_S1G3_SOCKET_SUPPORT - #if INSTALL_S1G3_SOCKET_SUPPORT == TRUE - #undef OPTION_S1G3_SOCKET_SUPPORT - #define OPTION_S1G3_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_S1G4_SOCKET_SUPPORT - #if INSTALL_S1G4_SOCKET_SUPPORT == TRUE - #undef OPTION_S1G4_SOCKET_SUPPORT - #define OPTION_S1G4_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_ASB2_SOCKET_SUPPORT - #if INSTALL_ASB2_SOCKET_SUPPORT == TRUE - #undef OPTION_ASB2_SOCKET_SUPPORT - #define OPTION_ASB2_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_FS1_SOCKET_SUPPORT - #if INSTALL_FS1_SOCKET_SUPPORT == TRUE - #undef OPTION_FS1_SOCKET_SUPPORT - #define OPTION_FS1_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_FM1_SOCKET_SUPPORT - #if INSTALL_FM1_SOCKET_SUPPORT == TRUE - #undef OPTION_FM1_SOCKET_SUPPORT - #define OPTION_FM1_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_FP1_SOCKET_SUPPORT - #if INSTALL_FP1_SOCKET_SUPPORT == TRUE - #undef OPTION_FP1_SOCKET_SUPPORT - #define OPTION_FP1_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_FT1_SOCKET_SUPPORT - #if INSTALL_FT1_SOCKET_SUPPORT == TRUE - #undef OPTION_FT1_SOCKET_SUPPORT - #define OPTION_FT1_SOCKET_SUPPORT TRUE - #endif -#endif - -#ifdef INSTALL_AM3_SOCKET_SUPPORT - #if INSTALL_AM3_SOCKET_SUPPORT == TRUE - #undef OPTION_AM3_SOCKET_SUPPORT - #define OPTION_AM3_SOCKET_SUPPORT TRUE - #endif -#endif - - -/* Enable the appropriate family support */ -// F10 is supported in G34, C32, S1g4, ASB2, S1g3, & AM3 -#ifdef INSTALL_FAMILY_10_SUPPORT - #if INSTALL_FAMILY_10_SUPPORT == TRUE - #undef OPTION_FAMILY10H - #define OPTION_FAMILY10H TRUE - #endif -#endif - -// F12 is supported in FP1, FS1, & FM1 -#ifdef INSTALL_FAMILY_12_SUPPORT - #if INSTALL_FAMILY_12_SUPPORT == TRUE - #undef OPTION_FAMILY12H - #define OPTION_FAMILY12H TRUE - #endif -#endif - -// F14 is supported in FT1 -#ifdef INSTALL_FAMILY_14_SUPPORT - #if INSTALL_FAMILY_14_SUPPORT == TRUE - #undef OPTION_FAMILY14H - #define OPTION_FAMILY14H TRUE - #endif -#endif - -// F15 is supported in G34, C32, & AM3 -#ifdef INSTALL_FAMILY_15_SUPPORT - #if INSTALL_FAMILY_15_SUPPORT == TRUE - #undef OPTION_FAMILY15H - #define OPTION_FAMILY15H TRUE - #endif -#endif - - -/* Turn off families not required by socket designations */ -#if (OPTION_FAMILY10H == TRUE) - #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_S1G3_SOCKET_SUPPORT == FALSE) && (OPTION_S1G4_SOCKET_SUPPORT == FALSE) && (OPTION_ASB2_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE) - #undef OPTION_FAMILY10H - #define OPTION_FAMILY10H FALSE - #endif -#endif - -#if (OPTION_FAMILY12H == TRUE) - #if (OPTION_FS1_SOCKET_SUPPORT == FALSE) && (OPTION_FM1_SOCKET_SUPPORT == FALSE) && (OPTION_FP1_SOCKET_SUPPORT == FALSE) - #undef OPTION_FAMILY12H - #define OPTION_FAMILY12H FALSE - #endif -#endif - -#if (OPTION_FAMILY14H == TRUE) - #if (OPTION_FT1_SOCKET_SUPPORT == FALSE) - #undef OPTION_FAMILY14H - #define OPTION_FAMILY14H FALSE - #endif -#endif - -#if (OPTION_FAMILY15H == TRUE) - #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE) - #undef OPTION_FAMILY15H - #define OPTION_FAMILY15H FALSE - #endif -#endif - - -/* Check for invalid combinations of socket/family */ -#if (OPTION_G34_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE) - #error No G34 supported families included in the build - #endif -#endif - -#if (OPTION_C32_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE) - #error No C32 supported families included in the build - #endif -#endif - -#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == FALSE) - #error No S1G3 supported families included in the build - #endif -#endif - -#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == FALSE) - #error No S1G4 supported families included in the build - #endif -#endif - -#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == FALSE) - #error No ASB2 supported families included in the build - #endif -#endif - -#if (OPTION_FS1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY12H == FALSE) - #error No FS1 supported families included in the build - #endif -#endif - -#if (OPTION_FM1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY12H == FALSE) - #error No FM1 supported families included in the build - #endif -#endif - -#if (OPTION_FP1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY12H == FALSE) - #error No FP1 supported families included in the build - #endif -#endif - -#if (OPTION_FT1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY14H == FALSE) - #error No FT1 supported families included in the build - #endif -#endif - -#if (OPTION_AM3_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE) - #error No AM3 supported families included in the build - #endif -#endif - - -/* Process AGESA private data - * - * Turn on appropriate CPU models and memory controllers, - * as well as some other memory controls. - */ - -/* Default all models to off */ -#define OPTION_FAMILY10H_BL FALSE -#define OPTION_FAMILY10H_DA FALSE -#define OPTION_FAMILY10H_HY FALSE -#define OPTION_FAMILY10H_PH FALSE -#define OPTION_FAMILY10H_RB FALSE -#define OPTION_FAMILY12H_LN FALSE -#define OPTION_FAMILY14H_ON FALSE -#define OPTION_FAMILY15H_OR FALSE - -/* Default all memory controllers to off */ -#define OPTION_MEMCTLR_DR FALSE -#define OPTION_MEMCTLR_HY FALSE -#define OPTION_MEMCTLR_OR FALSE -#define OPTION_MEMCTLR_C32 FALSE -#define OPTION_MEMCTLR_DA FALSE -#define OPTION_MEMCTLR_LN FALSE -#define OPTION_MEMCTLR_ON FALSE -#define OPTION_MEMCTLR_Ni FALSE -#define OPTION_MEMCTLR_PH FALSE -#define OPTION_MEMCTLR_RB FALSE - -/* Default all memory controls to off */ -#define OPTION_HW_WRITE_LEV_TRAINING FALSE -#define OPTION_SW_WRITE_LEV_TRAINING FALSE -#define OPTION_CONTINOUS_PATTERN_GENERATION FALSE -#define OPTION_HW_DQS_REC_EN_TRAINING FALSE -#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING FALSE -#define OPTION_OPT_SW_DQS_REC_EN_TRAINING FALSE -#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING FALSE -#define OPTION_OPT_SW_RD_WR_POS_TRAINING FALSE -#define OPTION_MAX_RD_LAT_TRAINING FALSE -#define OPTION_HW_DRAM_INIT FALSE -#define OPTION_SW_DRAM_INIT FALSE -#define OPTION_S3_MEM_SUPPORT FALSE -#define OPTION_ADDR_TO_CS_TRANSLATOR FALSE - -/* Defaults for public user options */ -#define OPTION_UDIMMS FALSE -#define OPTION_RDIMMS FALSE -#define OPTION_SODIMMS FALSE -#define OPTION_LRDIMMS FALSE -#define OPTION_DDR2 FALSE -#define OPTION_DDR3 FALSE -#define OPTION_ECC FALSE -#define OPTION_BANK_INTERLEAVE FALSE -#define OPTION_DCT_INTERLEAVE FALSE -#define OPTION_NODE_INTERLEAVE FALSE -#define OPTION_PARALLEL_TRAINING FALSE -#define OPTION_ONLINE_SPARE FALSE -#define OPTION_MEM_RESTORE FALSE -#define OPTION_DIMM_EXCLUDE FALSE - -/* Default all CPU controls to off */ -#define OPTION_MULTISOCKET FALSE -#define OPTION_SRAT FALSE -#define OPTION_SLIT FALSE -#define OPTION_HT_ASSIST FALSE -#define OPTION_ATM_MODE FALSE -#define OPTION_CPU_CORELEVLING FALSE -#define OPTION_MSG_BASED_C1E FALSE -#define OPTION_CPU_CFOH FALSE -#define OPTION_C6_STATE FALSE -#define OPTION_IO_CSTATE FALSE -#define OPTION_CPB FALSE -#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE -#define OPTION_S3SCRIPT FALSE -#define OPTION_GFX_RECOVERY FALSE - -/* Enable all private controls based on socket/family enables */ -#if (OPTION_G34_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == TRUE) - #undef OPTION_FAMILY10H_HY - #define OPTION_FAMILY10H_HY TRUE - #undef OPTION_MEMCTLR_HY - #define OPTION_MEMCTLR_HY TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_MULTISOCKET - #define OPTION_MULTISOCKET TRUE - #undef OPTION_SRAT - #define OPTION_SRAT TRUE - #undef OPTION_SLIT - #define OPTION_SLIT TRUE - #undef OPTION_HT_ASSIST - #define OPTION_HT_ASSIST TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_MSG_BASED_C1E - #define OPTION_MSG_BASED_C1E TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_RDIMMS - #define OPTION_RDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_PARALLEL_TRAINING - #define OPTION_PARALLEL_TRAINING TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif - #if (OPTION_FAMILY15H == TRUE) - #undef OPTION_FAMILY15H_OR - #define OPTION_FAMILY15H_OR TRUE - #undef OPTION_MEMCTLR_OR - #define OPTION_MEMCTLR_OR TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_CONTINOUS_PATTERN_GENERATION - #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE - #undef OPTION_HW_DQS_REC_EN_TRAINING - #define OPTION_HW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_MULTISOCKET - #define OPTION_MULTISOCKET TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT - #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE - #undef OPTION_SRAT - #define OPTION_SRAT TRUE - #undef OPTION_SLIT - #define OPTION_SLIT TRUE - #undef OPTION_HT_ASSIST - #define OPTION_HT_ASSIST TRUE - #undef OPTION_ATM_MODE - #define OPTION_ATM_MODE TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_MSG_BASED_C1E - #define OPTION_MSG_BASED_C1E TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_RDIMMS - #define OPTION_RDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_LRDIMMS - #define OPTION_LRDIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_C32_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == TRUE) - #undef OPTION_FAMILY10H_HY - #define OPTION_FAMILY10H_HY TRUE - #undef OPTION_MEMCTLR_C32 - #define OPTION_MEMCTLR_C32 TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_ADDR_TO_CS_TRANSLATOR - #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE - #undef OPTION_MULTISOCKET - #define OPTION_MULTISOCKET TRUE - #undef OPTION_SRAT - #define OPTION_SRAT TRUE - #undef OPTION_SLIT - #define OPTION_SLIT TRUE - #undef OPTION_HT_ASSIST - #define OPTION_HT_ASSIST TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_MSG_BASED_C1E - #define OPTION_MSG_BASED_C1E TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_RDIMMS - #define OPTION_RDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_PARALLEL_TRAINING - #define OPTION_PARALLEL_TRAINING TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif - #if (OPTION_FAMILY15H == TRUE) - #undef OPTION_FAMILY15H_OR - #define OPTION_FAMILY15H_OR TRUE - #undef OPTION_MEMCTLR_OR - #define OPTION_MEMCTLR_OR TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_CONTINOUS_PATTERN_GENERATION - #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE - #undef OPTION_HW_DQS_REC_EN_TRAINING - #define OPTION_HW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_ADDR_TO_CS_TRANSLATOR - #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE - #undef OPTION_MULTISOCKET - #define OPTION_MULTISOCKET TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT - #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE - #undef OPTION_SRAT - #define OPTION_SRAT TRUE - #undef OPTION_SLIT - #define OPTION_SLIT TRUE - #undef OPTION_HT_ASSIST - #define OPTION_HT_ASSIST TRUE - #undef OPTION_ATM_MODE - #define OPTION_ATM_MODE TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_MSG_BASED_C1E - #define OPTION_MSG_BASED_C1E TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_RDIMMS - #define OPTION_RDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_LRDIMMS - #define OPTION_LRDIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == TRUE) - #undef OPTION_FAMILY10H_BL - #define OPTION_FAMILY10H_BL TRUE - #undef OPTION_FAMILY10H_DA - #define OPTION_FAMILY10H_DA TRUE - #undef OPTION_MEMCTLR_DA - #define OPTION_MEMCTLR_DA TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_PARALLEL_TRAINING - #define OPTION_PARALLEL_TRAINING TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == TRUE) - #undef OPTION_FAMILY10H_BL - #define OPTION_FAMILY10H_BL TRUE - #undef OPTION_FAMILY10H_DA - #define OPTION_FAMILY10H_DA TRUE - #undef OPTION_MEMCTLR_DA - #define OPTION_MEMCTLR_DA TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == TRUE) - #undef OPTION_FAMILY10H_BL - #define OPTION_FAMILY10H_BL TRUE - #undef OPTION_FAMILY10H_DA - #define OPTION_FAMILY10H_DA TRUE - #undef OPTION_MEMCTLR_Ni - #define OPTION_MEMCTLR_Ni TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_FS1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY12H == TRUE) - #undef OPTION_FAMILY12H_LN - #define OPTION_FAMILY12H_LN TRUE - #undef OPTION_MEMCTLR_LN - #define OPTION_MEMCTLR_LN TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_CONTINOUS_PATTERN_GENERATION - #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE - #undef OPTION_HW_DQS_REC_EN_TRAINING - #define OPTION_HW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_GFX_RECOVERY - #define OPTION_GFX_RECOVERY TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_S3SCRIPT - #define OPTION_S3SCRIPT TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_FM1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY12H == TRUE) - #undef OPTION_FAMILY12H_LN - #define OPTION_FAMILY12H_LN TRUE - #undef OPTION_MEMCTLR_LN - #define OPTION_MEMCTLR_LN TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_CONTINOUS_PATTERN_GENERATION - #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE - #undef OPTION_HW_DQS_REC_EN_TRAINING - #define OPTION_HW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_GFX_RECOVERY - #define OPTION_GFX_RECOVERY TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_S3SCRIPT - #define OPTION_S3SCRIPT TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_FP1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY12H == TRUE) - #undef OPTION_FAMILY12H_LN - #define OPTION_FAMILY12H_LN TRUE - #undef OPTION_MEMCTLR_LN - #define OPTION_MEMCTLR_LN TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_CONTINOUS_PATTERN_GENERATION - #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE - #undef OPTION_HW_DQS_REC_EN_TRAINING - #define OPTION_HW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_ADDR_TO_CS_TRANSLATOR - #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE - #undef OPTION_GFX_RECOVERY - #define OPTION_GFX_RECOVERY TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_S3SCRIPT - #define OPTION_S3SCRIPT TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_FT1_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY14H == TRUE) - #undef OPTION_FAMILY14H_ON - #define OPTION_FAMILY14H_ON TRUE - #undef OPTION_MEMCTLR_ON - #define OPTION_MEMCTLR_ON TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_CONTINOUS_PATTERN_GENERATION - #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_HW_DQS_REC_EN_TRAINING - #define OPTION_HW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_GFX_RECOVERY - #define OPTION_GFX_RECOVERY TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_S3SCRIPT - #define OPTION_S3SCRIPT TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_AM3_SOCKET_SUPPORT == TRUE) - #if (OPTION_FAMILY10H == TRUE) - #undef OPTION_FAMILY10H_BL - #define OPTION_FAMILY10H_BL TRUE - #undef OPTION_FAMILY10H_DA - #define OPTION_FAMILY10H_DA TRUE - #undef OPTION_FAMILY10H_PH - #define OPTION_FAMILY10H_PH TRUE - #undef OPTION_FAMILY10H_RB - #define OPTION_FAMILY10H_RB TRUE - #undef OPTION_MEMCTLR_RB - #define OPTION_MEMCTLR_RB TRUE - #undef OPTION_MEMCTLR_DA - #define OPTION_MEMCTLR_DA TRUE - #undef OPTION_MEMCTLR_PH - #define OPTION_MEMCTLR_PH TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING - #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_PARALLEL_TRAINING - #define OPTION_PARALLEL_TRAINING TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif - #if (OPTION_FAMILY15H == TRUE) - #undef OPTION_FAMILY15H_OR - #define OPTION_FAMILY15H_OR TRUE - #undef OPTION_MEMCTLR_OR - #define OPTION_MEMCTLR_OR TRUE - #undef OPTION_HW_WRITE_LEV_TRAINING - #define OPTION_HW_WRITE_LEV_TRAINING TRUE - #undef OPTION_CONTINOUS_PATTERN_GENERATION - #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE - #undef OPTION_HW_DQS_REC_EN_TRAINING - #define OPTION_HW_DQS_REC_EN_TRAINING TRUE - #undef OPTION_OPT_SW_RD_WR_POS_TRAINING - #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE - #undef OPTION_MAX_RD_LAT_TRAINING - #define OPTION_MAX_RD_LAT_TRAINING TRUE - #undef OPTION_SW_DRAM_INIT - #define OPTION_SW_DRAM_INIT TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE TRUE - #undef OPTION_IO_CSTATE - #define OPTION_IO_CSTATE TRUE - #undef OPTION_CPB - #define OPTION_CPB TRUE - #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT - #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE - #undef OPTION_S3_MEM_SUPPORT - #define OPTION_S3_MEM_SUPPORT TRUE - #undef OPTION_ADDR_TO_CS_TRANSLATOR - #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE - #undef OPTION_CPU_CORELEVLING - #define OPTION_CPU_CORELEVLING TRUE - #undef OPTION_CPU_CFOH - #define OPTION_CPU_CFOH TRUE - #undef OPTION_MSG_BASED_C1E - #define OPTION_MSG_BASED_C1E TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS TRUE - #undef OPTION_RDIMMS - #define OPTION_RDIMMS TRUE - #undef OPTION_LRDIMMS - #define OPTION_LRDIMMS TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS TRUE - #undef OPTION_DDR3 - #define OPTION_DDR3 TRUE - #undef OPTION_ECC - #define OPTION_ECC TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE TRUE - #undef OPTION_DIMM_EXCLUDE - #define OPTION_DIMM_EXCLUDE TRUE - #endif -#endif - -#if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) - #undef GNB_SUPPORT - #define GNB_SUPPORT TRUE -#endif - -#define OPTION_ACPI_PSTATES TRUE -#define OPTION_WHEA TRUE -#define OPTION_DMI TRUE -#define OPTION_EARLY_SAMPLES FALSE -#define CFG_ACPI_PSTATES_PPC TRUE -#define CFG_ACPI_PSTATES_PCT TRUE -#define CFG_ACPI_PSTATES_PSD TRUE -#define CFG_ACPI_PSTATES_PSS TRUE -#define CFG_ACPI_PSTATES_XPSS TRUE -#define CFG_ACPI_PSTATE_PSD_INDPX FALSE -#define CFG_VRM_HIGH_SPEED_ENABLE FALSE -#define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE -#define OPTION_ALIB TRUE -/*--------------------------------------------------------------------------- - * Processing the options: Second, process the user's selections - *--------------------------------------------------------------------------*/ -#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT - #if BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE - #undef OPTION_MULTISOCKET - #define OPTION_MULTISOCKET FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_ECC_SUPPORT - #if BLDOPT_REMOVE_ECC_SUPPORT == TRUE - #undef OPTION_ECC - #define OPTION_ECC FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT - #if BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE - #undef OPTION_UDIMMS - #define OPTION_UDIMMS FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT - #if BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE - #undef OPTION_RDIMMS - #define OPTION_RDIMMS FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT - #if BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE - #undef OPTION_SODIMMS - #define OPTION_SODIMMS FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_LRDIMMS_SUPPORT - #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE - #undef OPTION_LRDIMMS - #define OPTION_LRDIMMS FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE - #if BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE - #undef OPTION_BANK_INTERLEAVE - #define OPTION_BANK_INTERLEAVE FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE - #if BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE - #undef OPTION_DCT_INTERLEAVE - #define OPTION_DCT_INTERLEAVE FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE - #if BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING - #if BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE - #undef OPTION_PARALLEL_TRAINING - #define OPTION_PARALLEL_TRAINING FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT - #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE - #undef OPTION_ONLINE_SPARE - #define OPTION_ONLINE_SPARE FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT - #if BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE - #undef OPTION_MEM_RESTORE - #define OPTION_MEM_RESTORE FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_ACPI_PSTATES - #if BLDOPT_REMOVE_ACPI_PSTATES == TRUE - #undef OPTION_ACPI_PSTATES - #define OPTION_ACPI_PSTATES FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_SRAT - #if BLDOPT_REMOVE_SRAT == TRUE - #undef OPTION_SRAT - #define OPTION_SRAT FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_SLIT - #if BLDOPT_REMOVE_SLIT == TRUE - #undef OPTION_SLIT - #define OPTION_SLIT FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_WHEA - #if BLDOPT_REMOVE_WHEA == TRUE - #undef OPTION_WHEA - #define OPTION_WHEA FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_DMI - #if BLDOPT_REMOVE_DMI == TRUE - #undef OPTION_DMI - #define OPTION_DMI FALSE - #endif -#endif -#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR - #if BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE - #undef OPTION_ADDR_TO_CS_TRANSLATOR - #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_HT_ASSIST - #if BLDOPT_REMOVE_HT_ASSIST == TRUE - #undef OPTION_HT_ASSIST - #define OPTION_HT_ASSIST FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_ATM_MODE - #if BLDOPT_REMOVE_ATM_MODE == TRUE - #undef OPTION_ATM_MODE - #define OPTION_ATM_MODE FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_MSG_BASED_C1E - #if BLDOPT_REMOVE_MSG_BASED_C1E == TRUE - #undef OPTION_MSG_BASED_C1E - #define OPTION_MSG_BASED_C1E FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_C6_STATE - #if BLDOPT_REMOVE_C6_STATE == TRUE - #undef OPTION_C6_STATE - #define OPTION_C6_STATE FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_GFX_RECOVERY - #if BLDOPT_REMOVE_GFX_RECOVERY == TRUE - #undef OPTION_GFX_RECOVERY - #define OPTION_GFX_RECOVERY FALSE - #endif -#endif - -#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC - #if BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE - #undef CFG_ACPI_PSTATES_PPC - #define CFG_ACPI_PSTATES_PPC FALSE - #endif -#endif - -#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT - #if BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE - #undef CFG_ACPI_PSTATES_PCT - #define CFG_ACPI_PSTATES_PCT FALSE - #endif -#endif - -#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD - #if BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE - #undef CFG_ACPI_PSTATES_PSD - #define CFG_ACPI_PSTATES_PSD FALSE - #endif -#endif - -#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS - #if BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE - #undef CFG_ACPI_PSTATES_PSS - #define CFG_ACPI_PSTATES_PSS FALSE - #endif -#endif - -#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS - #if BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE - #undef CFG_ACPI_PSTATES_XPSS - #define CFG_ACPI_PSTATES_XPSS FALSE - #endif -#endif - -#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT - #if BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE - #undef CFG_ACPI_PSTATE_PSD_INDPX - #define CFG_ACPI_PSTATE_PSD_INDPX TRUE - #endif -#endif - -#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE - #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE - #undef CFG_VRM_HIGH_SPEED_ENABLE - #define CFG_VRM_HIGH_SPEED_ENABLE TRUE - #endif -#endif - -#ifdef BLDCFG_VRM_NB_HIGH_SPEED_ENABLE - #if BLDCFG_VRM_NB_HIGH_SPEED_ENABLE == TRUE - #undef CFG_VRM_NB_HIGH_SPEED_ENABLE - #define CFG_VRM_NB_HIGH_SPEED_ENABLE TRUE - #endif -#endif - -#ifdef BLDCFG_STARTING_BUSNUM - #define CFG_STARTING_BUSNUM (BLDCFG_STARTING_BUSNUM) -#else - #define CFG_STARTING_BUSNUM (0) -#endif - -#ifdef BLDCFG_AMD_PLATFORM_TYPE - #define CFG_AMD_PLATFORM_TYPE BLDCFG_AMD_PLATFORM_TYPE -#else - #define CFG_AMD_PLATFORM_TYPE 0 -#endif - -CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; - -#ifdef BLDCFG_MAXIMUM_BUSNUM - #define CFG_MAXIMUM_BUSNUM (BLDCFG_MAXIMUM_BUSNUM) -#else - #define CFG_MAXIMUM_BUSNUM (0xF8) -#endif - -#ifdef BLDCFG_ALLOCATED_BUSNUM - #define CFG_ALLOCATED_BUSNUM (BLDCFG_ALLOCATED_BUSNUM) -#else - #define CFG_ALLOCATED_BUSNUM (0x20) -#endif - -#ifdef BLDCFG_BUID_SWAP_LIST - #define CFG_BUID_SWAP_LIST (BLDCFG_BUID_SWAP_LIST) -#else - #define CFG_BUID_SWAP_LIST (NULL) -#endif - -#ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST - #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST) -#else - #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (NULL) -#endif - -#ifdef BLDCFG_HTFABRIC_LIMITS_LIST - #define CFG_HTFABRIC_LIMITS_LIST (BLDCFG_HTFABRIC_LIMITS_LIST) -#else - #define CFG_HTFABRIC_LIMITS_LIST (NULL) -#endif - -#ifdef BLDCFG_HTCHAIN_LIMITS_LIST - #define CFG_HTCHAIN_LIMITS_LIST (BLDCFG_HTCHAIN_LIMITS_LIST) -#else - #define CFG_HTCHAIN_LIMITS_LIST (NULL) -#endif - -#ifdef BLDCFG_BUS_NUMBERS_LIST - #define CFG_BUS_NUMBERS_LIST (BLDCFG_BUS_NUMBERS_LIST) -#else - #define CFG_BUS_NUMBERS_LIST (NULL) -#endif - -#ifdef BLDCFG_IGNORE_LINK_LIST - #define CFG_IGNORE_LINK_LIST (BLDCFG_IGNORE_LINK_LIST) -#else - #define CFG_IGNORE_LINK_LIST (NULL) -#endif - -#ifdef BLDCFG_LINK_SKIP_REGANG_LIST - #define CFG_LINK_SKIP_REGANG_LIST (BLDCFG_LINK_SKIP_REGANG_LIST) -#else - #define CFG_LINK_SKIP_REGANG_LIST (NULL) -#endif - -#ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD - #define CFG_SET_HTCRC_SYNC_FLOOD (BLDCFG_SET_HTCRC_SYNC_FLOOD) -#else - #define CFG_SET_HTCRC_SYNC_FLOOD (FALSE) -#endif - -#ifdef BLDCFG_USE_UNIT_ID_CLUMPING - #define CFG_USE_UNIT_ID_CLUMPING (BLDCFG_USE_UNIT_ID_CLUMPING) -#else - #define CFG_USE_UNIT_ID_CLUMPING (FALSE) -#endif - -#ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST - #define CFG_ADDITIONAL_TOPOLOGIES_LIST (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST) -#else - #define CFG_ADDITIONAL_TOPOLOGIES_LIST (NULL) -#endif - -#ifdef BLDCFG_USE_HT_ASSIST - #define CFG_USE_HT_ASSIST (BLDCFG_USE_HT_ASSIST) -#else - #define CFG_USE_HT_ASSIST (TRUE) -#endif - -#ifdef BLDCFG_USE_ATM_MODE - #define CFG_USE_ATM_MODE (BLDCFG_USE_ATM_MODE) -#else - #define CFG_USE_ATM_MODE (TRUE) -#endif - -#ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE - #define CFG_PLATFORM_CONTROL_FLOW_MODE (BLDCFG_PLATFORM_CONTROL_FLOW_MODE) -#else - #define CFG_PLATFORM_CONTROL_FLOW_MODE (Nfcm) -#endif - -#ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST - #define CFG_PLATFORM_DEEMPHASIS_LIST (BLDCFG_PLATFORM_DEEMPHASIS_LIST) -#else - #define CFG_PLATFORM_DEEMPHASIS_LIST (NULL) -#endif - -#ifdef BLDCFG_VRM_ADDITIONAL_DELAY - #define CFG_VRM_ADDITIONAL_DELAY (BLDCFG_VRM_ADDITIONAL_DELAY) -#else - #define CFG_VRM_ADDITIONAL_DELAY (0) -#endif - -#ifdef BLDCFG_VRM_CURRENT_LIMIT - #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT -#else - #define CFG_VRM_CURRENT_LIMIT 0 -#endif - -#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD - #define CFG_VRM_LOW_POWER_THRESHOLD BLDCFG_VRM_LOW_POWER_THRESHOLD -#else - #define CFG_VRM_LOW_POWER_THRESHOLD 0 -#endif - -#ifdef BLDCFG_VRM_SLEW_RATE - #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE -#else - #define CFG_VRM_SLEW_RATE DFLT_VRM_SLEW_RATE -#endif - -#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT - #define CFG_VRM_INRUSH_CURRENT_LIMIT BLDCFG_VRM_INRUSH_CURRENT_LIMIT -#else - #define CFG_VRM_INRUSH_CURRENT_LIMIT 0 -#endif - -#ifdef BLDCFG_VRM_NB_ADDITIONAL_DELAY - #define CFG_VRM_NB_ADDITIONAL_DELAY (BLDCFG_VRM_NB_ADDITIONAL_DELAY) -#else - #define CFG_VRM_NB_ADDITIONAL_DELAY (0) -#endif - -#ifdef BLDCFG_VRM_NB_CURRENT_LIMIT - #define CFG_VRM_NB_CURRENT_LIMIT BLDCFG_VRM_NB_CURRENT_LIMIT -#else - #define CFG_VRM_NB_CURRENT_LIMIT (0) -#endif - -#ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD - #define CFG_VRM_NB_LOW_POWER_THRESHOLD BLDCFG_VRM_NB_LOW_POWER_THRESHOLD -#else - #define CFG_VRM_NB_LOW_POWER_THRESHOLD (0) -#endif - -#ifdef BLDCFG_VRM_NB_SLEW_RATE - #define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE -#else - #define CFG_VRM_NB_SLEW_RATE DFLT_VRM_SLEW_RATE -#endif - -#ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT - #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT -#else - #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT (0) -#endif - - -#ifdef BLDCFG_PLAT_NUM_IO_APICS - #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS -#else - #define CFG_PLAT_NUM_IO_APICS 0 -#endif - -#ifdef BLDCFG_MEM_INIT_PSTATE - #define CFG_MEM_INIT_PSTATE BLDCFG_MEM_INIT_PSTATE -#else - #define CFG_MEM_INIT_PSTATE 0 -#endif - -#ifdef BLDCFG_PLATFORM_C1E_MODE - #define CFG_C1E_MODE BLDCFG_PLATFORM_C1E_MODE -#else - #define CFG_C1E_MODE C1eModeDisabled -#endif - -#ifdef BLDCFG_PLATFORM_C1E_OPDATA - #define CFG_C1E_OPDATA BLDCFG_PLATFORM_C1E_OPDATA -#else - #define CFG_C1E_OPDATA 0 -#endif - -#ifdef BLDCFG_PLATFORM_C1E_OPDATA1 - #define CFG_C1E_OPDATA1 BLDCFG_PLATFORM_C1E_OPDATA1 -#else - #define CFG_C1E_OPDATA1 0 -#endif - -#ifdef BLDCFG_PLATFORM_C1E_OPDATA2 - #define CFG_C1E_OPDATA2 BLDCFG_PLATFORM_C1E_OPDATA2 -#else - #define CFG_C1E_OPDATA2 0 -#endif - -#ifdef BLDCFG_PLATFORM_CSTATE_MODE - #define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE -#else - #define CFG_CSTATE_MODE CStateModeDisabled -#endif - -#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA - #define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA -#else - #define CFG_CSTATE_OPDATA 0 -#endif - -#ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS - #define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS -#else - #define CFG_CSTATE_IO_BASE_ADDRESS 0 -#endif - -#ifdef BLDCFG_PLATFORM_CPB_MODE - #define CFG_CPB_MODE BLDCFG_PLATFORM_CPB_MODE -#else - #define CFG_CPB_MODE CpbModeAuto -#endif - -#ifdef BLDCFG_CORE_LEVELING_MODE - #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE -#else - #define CFG_CORE_LEVELING_MODE 0 -#endif - -#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE - #define CFG_AMD_PSTATE_CAP_VALUE BLDCFG_AMD_PSTATE_CAP_VALUE -#else - #define CFG_AMD_PSTATE_CAP_VALUE 0 -#endif - -#ifdef BLDCFG_HEAP_DRAM_ADDRESS - #define CFG_HEAP_DRAM_ADDRESS BLDCFG_HEAP_DRAM_ADDRESS -#else - #define CFG_HEAP_DRAM_ADDRESS AMD_HEAP_RAM_ADDRESS -#endif - -#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT - #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT -#else - #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY -#endif - -#ifdef BLDCFG_MEMORY_MODE_UNGANGED - #define CFG_MEMORY_MODE_UNGANGED BLDCFG_MEMORY_MODE_UNGANGED -#else - #define CFG_MEMORY_MODE_UNGANGED TRUE -#endif - -#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE - #define CFG_MEMORY_QUAD_RANK_CAPABLE BLDCFG_MEMORY_QUAD_RANK_CAPABLE -#else - #define CFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#endif - -#ifdef BLDCFG_MEMORY_QUADRANK_TYPE - #define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE -#else - #define CFG_MEMORY_QUADRANK_TYPE DFLT_MEMORY_QUADRANK_TYPE -#endif - -#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE - #define CFG_MEMORY_RDIMM_CAPABLE BLDCFG_MEMORY_RDIMM_CAPABLE -#else - #define CFG_MEMORY_RDIMM_CAPABLE TRUE -#endif - -#ifdef BLDCFG_MEMORY_LRDIMM_CAPABLE - #define CFG_MEMORY_LRDIMM_CAPABLE BLDCFG_MEMORY_LRDIMM_CAPABLE -#else - #define CFG_MEMORY_LRDIMM_CAPABLE TRUE -#endif - -#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE - #define CFG_MEMORY_UDIMM_CAPABLE BLDCFG_MEMORY_UDIMM_CAPABLE -#else - #define CFG_MEMORY_UDIMM_CAPABLE TRUE -#endif - -#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE - #define CFG_MEMORY_SODIMM_CAPABLE BLDCFG_MEMORY_SODIMM_CAPABLE -#else - #define CFG_MEMORY_SODIMM_CAPABLE FALSE -#endif - -#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING - #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING -#else - #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#endif - -#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING - #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING -#else - #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#endif - -#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING - #define CFG_MEMORY_CHANNEL_INTERLEAVING BLDCFG_MEMORY_CHANNEL_INTERLEAVING -#else - #define CFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#endif - -#ifdef BLDCFG_MEMORY_POWER_DOWN - #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN -#else - #define CFG_MEMORY_POWER_DOWN FALSE -#endif - -#ifdef BLDCFG_POWER_DOWN_MODE - #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE -#else - #define CFG_POWER_DOWN_MODE POWER_DOWN_MODE_AUTO -#endif - -#ifdef BLDCFG_ONLINE_SPARE - #define CFG_ONLINE_SPARE BLDCFG_ONLINE_SPARE -#else - #define CFG_ONLINE_SPARE FALSE -#endif - -#ifdef BLDCFG_MEMORY_PARITY_ENABLE - #define CFG_MEMORY_PARITY_ENABLE BLDCFG_MEMORY_PARITY_ENABLE -#else - #define CFG_MEMORY_PARITY_ENABLE FALSE -#endif - -#ifdef BLDCFG_BANK_SWIZZLE - #define CFG_BANK_SWIZZLE BLDCFG_BANK_SWIZZLE -#else - #define CFG_BANK_SWIZZLE TRUE -#endif - -#ifdef BLDCFG_TIMING_MODE_SELECT - #define CFG_TIMING_MODE_SELECT BLDCFG_TIMING_MODE_SELECT -#else - #define CFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#endif - -#ifdef BLDCFG_MEMORY_CLOCK_SELECT - #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT -#else - #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY -#endif - -#ifdef BLDCFG_DQS_TRAINING_CONTROL - #define CFG_DQS_TRAINING_CONTROL BLDCFG_DQS_TRAINING_CONTROL -#else - #define CFG_DQS_TRAINING_CONTROL TRUE -#endif - -#ifdef BLDCFG_IGNORE_SPD_CHECKSUM - #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM -#else - #define CFG_IGNORE_SPD_CHECKSUM FALSE -#endif - -#ifdef BLDCFG_USE_BURST_MODE - #define CFG_USE_BURST_MODE BLDCFG_USE_BURST_MODE -#else - #define CFG_USE_BURST_MODE FALSE -#endif - -#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON - #define CFG_MEMORY_ALL_CLOCKS_ON BLDCFG_MEMORY_ALL_CLOCKS_ON -#else - #define CFG_MEMORY_ALL_CLOCKS_ON FALSE -#endif - -#ifdef BLDCFG_ENABLE_ECC_FEATURE - #define CFG_ENABLE_ECC_FEATURE BLDCFG_ENABLE_ECC_FEATURE -#else - #define CFG_ENABLE_ECC_FEATURE TRUE -#endif - -#ifdef BLDCFG_ECC_REDIRECTION - #define CFG_ECC_REDIRECTION BLDCFG_ECC_REDIRECTION -#else - #define CFG_ECC_REDIRECTION FALSE -#endif - -#ifdef BLDCFG_SCRUB_DRAM_RATE - #define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE -#else - #define CFG_SCRUB_DRAM_RATE DFLT_SCRUB_DRAM_RATE -#endif - -#ifdef BLDCFG_SCRUB_L2_RATE - #define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE -#else - #define CFG_SCRUB_L2_RATE DFLT_SCRUB_L2_RATE -#endif - -#ifdef BLDCFG_SCRUB_L3_RATE - #define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE -#else - #define CFG_SCRUB_L3_RATE DFLT_SCRUB_L3_RATE -#endif - -#ifdef BLDCFG_SCRUB_IC_RATE - #define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE -#else - #define CFG_SCRUB_IC_RATE DFLT_SCRUB_IC_RATE -#endif - -#ifdef BLDCFG_SCRUB_DC_RATE - #define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE -#else - #define CFG_SCRUB_DC_RATE DFLT_SCRUB_DC_RATE -#endif - -#ifdef BLDCFG_ECC_SYNC_FLOOD - #define CFG_ECC_SYNC_FLOOD BLDCFG_ECC_SYNC_FLOOD -#else - #define CFG_ECC_SYNC_FLOOD 0 -#endif - -#ifdef BLDCFG_ECC_SYMBOL_SIZE - #define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE -#else - #define CFG_ECC_SYMBOL_SIZE 0 -#endif - -#ifdef BLDCFG_1GB_ALIGN - #define CFG_1GB_ALIGN BLDCFG_1GB_ALIGN -#else - #define CFG_1GB_ALIGN FALSE -#endif - -#ifdef BLDCFG_UMA_ALLOCATION_MODE - #define CFG_UMA_MODE BLDCFG_UMA_ALLOCATION_MODE -#else - #define CFG_UMA_MODE UMA_AUTO -#endif - -#ifdef BLDCFG_UMA_ALLOCATION_SIZE - #define CFG_UMA_SIZE BLDCFG_UMA_ALLOCATION_SIZE -#else - #define CFG_UMA_SIZE 0 -#endif - -#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT - #define CFG_UMA_ABOVE4G BLDCFG_UMA_ABOVE4G_SUPPORT -#else - #define CFG_UMA_ABOVE4G FALSE -#endif - -#ifdef BLDCFG_UMA_ALIGNMENT - #define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT -#else - #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED -#endif - -#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB - #define CFG_PROCESSOR_SCOPE_IN_SB BLDCFG_PROCESSOR_SCOPE_IN_SB -#else - #define CFG_PROCESSOR_SCOPE_IN_SB FALSE -#endif - -#ifdef BLDCFG_S3_LATE_RESTORE - #define CFG_S3_LATE_RESTORE BLDCFG_S3_LATE_RESTORE -#else - #define CFG_S3_LATE_RESTORE TRUE -#endif - -#ifdef BLDCFG_USE_32_BYTE_REFRESH - #define CFG_USE_32_BYTE_REFRESH (BLDCFG_USE_32_BYTE_REFRESH) -#else - #define CFG_USE_32_BYTE_REFRESH (FALSE) -#endif - -#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY - #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY) -#else - #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (FALSE) -#endif - -#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0 - #define CFG_PROCESSOR_SCOPE_NAME0 BLDCFG_PROCESSOR_SCOPE_NAME0 -#else - #define CFG_PROCESSOR_SCOPE_NAME0 SCOPE_NAME_VALUE -#endif - -#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1 - #define CFG_PROCESSOR_SCOPE_NAME1 BLDCFG_PROCESSOR_SCOPE_NAME1 -#else - #define CFG_PROCESSOR_SCOPE_NAME1 SCOPE_NAME_VALUE1 -#endif - -#ifdef BLDCFG_CFG_GNB_HD_AUDIO - #define CFG_GNB_HD_AUDIO BLDCFG_CFG_GNB_HD_AUDIO -#else - #define CFG_GNB_HD_AUDIO TRUE -#endif - -#ifdef BLDCFG_CFG_ABM_SUPPORT - #define CFG_ABM_SUPPORT BLDCFG_CFG_ABM_SUPPORT -#else - #define CFG_ABM_SUPPORT FALSE -#endif - -#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE - #define CFG_DINAMIC_REFRESH_RATE BLDCFG_CFG_DYNAMIC_REFRESH_RATE -#else - #define CFG_DYNAMIC_REFRESH_RATE 0 -#endif - -#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL - #define CFG_LCD_BACK_LIGHT_CONTROL BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL -#else - #define CFG_LCD_BACK_LIGHT_CONTROL 0 -#endif - -#ifdef BLDCFG_STEREO_3D_PINOUT - #define CFG_GNB_STEREO_3D_PINOUT BLDCFG_STEREO_3D_PINOUT -#else - #define CFG_GNB_STEREO_3D_PINOUT 0 -#endif - -#ifdef BLDCFG_IGPU_SUBSYSTEM_ID - #define CFG_GNB_IGPU_SSID BLDCFG_IGPU_SUBSYSTEM_ID -#else - #define CFG_GNB_IGPU_SSID 0 -#endif - -#ifdef BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID - #define CFG_GNB_HDAUDIO_SSID BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID -#else - #define CFG_GNB_HDAUDIO_SSID 0 -#endif - -#ifdef BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID - #define CFG_GNB_PCIE_SSID BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID -#else - #define CFG_GNB_PCIE_SSID 0x12341022 -#endif - -#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM - #define CFG_GFX_LVDS_SPREAD_SPECTRUM BLDCFG_GFX_LVDS_SPREAD_SPECTRUM -#else - #define CFG_GFX_LVDS_SPREAD_SPECTRUM 0 -#endif - -#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE - #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE -#else - #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE 0 -#endif - -#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS - #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS -#else - #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 -#endif - -#ifdef BLDOPT_REMOVE_EARLY_SAMPLES - #if BLDOPT_REMOVE_EARLY_SAMPLES == TRUE - #undef OPTION_EARLY_SAMPLES - #define OPTION_EARLY_SAMPLES FALSE - #else - #undef OPTION_EARLY_SAMPLES - #define OPTION_EARLY_SAMPLES TRUE - #endif -#endif - -#ifdef BLDOPT_REMOVE_ALIB - #if BLDOPT_REMOVE_ALIB == TRUE - #undef OPTION_ALIB - #define OPTION_ALIB FALSE - #else - #undef OPTION_ALIB - #define OPTION_ALIB TRUE - #endif -#endif - -/*--------------------------------------------------------------------------- - * Processing the options: Third, perform the option cross checks - *--------------------------------------------------------------------------*/ -// Assure that at least one type of memory support is included -#if OPTION_UDIMMS == FALSE - #if OPTION_RDIMMS == FALSE - #if OPTION_SODIMMS == FALSE - #if OPTION_LRDIMMS == FALSE - #error BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT or BLDOPT_REMOVE_LRDIMMS_SUPPORT must be FALSE. - #endif - #endif - #endif -#endif -// Ensure at least one dimm type is capable -#if CFG_MEMORY_RDIMM_CAPABLE == FALSE - #if CFG_MEMORY_UDIMM_CAPABLE == FALSE - #if CFG_MEMORY_SODIMM_CAPABLE == FALSE - #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE - #error BLDCFG: No dimm type is capable - #endif - #endif - #endif -#endif -// Check LRDIMM CODE and LRDIMM CFG item -#if CFG_MEMORY_LRDIMM_CAPABLE == FALSE - #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE - #error Warning: LRDIMM capability is false, but LRIDMM support code included - #endif -#endif -// Turn off multi-socket based features if only one node... -#if OPTION_MULTISOCKET == FALSE - #undef OPTION_PARALLEL_TRAINING - #define OPTION_PARALLEL_TRAINING FALSE - #undef OPTION_NODE_INTERLEAVE - #define OPTION_NODE_INTERLEAVE FALSE -#endif -// Ensure that at least one write leveling option is selected -#if OPTION_DDR3 == TRUE - #if OPTION_HW_WRITE_LEV_TRAINING == FALSE - #if OPTION_SW_WRITE_LEV_TRAINING == FALSE - #error No Write leveling option selected for DDR3 - #endif - #endif - #if OPTION_SW_DRAM_INIT == FALSE - #error Software dram init must be enabled for DDR3 dimms - #endif -#endif -// Ensure at least one DQS receiver training option is selected -#if OPTION_HW_DQS_REC_EN_TRAINING == FALSE - #if OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == FALSE - #if OPTION_OPT_SW_DQS_REC_EN_TRAINING == FALSE - #error No DQS receiver training option has been slected - #endif - #endif -#endif -// Ensure at least one Rd Wr position training option has been selected -#if OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == FALSE - #if OPTION_OPT_SW_RD_WR_POS_TRAINING == FALSE - #error No Rd Wr position training option has been selected - #endif -#endif -// Ensure at least one dram init option has been selected -#if OPTION_HW_DRAM_INIT == FALSE - #if OPTION_SW_DRAM_INIT == FALSE - #error No Dram init option has been selected - #endif -#endif -// Ensure the frequency limit is valid -#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 933) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266) - #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200) - #error BLDCFG: Unsupported memory bus frequency - #endif - #endif - #endif - #endif - #endif - #endif - #endif -#endif -// Ensure timing mode is valid -#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC - #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED - #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO - #error BLDCFG: Invalid timing mode is set - #endif - #endif -#endif -// Ensure the scrub rate is valid -#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF)) - #error BLDCFG: Unsupported dram scrub rate set -#endif -#if CFG_SCRUB_L2_RATE > 0x16 - #error BLDCFG: Unsupported L2 scrubber rate set -#endif -#if CFG_SCRUB_L3_RATE > 0x16 - #error BLDCFG: unsupported L3 scrubber rate set -#endif -#if CFG_SCRUB_IC_RATE > 0x16 - #error BLDCFG: Unsupported Instruction cache scrub rate set -#endif -#if CFG_SCRUB_DC_RATE > 0x16 - #error BLDCFG: Unsupported Dcache scrub rate set -#endif -// Ensure Quad rank dimm type is valid -#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED - #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED - #error BLDCFG: Invalid quad rank dimm type set - #endif -#endif -// Ensure ECC symbol size is valid -#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG - #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4 - #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8 - #error BLDCFG: Invalid Ecc symbol size set - #endif - #endif -#endif -// Ensure power down mode is valid -#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT - #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL - #error BLDCFG: Invalid power down mode set - #endif -#endif - -/***************************************************************************** - * - * Process the option logic, setting local control variables - * - ****************************************************************************/ -#if OPTION_ACPI_PSTATES == TRUE - #define OPTFCN_ACPI_TABLES CreateAcpiTablesMain - #define OPTFCN_GATHER_DATA PStateGatherData - #if OPTION_MULTISOCKET == TRUE - #define OPTFCN_PSTATE_LEVELING PStateLeveling - #else - #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess - #endif -#else - #define OPTFCN_ACPI_TABLES CommonReturnAgesaSuccess - #define OPTFCN_GATHER_DATA CommonReturnAgesaSuccess - #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess -#endif - - -/***************************************************************************** - * - * Include the structure definitions for the defaults table structures - * - ****************************************************************************/ -#include "Options.h" -#include "OptionCpuFamiliesInstall.h" -#include "OptionsHt.h" -#include "OptionHtInstall.h" -#include "OptionMemory.h" -#include "PlatformMemoryConfiguration.h" -#include "OptionMemoryInstall.h" -#include "OptionMemoryRecovery.h" -#include "OptionMemoryRecoveryInstall.h" -#include "OptionCpuFeaturesInstall.h" -#include "OptionDmi.h" -#include "OptionDmiInstall.h" -#include "OptionPstate.h" -#include "OptionPstateInstall.h" -#include "OptionWhea.h" -#include "OptionWheaInstall.h" -#include "OptionSrat.h" -#include "OptionSratInstall.h" -#include "OptionSlit.h" -#include "OptionSlitInstall.h" -#include "OptionMultiSocket.h" -#include "OptionMultiSocketInstall.h" -#include "OptionIdsInstall.h" -#include "OptionGfxRecovery.h" -#include "OptionGfxRecoveryInstall.h" -#include "OptionGnb.h" -#include "OptionGnbInstall.h" -#include "OptionS3ScriptInstall.h" - - -/***************************************************************************** - * - * Generate the output structures (defaults tables) - * - ****************************************************************************/ -BUILD_OPT_CFG UserOptions = { - { // AGESA version string - AGESA_CODE_SIGNATURE, // code header Signature - AGESA_PACKAGE_STRING, // 8 character ID - AGESA_VERSION_STRING, // 12 character version string - 0 // null string terminator - }, - //Build Option Area - OPTION_UDIMMS, //UDIMMS - OPTION_RDIMMS, //RDIMMS - OPTION_LRDIMMS, //LRDIMMS - OPTION_ECC, //ECC - OPTION_BANK_INTERLEAVE, //BANK_INTERLEAVE - OPTION_DCT_INTERLEAVE, //DCT_INTERLEAVE - OPTION_NODE_INTERLEAVE, //NODE_INTERLEAVE - OPTION_PARALLEL_TRAINING, //PARALLEL_TRAINING - OPTION_ONLINE_SPARE, //ONLINE_SPARE - OPTION_MEM_RESTORE, //MEM CONTEXT RESTORE - OPTION_MULTISOCKET, //MULTISOCKET - OPTION_ACPI_PSTATES, //ACPI_PSTATES - OPTION_SRAT, //SRAT - OPTION_SLIT, //SLIT - OPTION_WHEA, //WHEA - OPTION_DMI, //DMI - OPTION_EARLY_SAMPLES, //EARLY_SAMPLES - OPTION_ADDR_TO_CS_TRANSLATOR, //ADDR_TO_CS_TRANSLATOR - - //Build Configuration Area - CFG_PCI_MMIO_BASE, - CFG_PCI_MMIO_SIZE, - { - // CoreVrm - { - CFG_VRM_CURRENT_LIMIT, // VrmCurrentLimit - CFG_VRM_LOW_POWER_THRESHOLD, // VrmLowPowerThershold - CFG_VRM_SLEW_RATE, // VrmSlewRate - CFG_VRM_ADDITIONAL_DELAY, // VrmAdditionalDelay - CFG_VRM_HIGH_SPEED_ENABLE, // VrmHiSpeedEnable - CFG_VRM_INRUSH_CURRENT_LIMIT // VrmInrushCurrentLimit - }, - // NbVrm - { - CFG_VRM_NB_CURRENT_LIMIT, // VrmNbCurrentLimit - CFG_VRM_NB_LOW_POWER_THRESHOLD, // VrmNbLowPowerThershold - CFG_VRM_NB_SLEW_RATE, // VrmNbSlewRate - CFG_VRM_NB_ADDITIONAL_DELAY, // VrmNbAdditionalDelay - CFG_VRM_NB_HIGH_SPEED_ENABLE, // VrmNbHiSpeedEnable - CFG_VRM_NB_INRUSH_CURRENT_LIMIT // VrmNbInrushCurrentLimit - } - }, - CFG_PLAT_NUM_IO_APICS, //PlatformApicIoNumber - CFG_MEM_INIT_PSTATE, //MemoryInitPstate - CFG_C1E_MODE, //C1eMode - CFG_C1E_OPDATA, //C1ePlatformData - CFG_C1E_OPDATA1, //C1ePlatformData1 - CFG_C1E_OPDATA2, //C1ePlatformData2 - CFG_CSTATE_MODE, //CStateMode - CFG_CSTATE_OPDATA, //CStatePlatformData - CFG_CSTATE_IO_BASE_ADDRESS, //CStateIoBaseAddress - CFG_CPB_MODE, //CpbMode - CFG_CORE_LEVELING_MODE, //CoreLevelingCofig - { - CFG_PLATFORM_CONTROL_FLOW_MODE, // The platform's control flow mode. - CFG_USE_HT_ASSIST, // CfgUseHtAssist - CFG_USE_ATM_MODE, // CfgUseAtmMode - CFG_USE_32_BYTE_REFRESH, // Display Refresh uses 32 byte packets. - CFG_USE_VARIABLE_MCT_ISOC_PRIORITY, // The Memory controller will be set to Variable Isoc Priority. - CFG_PLATFORM_POWER_POLICY_MODE // The platform's power policy mode. - }, - (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST, // Deemphasis settings - CFG_AMD_PLATFORM_TYPE, //AmdPlatformType - CFG_AMD_PSTATE_CAP_VALUE, // Amd pstate ceiling enabling deck - - CFG_MEMORY_BUS_FREQUENCY_LIMIT, // CfgMemoryBusFrequencyLimit - CFG_MEMORY_MODE_UNGANGED, // CfgMemoryModeUnganged - CFG_MEMORY_QUAD_RANK_CAPABLE, // CfgMemoryQuadRankCapable - CFG_MEMORY_QUADRANK_TYPE, // CfgMemoryQuadrankType - CFG_MEMORY_RDIMM_CAPABLE, // CfgMemoryRDimmCapable - CFG_MEMORY_LRDIMM_CAPABLE, // CfgMemoryLRDimmCapable - CFG_MEMORY_UDIMM_CAPABLE, // CfgMemoryUDimmCapable - CFG_MEMORY_SODIMM_CAPABLE, // CfgMemorySodimmCapable - CFG_MEMORY_ENABLE_BANK_INTERLEAVING, // CfgMemoryEnableBankInterleaving - CFG_MEMORY_ENABLE_NODE_INTERLEAVING, // CfgMemoryEnableNodeInterleaving - CFG_MEMORY_CHANNEL_INTERLEAVING, // CfgMemoryChannelInterleaving - CFG_MEMORY_POWER_DOWN, // CfgMemoryPowerDown - CFG_POWER_DOWN_MODE, // CfgPowerDownMode - CFG_ONLINE_SPARE, // CfgOnlineSpare - CFG_MEMORY_PARITY_ENABLE, // CfgMemoryParityEnable - CFG_BANK_SWIZZLE, // CfgBankSwizzle - CFG_TIMING_MODE_SELECT, // CfgTimingModeSelect - CFG_MEMORY_CLOCK_SELECT, // CfgMemoryClockSelect - CFG_DQS_TRAINING_CONTROL, // CfgDqsTrainingControl - CFG_IGNORE_SPD_CHECKSUM, // CfgIgnoreSpdChecksum - CFG_USE_BURST_MODE, // CfgUseBurstMode - CFG_MEMORY_ALL_CLOCKS_ON, // CfgMemoryAllClocksOn - CFG_ENABLE_ECC_FEATURE, // CfgEnableEccFeature - CFG_ECC_REDIRECTION, // CfgEccRedirection - CFG_SCRUB_DRAM_RATE, // CfgScrubDramRate - CFG_SCRUB_L2_RATE, // CfgScrubL2Rate - CFG_SCRUB_L3_RATE, // CfgScrubL3Rate - CFG_SCRUB_IC_RATE, // CfgScrubIcRate - CFG_SCRUB_DC_RATE, // CfgScrubDcRate - CFG_ECC_SYNC_FLOOD, // CfgEccSyncFlood - CFG_ECC_SYMBOL_SIZE, // CfgEccSymbolSize - CFG_HEAP_DRAM_ADDRESS, // CfgHeapDramAddress - CFG_1GB_ALIGN, // CfgNodeMem1GBAlign - CFG_S3_LATE_RESTORE, // CfgS3LateRestore - CFG_ACPI_PSTATE_PSD_INDPX, // CfgAcpiPstateIndependent - (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList - CFG_UMA_MODE, // CfgUmaMode - CFG_UMA_SIZE, // CfgUmaSize - CFG_UMA_ABOVE4G, // CfgUmaAbove4G - CFG_UMA_ALIGNMENT, // CfgUmaAlignment - CFG_PROCESSOR_SCOPE_IN_SB, // CfgProcessorScopeInSb - CFG_PROCESSOR_SCOPE_NAME0, // CfgProcessorScopeName0 - CFG_PROCESSOR_SCOPE_NAME1, // CfgProcessorScopeName1 - CFG_GNB_HD_AUDIO, // CfgGnbHdAudio - CFG_ABM_SUPPORT, // CfgAbmSupport - CFG_DYNAMIC_REFRESH_RATE, // CfgDynamicRefreshRate - CFG_LCD_BACK_LIGHT_CONTROL, // CfgLcdBackLightControl - CFG_GNB_STEREO_3D_PINOUT, // CfgGnb3dStereoPinIndex - CFG_TEMP_PCIE_MMIO_BASE_ADDRESS, // CfgTempPcieMmioBaseAddress - CFG_GNB_IGPU_SSID, // CfgGnbIGPUSSID - CFG_GNB_HDAUDIO_SSID, // CfgGnbHDAudioSSID - CFG_GNB_PCIE_SSID, // CfgGnbPcieSSID - CFG_GFX_LVDS_SPREAD_SPECTRUM, // CfgLvdsSpreadSpectrum - CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE, // CfgLvdsSpreadSpectrumRate - - 0, //reserved... -}; - -CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] = -{ - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, - sizeof (AMD_RESET_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResetConstructor, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_RESET_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, - sizeof (AMD_RECOVERY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, - sizeof (AMD_EARLY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEarlyInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_EARLY_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, - sizeof (AMD_ENV_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEnvInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_ENV_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, - sizeof (AMD_LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdInitLateInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor, - AMD_INIT_LATE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, - sizeof (AMD_MID_PARAMS), - (PF_AGESA_FUNCTION) AmdInitMidInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_MID_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, - sizeof (AMD_POST_PARAMS), - (PF_AGESA_FUNCTION) AmdInitPostInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, - sizeof (AMD_RESUME_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResumeInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor, - AMD_INIT_RESUME_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, - sizeof (AMD_S3LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_S3_LATE_RESTORE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, - sizeof (AMD_S3SAVE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3SaveInitializer, - (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor, - AMD_S3_SAVE_HANDLE - }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, - sizeof (AP_EXE_PARAMS), - (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_LATE_RUN_AP_TASK_HANDLE - }, - #endif - { 0, NULL } -}; - -CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0]))); - -CONST DISPATCH_TABLE ROMDATA DispatchTable[] = -{ - { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct }, - { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct }, - - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore }, - #endif - - #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE - { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId }, - { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress }, - { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore }, - { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog }, - { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm }, - { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask }, - #endif - { 0, NULL } -}; - -CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] = -{ - IDS_LATE_RUN_AP_TASK - // Get DMI info - CPU_DMI_AP_GET_TYPE4_TYPE7 - // Probe filter enable - HT_ASSIST_AP_DISABLE_CACHE - HT_ASSIST_AP_ENABLE_CACHE - - { 0, NULL } -}; - -#if AGESA_ENTRY_INIT_RESET == TRUE - #if IDSOPT_IDS_ENABLED == TRUE - #if IDSOPT_TRACING_ENABLED == TRUE - #define MAKE_DBG_STR(x, y) MAKE_AS_A_STRING(x : y) - CONST CHAR8 *BldOptDebugOutput[] = { - #if IDS_TRACE_SHOW_BLD_OPT_CFG == TRUE - //Build Option Area - MAKE_DBG_STR (\nOptUDIMM, OPTION_UDIMMS) - MAKE_DBG_STR (\nOptRDIMM, OPTION_RDIMMS) - MAKE_DBG_STR (\nOptLRDIMM, OPTION_LRDIMMS) - MAKE_DBG_STR (\nOptECC, OPTION_ECC) - MAKE_DBG_STR (\nOptCsIntlv, OPTION_BANK_INTERLEAVE) - MAKE_DBG_STR (\nOptDctIntlv, OPTION_DCT_INTERLEAVE) - MAKE_DBG_STR (\nOptNodeIntlv, OPTION_NODE_INTERLEAVE) - //MAKE_DBG_STR (\nOptParallelTraining, OPTION_PARALLEL_TRAINING) - MAKE_DBG_STR (\nOptOnlineSpare, OPTION_ONLINE_SPARE) - MAKE_DBG_STR (\nOptAddr2CsTranslator, OPTION_ADDR_TO_CS_TRANSLATOR) - MAKE_DBG_STR (\nOptMemRestore, OPTION_MEM_RESTORE) - MAKE_DBG_STR (\nOptMultiSocket, OPTION_MULTISOCKET) - MAKE_DBG_STR (\nOptPstates, OPTION_ACPI_PSTATES) - MAKE_DBG_STR (\nOptSRAT, OPTION_SRAT) - MAKE_DBG_STR (\nOptSLIT, OPTION_SLIT) - MAKE_DBG_STR (\nOptWHEA, OPTION_WHEA) - MAKE_DBG_STR (\nOptDMI, OPTION_DMI) - MAKE_DBG_STR (\nOptEarlySamples, OPTION_EARLY_SAMPLES), - - //Build Configuration Area - // CoreVrm - MAKE_DBG_STR (\nVrmCurrentLimit , CFG_VRM_CURRENT_LIMIT) - MAKE_DBG_STR (\nVrmLowPowerThreshold , CFG_VRM_LOW_POWER_THRESHOLD) - MAKE_DBG_STR (\nVrmSlewRate , CFG_VRM_SLEW_RATE) - MAKE_DBG_STR (\nVrmAdditionalDelay , CFG_VRM_ADDITIONAL_DELAY) - MAKE_DBG_STR (\nVrmHiSpeedEnable , CFG_VRM_HIGH_SPEED_ENABLE) - MAKE_DBG_STR (\nVrmInrushCurrentLimit, CFG_VRM_INRUSH_CURRENT_LIMIT) - // NbVrm - MAKE_DBG_STR (\nNbVrmCurrentLimit , CFG_VRM_NB_CURRENT_LIMIT) - MAKE_DBG_STR (\nNbVrmLowPowerThreshold , CFG_VRM_NB_LOW_POWER_THRESHOLD) - MAKE_DBG_STR (\nNbVrmSlewRate , CFG_VRM_NB_SLEW_RATE) - MAKE_DBG_STR (\nNbVrmAdditionalDelay , CFG_VRM_NB_ADDITIONAL_DELAY) - MAKE_DBG_STR (\nNbVrmHiSpeedEnable , CFG_VRM_NB_HIGH_SPEED_ENABLE) - MAKE_DBG_STR (\nNbVrmInrushCurrentLimit, CFG_VRM_NB_INRUSH_CURRENT_LIMIT), - - MAKE_DBG_STR (\nNumIoApics , CFG_PLAT_NUM_IO_APICS) - MAKE_DBG_STR (\nMemInitPstate , CFG_MEM_INIT_PSTATE) - MAKE_DBG_STR (\nC1eMode , CFG_C1E_MODE) - MAKE_DBG_STR (\nC1eOpData , CFG_C1E_OPDATA) - MAKE_DBG_STR (\nC1eOpdata1 , CFG_C1E_OPDATA1) - MAKE_DBG_STR (\nC1eOpdata2 , CFG_C1E_OPDATA2) - MAKE_DBG_STR (\nCStateMode , CFG_CSTATE_MODE) - MAKE_DBG_STR (\nCStateOpData , CFG_CSTATE_OPDATA) - MAKE_DBG_STR (\nCStateIoBaseAddr , CFG_CSTATE_IO_BASE_ADDRESS) - MAKE_DBG_STR (\nCpbMode , CFG_CPB_MODE) - MAKE_DBG_STR (\nCoreLevelingMode , CFG_CORE_LEVELING_MODE), - - MAKE_DBG_STR (\nControlFlowMode , CFG_PLATFORM_CONTROL_FLOW_MODE) - MAKE_DBG_STR (\nUseHtAssist , CFG_USE_HT_ASSIST) - MAKE_DBG_STR (\nUseAtmMode , CFG_USE_ATM_MODE) - MAKE_DBG_STR (\nUse32ByteRefresh , CFG_USE_32_BYTE_REFRESH) - MAKE_DBG_STR (\nUseVarMctIsocPriority , CFG_USE_VARIABLE_MCT_ISOC_PRIORITY) - MAKE_DBG_STR (\nPowerPolicy , CFG_PLATFORM_POWER_POLICY_MOD) - - MAKE_DBG_STR (\nDeemphasisList , CFG_PLATFORM_DEEMPHASIS_LIST) - - MAKE_DBG_STR (\nPciMmioAddr , CFG_PCI_MMIO_BASE) - MAKE_DBG_STR (\nPciMmioSize , CFG_PCI_MMIO_SIZE) - MAKE_DBG_STR (\nPlatformType , CFG_AMD_PLATFORM_TYPE) - MAKE_DBG_STR (\nPstateCapValue , CFG_AMD_PSTATE_CAP_VALUE), - - MAKE_DBG_STR (\nMemBusFreqLimit , CFG_MEMORY_BUS_FREQUENCY_LIMIT) - MAKE_DBG_STR (\nTimingModeSelect , CFG_TIMING_MODE_SELECT) - MAKE_DBG_STR (\nMemoryClockSelect , CFG_MEMORY_CLOCK_SELECT) - - MAKE_DBG_STR (\nMemUnganged , CFG_MEMORY_MODE_UNGANGED) - MAKE_DBG_STR (\nQRCap , CFG_MEMORY_QUAD_RANK_CAPABLE) - MAKE_DBG_STR (\nQRType , CFG_MEMORY_QUADRANK_TYPE) - MAKE_DBG_STR (\nRDimmCap , CFG_MEMORY_RDIMM_CAPABLE) - MAKE_DBG_STR (\nLRDimmCap , CFG_MEMORY_LRDIMM_CAPABLE) - MAKE_DBG_STR (\nUDimmCap , CFG_MEMORY_UDIMM_CAPABLE) - MAKE_DBG_STR (\nSODimmCap , CFG_MEMORY_SODIMM_CAPABLE) - MAKE_DBG_STR (\nDqsTrainingControl , CFG_DQS_TRAINING_CONTROL) - MAKE_DBG_STR (\nIgnoreSpdChecksum , CFG_IGNORE_SPD_CHECKSUM) - MAKE_DBG_STR (\nUseBurstMode , CFG_USE_BURST_MODE) - MAKE_DBG_STR (\nAllMemClkOn , CFG_MEMORY_ALL_CLOCKS_ON), - - MAKE_DBG_STR (\nPowerDownEn , CFG_MEMORY_POWER_DOWN) - MAKE_DBG_STR (\nPowerDownMode , CFG_POWER_DOWN_MODE) - MAKE_DBG_STR (\nOnlineSpare , CFG_ONLINE_SPARE) - MAKE_DBG_STR (\nAddrParityEn , CFG_MEMORY_PARITY_ENABLE) - MAKE_DBG_STR (\nBankSwizzle , CFG_BANK_SWIZZLE) - MAKE_DBG_STR (\nCsIntlvEn , CFG_MEMORY_ENABLE_BANK_INTERLEAVING) - MAKE_DBG_STR (\nNodeIntlvEn , CFG_MEMORY_ENABLE_NODE_INTERLEAVING) - MAKE_DBG_STR (\nDctIntlvEn , CFG_MEMORY_CHANNEL_INTERLEAVING), - - MAKE_DBG_STR (\nUmaMode , CFG_UMA_MODE) - MAKE_DBG_STR (\nUmaSize , CFG_UMA_SIZE) - MAKE_DBG_STR (\nUmaAbove4G , CFG_UMA_ABOVE4G) - MAKE_DBG_STR (\nUmaAlignment , CFG_UMA_ALIGNMENT) - - MAKE_DBG_STR (\nEccEn , CFG_ENABLE_ECC_FEATURE) - MAKE_DBG_STR (\nEccRedirect , CFG_ECC_REDIRECTION) - MAKE_DBG_STR (\nScrubDramRate , CFG_SCRUB_DRAM_RATE) - MAKE_DBG_STR (\nScrubL2Rate , CFG_SCRUB_L2_RATE) - MAKE_DBG_STR (\nScrubL3Rate , CFG_SCRUB_L3_RATE) - MAKE_DBG_STR (\nScrubIcRate , CFG_SCRUB_IC_RATE) - MAKE_DBG_STR (\nScrubDcRate , CFG_SCRUB_DC_RATE) - MAKE_DBG_STR (\nEccSyncFlood , CFG_ECC_SYNC_FLOOD) - MAKE_DBG_STR (\nEccSymbolSize , CFG_ECC_SYMBOL_SIZE) - MAKE_DBG_STR (\nHeapDramAddress , CFG_HEAP_DRAM_ADDRESS) - MAKE_DBG_STR (\nNodeMem1GBAlign , CFG_1GB_ALIGN), - - MAKE_DBG_STR (\nS3LateRestore , CFG_S3_LATE_RESTORE) - MAKE_DBG_STR (\nAcpiPstateIndependent , CFG_ACPI_PSTATE_PSD_INDPX) - - MAKE_DBG_STR (\nApMtrrSettingsList , CFG_AP_MTRR_SETTINGS_LIST) - - MAKE_DBG_STR (\nProcessorScopeInSb , CFG_PROCESSOR_SCOPE_IN_SB) - MAKE_DBG_STR (\nProcessorScopeName0 , CFG_PROCESSOR_SCOPE_NAME0) - MAKE_DBG_STR (\nProcessorScopeName1 , CFG_PROCESSOR_SCOPE_NAME1) - MAKE_DBG_STR (\nGnbHdAudio , CFG_GNB_HD_AUDIO) - MAKE_DBG_STR (\nAbmSupport , CFG_ABM_SUPPORT) - MAKE_DBG_STR (\nDynamicRefreshRate , CFG_DYNAMIC_REFRESH_RATE) - MAKE_DBG_STR (\nLcdBackLightControl , CFG_LCD_BACK_LIGHT_CONTROL) - MAKE_DBG_STR (\nGnb3dStereoPinIndex , CFG_GNB_STEREO_3D_PINOUT) - MAKE_DBG_STR (\nTempPcieMmioBaseAddress, CFG_TEMP_PCIE_MMIO_BASE_ADDRESS), - MAKE_DBG_STR (\nCfgGnbIGPUSSID , CFG_GNB_IGPU_SSID), - MAKE_DBG_STR (\nCfgGnbHDAudioSSID , CFG_GNB_HDAUDIO_SSID), - MAKE_DBG_STR (\nCfgGnbPcieSSID , CFG_GNB_PCIE_SSID), - - MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum , CFG_GFX_LVDS_SPREAD_SPECTRUM), - MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE), - #endif - NULL - }; - #endif - #endif -#endif diff --git a/src/vendorcode/amd/agesa/Include/PlatformMemoryConfiguration.h b/src/vendorcode/amd/agesa/Include/PlatformMemoryConfiguration.h deleted file mode 100644 index 85c14d9644..0000000000 --- a/src/vendorcode/amd/agesa/Include/PlatformMemoryConfiguration.h +++ /dev/null @@ -1,314 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * AMD Platform Specific Memory Configuration - * - * Contains Definitions and Macros for control of AGESA Memory code on a per platform basis - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: OPTION - * @e \$Revision: 35415 $ @e \$Date: 2010-07-22 06:10:32 +0800 (Thu, 22 Jul 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _PLATFORM_MEMORY_CONFIGURATION_H_ -#define _PLATFORM_MEMORY_CONFIGURATION_H_ - -/*---------------------------------------------------------------------------------------- - * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) - *---------------------------------------------------------------------------------------- - */ -#ifndef PSO_ENTRY - #define PSO_ENTRY UINT8 -#endif - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S, S T R U C T U R E S, E N U M S - *---------------------------------------------------------------------------------------- - */ -/*---------------------------------------------------------------------------------------- - * PLATFORM SPECIFIC MEMORY DEFINITIONS - *---------------------------------------------------------------------------------------- - */ -/// -/// Memory Speed and DIMM Population Masks -/// -///< DDR Speed Masks -///< Specifies the DDR Speed on a memory channel -/// -#define ANY_SPEED 0xFFFFFFFF -#define DDR400 ((UINT32) 1 << (DDR400_FREQUENCY / 66)) -#define DDR533 ((UINT32) 1 << (DDR533_FREQUENCY / 66)) -#define DDR667 ((UINT32) 1 << (DDR667_FREQUENCY / 66)) -#define DDR800 ((UINT32) 1 << (DDR800_FREQUENCY / 66)) -#define DDR1066 ((UINT32) 1 << (DDR1066_FREQUENCY / 66)) -#define DDR1333 ((UINT32) 1 << (DDR1333_FREQUENCY / 66)) -#define DDR1600 ((UINT32) 1 << (DDR1600_FREQUENCY / 66)) -#define DDR1866 ((UINT32) 1 << (DDR1866_FREQUENCY / 66)) -/// -///< DIMM POPULATION MASKS -///< Specifies the DIMM Population on a channel (can be added together to specify configuration). -///< ex. SR_DIMM0 + SR_DIMM1 : Single Rank Dimm in slot 0 AND Slot 1 -///< SR_DIMM0 + DR_DIMM0 + SR_DIMM1 +DR_DIMM1 : Single OR Dual rank in Slot 0 AND Single OR Dual rank in Slot 1 -/// -#define ANY_ 0xFF ///< Any dimm configuration the current channel -#define SR_DIMM0 0x0001 ///< Single rank dimm in slot 0 on the current channel -#define SR_DIMM1 0x0010 ///< Single rank dimm in slot 1 on the current channel -#define SR_DIMM2 0x0100 ///< Single rank dimm in slot 2 on the current channel -#define SR_DIMM3 0x1000 ///< Single rank dimm in slot 3 on the current channel -#define DR_DIMM0 0x0002 ///< Dual rank dimm in slot 0 on the current channel -#define DR_DIMM1 0x0020 ///< Dual rank dimm in slot 1 on the current channel -#define DR_DIMM2 0x0200 ///< Dual rank dimm in slot 2 on the current channel -#define DR_DIMM3 0x2000 ///< Dual rank dimm in slot 3 on the current channel -#define QR_DIMM0 0x0004 ///< Quad rank dimm in slot 0 on the current channel -#define QR_DIMM1 0x0040 ///< Quad rank dimm in slot 1 on the current channel -#define QR_DIMM2 0x0400 ///< Quad rank dimm in slot 2 on the current channel -#define QR_DIMM3 0x4000 ///< Quad rank dimm in slot 3 on the current channel -#define ANY_DIMM0 0x000F ///< Any Dimm combination in slot 0 on the current channel -#define ANY_DIMM1 0x00F0 ///< Any Dimm combination in slot 1 on the current channel -#define ANY_DIMM2 0x0F00 ///< Any Dimm combination in slot 2 on the current channel -#define ANY_DIMM3 0xF000 ///< Any Dimm combination in slot 3 on the current channel -/// -///< Number of Dimms on the current channel -///< This is a mask used to indicate the number of dimms in a channel -///< They can be added to indicate multiple conditions (i.e 1 OR 2 Dimms) -/// -#define ANY_NUM 0xFF ///< Any number of Dimms -#define NO_DIMM 0x00 ///< No Dimms present -#define ONE_DIMM 0x01 ///< One dimm Poulated on the current channel -#define TWO_DIMM 0x02 ///< Two dimms Poulated on the current channel -#define THREE_DIMM 0x04 ///< Three dimms Poulated on the current channel -#define FOUR_DIMM 0x08 ///< Four dimms Poulated on the current channel - -/*---------------------------------------------------------------------------------------- - * - * Platform Specific Override Definitions for Socket, Channel and Dimm - * This indicates where a platform override will be applied. - * - *---------------------------------------------------------------------------------------- - */ -/// -///< SOCKET MASKS -///< Indicates associated processor sockets to apply override settings -/// -#define ANY_SOCKET 0xFF ///< Apply to all sockets -#define SOCKET0 0x01 ///< Apply to socket 0 -#define SOCKET1 0x02 ///< Apply to socket 1 -#define SOCKET2 0x04 ///< Apply to socket 2 -#define SOCKET3 0x08 ///< Apply to socket 3 -#define SOCKET4 0x10 ///< Apply to socket 4 -#define SOCKET5 0x20 ///< Apply to socket 5 -#define SOCKET6 0x40 ///< Apply to socket 6 -#define SOCKET7 0x80 ///< Apply to socket 7 -/// -///< CHANNEL MASKS -///< Indicates Memory channels where override should be applied -/// -#define ANY_CHANNEL 0xFF ///< Apply to all Memory channels -#define CHANNEL_A 0x01 ///< Apply to Channel A -#define CHANNEL_B 0x02 ///< Apply to Channel B -#define CHANNEL_C 0x04 ///< Apply to Channel C -#define CHANNEL_D 0x08 ///< Apply to Channel D -/// -/// DIMM MASKS -/// Indicates Dimm Slots where override should be applied -/// -#define ALL_DIMMS 0xFF ///< Apply to all dimm slots -#define DIMM0 0x01 ///< Apply to Dimm Slot 0 -#define DIMM1 0x02 ///< Apply to Dimm Slot 1 -#define DIMM2 0x04 ///< Apply to Dimm Slot 2 -#define DIMM3 0x08 ///< Apply to Dimm Slot 3 -/// -/// REGISTER ACCESS MASKS -/// Not supported as an at this time -/// -#define ACCESS_NB0 0x0 -#define ACCESS_NB1 0x1 -#define ACCESS_NB2 0x2 -#define ACCESS_NB3 0x3 -#define ACCESS_NB4 0x4 -#define ACCESS_PHY 0x5 -#define ACCESS_DCT_XT 0x6 - -/*---------------------------------------------------------------------------------------- - * - * Platform Specific Overriding Table Definitions - * - *---------------------------------------------------------------------------------------- - */ - -#define PSO_END 0 ///< Table End -#define PSO_CKE_TRI 1 ///< CKE Tristate Map -#define PSO_ODT_TRI 2 ///< ODT Tristate Map -#define PSO_CS_TRI 3 ///< CS Tristate Map -#define PSO_MAX_DIMMS 4 ///< Max Dimms per channel -#define PSO_CLK_SPEED 5 ///< Clock Speed -#define PSO_DIMM_TYPE 6 ///< Dimm Type -#define PSO_MEMCLK_DIS 7 ///< MEMCLK Disable Map -#define PSO_MAX_CHNLS 8 ///< Max Channels per Socket -#define PSO_BUS_SPEED 9 ///< Max Memory Bus Speed -#define PSO_MAX_CHIPSELS 10 ///< Max Chipsel per Channel -#define PSO_MEM_TECH 11 ///< Channel Memory Type -#define PSO_WL_SEED 12 ///< DDR3 Write Levelization Seed delay -#define PSO_RXEN_SEED 13 ///< Hardwared based RxEn seed -#define PSO_NO_LRDIMM_CS67_ROUTING 14 ///< CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs - -/*---------------------------------- - * CONDITIONAL PSO SPECIFIC ENTRIES - *---------------------------------*/ -// Condition Types -#define CONDITIONAL_PSO_MIN 100 ///< Start of Conditional Entry Types -#define PSO_CONDITION_AND 100 ///< And Block - Start of Conditional block -#define PSO_CONDITION_LOC 101 ///< Location - Specify Socket, Channel, Dimms to be affected -#define PSO_CONDITION_SPD 102 ///< SPD - Specify a specific SPD value on a Dimm on the channel -#define PSO_CONDITION_REG 103 // Reserved -#define PSO_CONDITION_MAX 103 ///< End Of Condition Entry Types -// Action Types -#define PSO_ACTION_MIN 120 ///< Start of Action Entry Types -#define PSO_ACTION_ODT 120 ///< ODT values to override -#define PSO_ACTION_ADDRTMG 121 ///< Address/Timing values to override -#define PSO_ACTION_ODCCONTROL 122 ///< ODC Control values to override -#define PSO_ACTION_SLEWRATE 123 ///< Slew Rate value to override -#define PSO_ACTION_REG 124 // Reserved -#define PSO_ACTION_SPEEDLIMIT 125 ///< Memory Bus speed Limit based on configuration -#define PSO_ACTION_MAX 125 ///< End of Action Entry Types -#define CONDITIONAL_PSO_MAX 139 ///< End of Conditional Entry Types - -/*---------------------------------------------------------------------------------------- - * CONDITIONAL OVERRIDE TABLE MACROS - *---------------------------------------------------------------------------------------- - */ -#define MEMCLK_DIS_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \ - PSO_MEMCLK_DIS, 10, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map - -#define CKE_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map) \ - PSO_CKE_TRI, 4, SocketID, ChannelID, Bit0Map, Bit1Map - -#define ODT_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \ - PSO_ODT_TRI, 6, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map - -#define CS_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \ - PSO_CS_TRI, 10, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map - -#define NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) \ - PSO_MAX_DIMMS, 3, SocketID, ChannelID, NumberOfDimmSlotsPerChannel - -#define NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) \ - PSO_MAX_CHIPSELS, 3, SocketID, ChannelID, NumberOfChipSelectsPerChannel - -#define NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) \ - PSO_MAX_CHNLS, 3, SocketID, ANY_CHANNEL, NumberOfChannelsPerSocket - -#define OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, TimingMode, BusSpeed) \ - PSO_BUS_SPEED, 10, SocketID, ChannelID, TimingMode, (TimingMode >> 8), (TimingMode >> 16), (TimingMode >> 24), \ - BusSpeed, (BusSpeed >> 8), (BusSpeed >> 16), (BusSpeed >> 24) - -#define DRAM_TECHNOLOGY(SocketID, MemTechType) \ - PSO_MEM_TECH, 6, SocketID, ANY_CHANNEL, MemTechType, (MemTechType >> 8), (MemTechType >> 16), (MemTechType >> 24) - -#define WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \ - Byte6Seed, Byte7Seed, ByteEccSeed) \ - PSO_WL_SEED, 11, SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \ - Byte6Seed, Byte7Seed, ByteEccSeed - -#define HW_RXEN_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \ - Byte6Seed, Byte7Seed, ByteEccSeed) \ - PSO_RXEN_SEED, 20, SocketID, ChannelID, Byte0Seed, (Byte0Seed >> 8), Byte1Seed, (Byte1Seed >> 8), Byte2Seed, (Byte2Seed >> 8), \ - Byte3Seed, (Byte3Seed >> 8), Byte4Seed, (Byte4Seed >> 8), Byte5Seed, (Byte5Seed >> 8), Byte6Seed, (Byte6Seed >> 8), \ - Byte7Seed, (Byte7Seed >> 8), ByteEccSeed, (ByteEccSeed >> 8) - -#define NO_LRDIMM_CS67_ROUTING(SocketID, ChannelID) \ - PSO_NO_LRDIMM_CS67_ROUTING, 3, SocketID, ChannelID, TRUE - - -/*---------------------------------------------------------------------------------------- - * CONDITIONAL OVERRIDE TABLE MACROS - *---------------------------------------------------------------------------------------- - */ -#define CONDITION_AND \ - PSO_CONDITION_AND, 0 - -#define COND_LOC(SocketMsk, ChannelMsk, DimmMsk) \ - PSO_CONDITION_LOC, 3, SocketMsk, ChannelMsk, DimmMsk - -#define COND_SPD(Byte, Mask, Value) \ - PSO_CONDITION_SPD, 3, Byte, Mask, Value - -#define COND_REG(Access, Offset, Mask, Value) \ - PSO_CONDITION_REG, 11, Access, (Offset & 0x0FF), (Offset >> 8), \ - ((Mask) & 0x0FF), (((Mask) >> 8) & 0x0FF), (((Mask) >> 16) & 0x0FF), (((Mask) >> 24) & 0x0FF), \ - ((Value) & 0x0FF), (((Value) >> 8) & 0x0FF), (((Value) >> 16) & 0x0FF), (((Value) >> 24) & 0x0FF) - -#define ACTION_ODT(Frequency, Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt) \ - PSO_ACTION_ODT, 9, \ - ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), ((Frequency >> 24)& 0x0FF), \ - Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt - -#define ACTION_ADDRTMG(Frequency, DimmConfig, AddrTmg) \ - PSO_ACTION_ADDRTMG, 10, \ - ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ - ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \ - (AddrTmg & 0x0FF), ((AddrTmg >> 8)& 0x0FF), ((AddrTmg >> 16)& 0x0FF), ((AddrTmg >> 24)& 0x0FF) - -#define ACTION_ODCCTRL(Frequency, DimmConfig, OdcCtrl) \ - PSO_ACTION_ODCCONTROL, 10, \ - ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ - ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \ - (OdcCtrl & 0x0FF), ((OdcCtrl >> 8)& 0x0FF), ((OdcCtrl >> 16)& 0x0FF), ((OdcCtrl >> 24)& 0x0FF) - -#define ACTION_SLEWRATE(Frequency, DimmConfig, SlewRate) \ - PSO_ACTION_SLEWRATE, 10, \ - ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \ - ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \ - (SlewRate & 0x0FF), ((SlewRate >> 8)& 0x0FF), ((SlewRate >> 16)& 0x0FF), ((SlewRate >> 24)& 0x0FF) - -#define ACTION_SPEEDLIMIT(DimmConfig, Dimms, SpeedLimit15, SpeedLimit135, SpeedLimit125) \ - PSO_ACTION_SPEEDLIMIT, 9, \ - ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), Dimms, \ - (SpeedLimit15 & 0x0FF), ((SpeedLimit15 >> 8)& 0x0FF), \ - (SpeedLimit135 & 0x0FF), ((SpeedLimit135 >> 8)& 0x0FF), \ - (SpeedLimit125 & 0x0FF), ((SpeedLimit125 >> 8)& 0x0FF) - -/*---------------------------------------------------------------------------------------- - * END OF CONDITIONAL OVERRIDE TABLE MACROS - *---------------------------------------------------------------------------------------- - */ - -#endif // _PLATFORM_MEMORY_CONFIGURATION_H_ diff --git a/src/vendorcode/amd/agesa/Include/SabineInstall.h b/src/vendorcode/amd/agesa/Include/SabineInstall.h deleted file mode 100644 index 99838e3c01..0000000000 --- a/src/vendorcode/amd/agesa/Include/SabineInstall.h +++ /dev/null @@ -1,117 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build options for a Sabine platform solution - * - * This file generates the defaults tables for the "Sabine" platform solution - * set of processors. The documented build options are imported from a user - * controlled file for processing. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 37651 $ @e \$Date: 2010-09-09 07:05:06 +0800 (Thu, 09 Sep 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "CommonReturns.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterface.h" - -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ - // This is the delivery package title, "LlanoPI " - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'L', 'l', 'a', 'n', 'o', 'P', 'I', ' '} - - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '6', '.', '0', 'X', ' ', ' ', ' '} - - -// The Sabine solution is defined to be family 0x12 in the FS1 and FP1 sockets. -#define INSTALL_FS1_SOCKET_SUPPORT TRUE -#define INSTALL_FP1_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_12_SUPPORT TRUE - -#ifdef BLDOPT_REMOVE_FS1_SOCKET_SUPPORT - #if BLDOPT_REMOVE_FS1_SOCKET_SUPPORT == TRUE - #undef INSTALL_FS1_SOCKET_SUPPORT - #define INSTALL_FS1_SOCKET_SUPPORT FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_FP1_SOCKET_SUPPORT - #if BLDOPT_REMOVE_FP1_SOCKET_SUPPORT == TRUE - #undef INSTALL_FP1_SOCKET_SUPPORT - #define INSTALL_FP1_SOCKET_SUPPORT FALSE - #endif -#endif - - -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED -#define DFLT_VRM_SLEW_RATE (5000) - - -// Instantiate all solution relevant data. -#include "PlatformInstall.h" - diff --git a/src/vendorcode/amd/agesa/Include/SanMarinoInstall.h b/src/vendorcode/amd/agesa/Include/SanMarinoInstall.h deleted file mode 100644 index e0b4c596da..0000000000 --- a/src/vendorcode/amd/agesa/Include/SanMarinoInstall.h +++ /dev/null @@ -1,118 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build options for a SanMarino platform solution - * - * This file generates the defaults tables for the "San Marino" platform solution - * set of processors. The documented build options are imported from a user - * controlled file for processing. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "AGESA.h" -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "CommonReturns.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterfaceStub.h" - -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ - // This is the delivery package title, "OrochiPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'} - - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '6', '.', '0', 'X', ' ', ' ', ' '} - - -// The San Marino solution is defined to be families 0x10 and 0x15 in the C32 socket. -#define INSTALL_C32_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_10_SUPPORT TRUE -#define INSTALL_FAMILY_15_SUPPORT TRUE - -#ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT - #if BLDOPT_REMOVE_FAMILY_10_SUPPORT == TRUE - #undef INSTALL_FAMILY_10_SUPPORT - #define INSTALL_FAMILY_10_SUPPORT FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_FAMILY_15_SUPPORT - #if BLDOPT_REMOVE_FAMILY_15_SUPPORT == TRUE - #undef INSTALL_FAMILY_15_SUPPORT - #define INSTALL_FAMILY_15_SUPPORT FALSE - #endif -#endif - - -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0xFF) -#define DFLT_SCRUB_L2_RATE (0x10) -#define DFLT_SCRUB_L3_RATE (0x10) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0x12) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED -#define DFLT_VRM_SLEW_RATE (2500) - - -// Instantiate all solution relevant data. -#include "PlatformInstall.h" - diff --git a/src/vendorcode/amd/agesa/Include/ScorpiusInstall.h b/src/vendorcode/amd/agesa/Include/ScorpiusInstall.h deleted file mode 100644 index f3d3cc014a..0000000000 --- a/src/vendorcode/amd/agesa/Include/ScorpiusInstall.h +++ /dev/null @@ -1,117 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build options for a Scorpius platform solution - * - * This file generates the defaults tables for the "Scorpius" platform solution - * set of processors. The documented build options are imported from a user - * controlled file for processing. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "CommonReturns.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterfaceStub.h" - -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ - // This is the delivery package title, "OrochiPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'} - - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '6', '.', '0', 'X', ' ', ' ', ' '} - - -// The Scorpius solution is defined to be families 0x10 and 0x15 in the AM3 socket. -#define INSTALL_AM3_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_10_SUPPORT TRUE -#define INSTALL_FAMILY_15_SUPPORT TRUE - -#ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT - #if BLDOPT_REMOVE_FAMILY_10_SUPPORT == TRUE - #undef INSTALL_FAMILY_10_SUPPORT - #define INSTALL_FAMILY_10_SUPPORT FALSE - #endif -#endif - -#ifdef BLDOPT_REMOVE_FAMILY_15_SUPPORT - #if BLDOPT_REMOVE_FAMILY_15_SUPPORT == TRUE - #undef INSTALL_FAMILY_15_SUPPORT - #define INSTALL_FAMILY_15_SUPPORT FALSE - #endif -#endif - - -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED -#define DFLT_VRM_SLEW_RATE (2500) - - -// Instantiate all solution relevant data. -#include "PlatformInstall.h" - diff --git a/src/vendorcode/amd/agesa/Include/TigrisInstall.h b/src/vendorcode/amd/agesa/Include/TigrisInstall.h deleted file mode 100644 index 77404e0fb9..0000000000 --- a/src/vendorcode/amd/agesa/Include/TigrisInstall.h +++ /dev/null @@ -1,102 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Install of build options for a Tigris platform solution - * - * This file generates the defaults tables for the "Tigris" platform solution - * set of processors. The documented build options are imported from a user - * controlled file for processing. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "cpuRegisters.h" -#include "cpuFamRegisters.h" -#include "cpuFamilyTranslation.h" -#include "AdvancedApi.h" -#include "heapManager.h" -#include "CreateStruct.h" -#include "cpuFeatures.h" -#include "Table.h" -#include "CommonReturns.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "GnbInterfaceStub.h" - -/***************************************************************************** - * Define the RELEASE VERSION string - * - * The Release Version string should identify the next planned release. - * When a branch is made in preparation for a release, the release manager - * should change/confirm that the branch version of this file contains the - * string matching the desired version for the release. The trunk version of - * the file should always contain a trailing 'X'. This will make sure that a - * development build from trunk will not be confused for a released version. - * The release manager will need to remove the trailing 'X' and update the - * version string as appropriate for the release. The trunk copy of this file - * should also be updated/incremented for the next expected version, + trailing 'X' - ****************************************************************************/ - // This is the delivery package title, "TigrisPI" - // This string MUST be exactly 8 characters long -#define AGESA_PACKAGE_STRING {'T', 'i', 'g', 'r', 'i', 's', 'P', 'I'} - - // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long -#define AGESA_VERSION_STRING {'V', '0', '.', '1', '.', '2', '.', '3', 'X', ' ', ' ', ' '} - - -// The Tigris solution is defined to be family 0x10 in the S1g3 socket. -#define INSTALL_S1G3_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_10_SUPPORT TRUE - - -// The following definitions specify the default values for various parameters in which there are -// no clearly defined defaults to be used in the common file. The values below are based on product -// and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED -#define DFLT_VRM_SLEW_RATE (5000) - - -// Instantiate all solution relevant data. -#include "PlatformInstall.h" - diff --git a/src/vendorcode/amd/agesa/Include/Topology.h b/src/vendorcode/amd/agesa/Include/Topology.h deleted file mode 100644 index 73c324e773..0000000000 --- a/src/vendorcode/amd/agesa/Include/Topology.h +++ /dev/null @@ -1,165 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Topology interface definitions. - * - * Contains AMD AGESA internal interface for topology related data which - * is consumed by code other than HyperTransport init (and produced by - * HyperTransport init.) - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _TOPOLOGY_H_ -#define _TOPOLOGY_H_ - -// Defines for limiting data structure maximum allocation and limit checking. -#define MAX_NODES 8 -#define MAX_SOCKETS MAX_NODES -#define MAX_DIES 2 - -// Defines useful with package link -#define HT_LIST_MATCH_INTERNAL_LINK_0 0xFA -#define HT_LIST_MATCH_INTERNAL_LINK_1 0xFB -#define HT_LIST_MATCH_INTERNAL_LINK_2 0xFC - -/** - * Hop Count Table. - * This is a heap data structure. The Hops array is filled as a size x size matrix. - * The unused space, if any, is all at the end. - */ -typedef struct { - UINT8 Size; ///< The row and column size of actual hop count data */ - UINT8 Hops[MAX_NODES * MAX_NODES]; ///< Room for a dynamic two dimensional array of [size][size] */ -} HOP_COUNT_TABLE; - -/** - * Socket and Module to Node Map Item. - * Provide the Node Id and core id range for each module in each processor. - */ -typedef struct { - UINT8 Node; ///< The module's Node id. - UINT8 LowCore; ///< The lowest processor core id for this module. - UINT8 HighCore; ///< The highest processor core id for this module. - UINT8 EnabledComputeUnits; ///< The value of Enabled for this processor module. - UINT8 DualCoreComputeUnits; ///< The value of DualCore for this processor module. -} SOCKET_DIE_TO_NODE_ITEM; - -/** - * Socket and Module to Node Map. - * This type is a pointer to the actual map, it can be used for a struct item or - * for typecasting a heap buffer pointer. - */ -typedef SOCKET_DIE_TO_NODE_ITEM (*SOCKET_DIE_TO_NODE_MAP)[MAX_SOCKETS][MAX_DIES]; - -/** - * Node id to Socket Die Map Item. - */ -typedef struct { - UINT8 Socket; ///< socket of the processor containing the Node. - UINT8 Die; ///< the module in the processor which is Node. -} NODE_TO_SOCKET_DIE_ITEM; - -/** - * Node id to Socket Die Map. - */ -typedef NODE_TO_SOCKET_DIE_ITEM (*NODE_TO_SOCKET_DIE_MAP)[MAX_NODES]; - -/** - * Provide AP core with socket and node context at start up. - * This information is posted to the AP cores using a register as a mailbox. - */ -typedef struct { - UINT32 Node:4; ///< The node id of Core's node. - UINT32 Socket:4; ///< The socket of this Core's node. - UINT32 Module:2; ///< The internal module number for Core's node. - UINT32 ModuleType:2; ///< Single Module = 0, Multi-module = 1. - UINT32 :20; ///< Reserved -} AP_MAIL_INFO_FIELDS; - -/** - * AP info fields can be written and read to a register. - */ -typedef union { - UINT32 Info; ///< Just a number for register access, or opaque passing. - AP_MAIL_INFO_FIELDS Fields; ///< access to the info fields. -} AP_MAIL_INFO; - -/** - * Provide AP core with system degree and system core number at start up. - * This information is posted to the AP cores using a register as a mailbox. - */ -typedef struct { - UINT32 SystemDegree:3; ///< The number of connected links - UINT32 :3; ///< Reserved - UINT32 HeapIndex:6; ///< The zero-based system core number - UINT32 :20; ///< Reserved -} AP_MAIL_EXT_INFO_FIELDS; - -/** - * AP info fields can be written and read to a register. - */ -typedef union { - UINT32 Info; ///< Just a number for register access, or opaque passing. - AP_MAIL_EXT_INFO_FIELDS Fields; ///< access to the info fields. -} AP_MAIL_EXT_INFO; - -/** - * AP Info mailbox set. - */ -typedef struct { - AP_MAIL_INFO ApMailInfo; ///< The AP mail info - AP_MAIL_EXT_INFO ApMailExtInfo; ///< The extended AP mail info -} AP_MAILBOXES; - -/** - * Provide a northbridge to package mapping for link assignments. - * - */ -typedef struct { - UINT8 Link; ///< The Node's link - UINT8 Module; ///< The internal module position of Node - UINT8 PackageLink; ///< The corresponding package link -} PACKAGE_HTLINK_MAP_ITEM; - -/** - * A Processor's complete set of link assignments - */ -typedef PACKAGE_HTLINK_MAP_ITEM (*PACKAGE_HTLINK_MAP)[]; - -#endif // _TOPOLOGY_H_ diff --git a/src/vendorcode/amd/agesa/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/Include/gcc-intrin.h deleted file mode 100644 index 58438b9815..0000000000 --- a/src/vendorcode/amd/agesa/Include/gcc-intrin.h +++ /dev/null @@ -1,630 +0,0 @@ -/* - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#if defined (__GNUC__) - -/* I/O intrin functions. */ -static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned short Port) -{ - unsigned char value; - - __asm__ __volatile__ ( - "in %%dx, %%al" - : "=a" (value) - : "d" (Port) - ); - - return value; -} - -static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigned short Port) -{ - unsigned short value; - - __asm__ __volatile__ ( - "in %%dx, %%ax" - : "=a" (value) - : "d" (Port) - ); - - return value; -} - -static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigned short Port) -{ - unsigned long value; - - __asm__ __volatile__ ( - "in %%dx, %%eax" - : "=a" (value) - : "d" (Port) - ); - return value; - -} - -static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short Port,unsigned char Data) -{ - __asm__ __volatile__ ( - "out %%al, %%dx" - : - : "a" (Data), "d" (Port) - ); -} - -static __inline__ __attribute__((always_inline)) void __outword(unsigned short Port,unsigned short Data) -{ - __asm__ __volatile__ ( - "out %%ax, %%dx" - : - : "a" (Data), "d" (Port) - ); -} - -static __inline__ __attribute__((always_inline)) void __outdword(unsigned short Port,unsigned long Data) -{ - __asm__ __volatile__ ( - "out %%eax, %%dx" - : - : "a" (Data), "d" (Port) - ); -} - -static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count) -{ - __asm__ __volatile__ ( - "cld ; rep ; insb " - : "=D" (Buffer), "=c" (Count) - : "d"(Port), "0"(Buffer), "1" (Count) - ); -} - -static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count) -{ - __asm__ __volatile__ ( - "cld ; rep ; insw " - : "=D" (Buffer), "=c" (Count) - : "d"(Port), "0"(Buffer), "1" (Count) - ); -} - -static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count) -{ - __asm__ __volatile__ ( - "cld ; rep ; insl " - : "=D" (Buffer), "=c" (Count) - : "d"(Port), "0"(Buffer), "1" (Count) - ); -} - -static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count) -{ - __asm__ __volatile__ ( - "cld ; rep ; outsb " - : "=S" (Buffer), "=c" (Count) - : "d"(Port), "0"(Buffer), "1" (Count) - ); -} - -static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count) -{ - __asm__ __volatile__ ( - "cld ; rep ; outsw " - : "=S" (Buffer), "=c" (Count) - : "d"(Port), "0"(Buffer), "1" (Count) - ); -} - -static __inline__ __attribute__((always_inline)) void __outdwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count) -{ - __asm__ __volatile__ ( - "cld ; rep ; outsl " - : "=S" (Buffer), "=c" (Count) - : "d"(Port), "0"(Buffer), "1" (Count) - ); -} - -static __inline__ __attribute__((always_inline)) unsigned long __readdr0(void) -{ - unsigned long value; - __asm__ __volatile__ ( - "mov %%dr0, %[value]" - : [value] "=a" (value) - ); - return value; -} - -static __inline__ __attribute__((always_inline)) unsigned long __readdr1(void) -{ - unsigned long value; - __asm__ __volatile__ ( - "mov %%dr1, %[value]" - : [value] "=a" (value) - ); - return value; -} - -static __inline__ __attribute__((always_inline)) unsigned long __readdr2(void) -{ - unsigned long value; - __asm__ __volatile__ ( - "mov %%dr2, %[value]" - : [value] "=a" (value) - ); - return value; -} - -static __inline__ __attribute__((always_inline)) unsigned long __readdr3(void) -{ - unsigned long value; - __asm__ __volatile__ ( - "mov %%dr3, %[value]" - : [value] "=a" (value) - ); - return value; -} - -static __inline__ __attribute__((always_inline)) unsigned long __readdr7(void) -{ - unsigned long value; - __asm__ __volatile__ ( - "mov %%dr7, %[value]" - : [value] "=a" (value) - ); - return value; -} - -static __inline__ __attribute__((always_inline)) unsigned long __readdr(unsigned long reg) -{ - switch (reg){ - case 0: - return __readdr0 (); - break; - - case 1: - return __readdr1 (); - break; - - case 2: - return __readdr2 (); - break; - - case 3: - return __readdr3 (); - break; - - case 7: - return __readdr7 (); - break; - - default: - return -1; - } -} - -static __inline__ __attribute__((always_inline)) void __writedr0(unsigned long Data) -{ - __asm__ __volatile__ ( - "mov %%eax, %%dr0" - : - : "a" (Data) - ); -} - -static __inline__ __attribute__((always_inline)) void __writedr1(unsigned long Data) -{ - __asm__ __volatile__ ( - "mov %%eax, %%dr1" - : - : "a" (Data) - ); -} - -static __inline__ __attribute__((always_inline)) void __writedr2(unsigned long Data) -{ - __asm__ __volatile__ ( - "mov %%eax, %%dr2" - : - : "a" (Data) - ); -} - -static __inline__ __attribute__((always_inline)) void __writedr3(unsigned long Data) -{ - __asm__ __volatile__ ( - "mov %%eax, %%dr3" - : - : "a" (Data) - ); -} - -static __inline__ __attribute__((always_inline)) void __writedr7(unsigned long Data) -{ - __asm__ __volatile__ ( - "mov %%eax, %%dr7" - : - : "a" (Data) - ); -} - -static __inline__ __attribute__((always_inline)) void __writedr(unsigned long reg, unsigned long Data) -{ - switch (reg){ - case 0: - __writedr0 (Data); - break; - - case 1: - __writedr1 (Data); - break; - - case 2: - __writedr2 (Data); - break; - - case 3: - __writedr3 (Data); - break; - - case 7: - __writedr7 (Data); - break; - - default: - ; - } -} - -static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void) -{ - unsigned long value; - __asm__ __volatile__ ( - "mov %%cr0, %[value]" - : [value] "=a" (value)); - return value; -} - -static __inline__ __attribute__((always_inline)) unsigned long __readcr2(void) -{ - unsigned long value; - __asm__ __volatile__ ( - "mov %%cr2, %[value]" - : [value] "=a" (value)); - return value; -} - -static __inline__ __attribute__((always_inline)) unsigned long __readcr3(void) -{ - unsigned long value; - __asm__ __volatile__ ( - "mov %%cr3, %[value]" - : [value] "=a" (value)); - return value; -} - -static __inline__ __attribute__((always_inline)) unsigned long __readcr4(void) -{ - unsigned long value; - __asm__ __volatile__ ( - "mov %%cr4, %[value]" - : [value] "=a" (value)); - return value; -} - -static __inline__ __attribute__((always_inline)) unsigned long __readcr8(void) -{ - unsigned long value; - __asm__ __volatile__ ( - "mov %%cr8, %[value]" - : [value] "=a" (value)); - return value; -} - -static __inline__ __attribute__((always_inline)) unsigned long __readcr(unsigned long reg) -{ - switch (reg){ - case 0: - return __readcr0 (); - break; - - case 2: - return __readcr2 (); - break; - - case 3: - return __readcr3 (); - break; - - case 4: - return __readcr4 (); - break; - - case 8: - return __readcr8 (); - break; - - default: - return -1; - } -} - -static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long Data) -{ - __asm__ __volatile__ ( - "mov %%eax, %%cr0" - : - : "a" (Data) - ); -} - -static __inline__ __attribute__((always_inline)) void __writecr2(unsigned long Data) -{ - __asm__ __volatile__ ( - "mov %%eax, %%cr2" - : - : "a" (Data) - ); -} - -static __inline__ __attribute__((always_inline)) void __writecr3(unsigned long Data) -{ - __asm__ __volatile__ ( - "mov %%eax, %%cr3" - : - : "a" (Data) - ); -} - -static __inline__ __attribute__((always_inline)) void __writecr4(unsigned long Data) -{ - __asm__ __volatile__ ( - "mov %%eax, %%cr4" - : - : "a" (Data) - ); -} - -static __inline__ __attribute__((always_inline)) void __writecr8(unsigned long Data) -{ - __asm__ __volatile__ ( - "mov %%eax, %%cr8" - : - : "a" (Data) - ); -} - -static __inline__ __attribute__((always_inline)) void __writecr(unsigned long reg, unsigned long Data) -{ - switch (reg){ - case 0: - __writecr0 (Data); - break; - - case 2: - __writecr2 (Data); - break; - - case 3: - __writecr3 (Data); - break; - - case 4: - __writecr4 (Data); - break; - - case 8: - __writecr8 (Data); - break; - - default: - ; - } -} - -static __inline__ __attribute__((always_inline)) UINT64 __readmsr(UINT32 msr) -{ - UINT64 retval; - __asm__ __volatile__( - "rdmsr\n\t" - : "=A" (retval) - : "c" (msr) - ); - return retval; -} - -static __inline__ __attribute__((always_inline)) void __writemsr (UINT32 msr, UINT64 Value) -{ - __asm__ __volatile__ ( - "wrmsr\n\t" - : - : "c" (msr), "A" (Value) - ); -} - -static __inline__ __attribute__((always_inline)) UINT64 __rdtsc(void) -{ - UINT64 retval; - __asm__ __volatile__ ( - "rdtsc" - : "=A" (retval)); - return retval; -} - -static __inline__ __attribute__((always_inline)) void __cpuid(int CPUInfo[], const int InfoType) -{ - __asm__ __volatile__( - "cpuid" - :"=a" (CPUInfo[0]), "=b" (CPUInfo[1]), "=c" (CPUInfo[2]), "=d" (CPUInfo[3]) - : "a" (InfoType) - ); -} - - -static __inline__ __attribute__((always_inline)) void _disable(void) -{ - __asm__ __volatile__ ("cli"); -} - - -static __inline__ __attribute__((always_inline)) void _enable(void) -{ - __asm__ __volatile__ ("sti"); -} - - -static __inline__ __attribute__((always_inline)) void __halt(void) -{ - __asm__ __volatile__ ("hlt"); -} - - -static __inline__ __attribute__((always_inline)) void __debugbreak(void) -{ - __asm__ __volatile__ ("int3"); -} - - -static __inline__ __attribute__((always_inline)) void __wbinvd(void) -{ - __asm__ __volatile__ ("wbinvd"); -} - - -static __inline__ __attribute__((always_inline)) void __lidt(void *Source) -{ - __asm__ __volatile__("lidt %0" : : "m"(*(short*)Source)); -} - -static __inline__ __attribute__((always_inline)) void __writefsbyte(const unsigned long Offset, const unsigned char Data) -{ - __asm__("movb %b[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data)); -} - -static __inline__ __attribute__((always_inline)) void __writefsword(const unsigned long Offset, const unsigned short Data) -{ - __asm__("movw %w[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data)); -} - -static __inline__ __attribute__((always_inline)) void __writefsdword(const unsigned long Offset, const unsigned long Data) -{ - __asm__("movl %k[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data)); -} - -static __inline__ __attribute__((always_inline)) unsigned char __readfsbyte(const unsigned long Offset) -{ - unsigned char value; - __asm__("movb %%fs:%a[Offset], %b[value]" : [value] "=q" (value) : [Offset] "irm" (Offset)); - return value; -} - -static __inline__ __attribute__((always_inline)) unsigned short __readfsword(const unsigned long Offset) -{ - unsigned short value; - __asm__("movw %%fs:%a[Offset], %w[value]" : [value] "=q" (value) : [Offset] "irm" (Offset)); - return value; -} - -static __inline__ __attribute__((always_inline)) unsigned long long __readfsdword(unsigned long long Offset) -{ - unsigned long long value; - __asm__("movl %%fs:%a[Offset], %k[value]" : [value] "=q" (value) : [Offset] "irm" (Offset)); - return value; -} - -#ifdef __SSE3__ -typedef long long __v2di __attribute__ ((__vector_size__ (16))); -typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); - -static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs2 (void *__A, __m128i __B) -{ - __asm__(".byte 0x64"); // fs prefix - __builtin_ia32_movntdq ((__v2di *)__A, (__v2di)__B); -} - -static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs (void *__A, void *__B) -{ - __m128i data; - data = (__m128i) __builtin_ia32_lddqu ((char const *)__B); - _mm_stream_si128_fs2 (__A, data); -} - -static __inline__ __attribute__((always_inline)) void _mm_clflush_fs (void *__A) -{ - __asm__(".byte 0x64"); // fs prefix - __builtin_ia32_clflush (__A); -} - -static __inline __attribute__(( __always_inline__)) void _mm_mfence (void) -{ - __builtin_ia32_mfence (); -} - -static __inline __attribute__(( __always_inline__)) void _mm_sfence (void) -{ - __builtin_ia32_sfence (); -} -#endif - -static __inline__ __attribute__((always_inline)) void __stosb(unsigned char *dest, unsigned char data, size_t count) -{ - __asm__ __volatile__ ( - "cld ; rep ; stosb " - : "=D" (dest), "=c" (count) - : "a"(data), "0"(dest), "1" (count) - ); -} - -static __inline__ __attribute__((always_inline)) void __movsb(unsigned char *dest, unsigned char *data, size_t count) -{ - __asm__ __volatile__ ( - "cld ; rep ; movsb " - : "=D" (dest), "=S"(data), "=c" (count) - : "S"(data), "0"(dest), "1" (count) - ); -} - -static __inline__ __attribute__((always_inline)) -void debug_point ( unsigned short Port, unsigned long Data ) -{ - __outdword (Port, Data); - __asm__ __volatile__ (".word 0xfeeb"); - -} - -static __inline__ __attribute__((always_inline)) -void delay_point ( unsigned short Port, unsigned long Data, unsigned long delayTime ) -{ - UINTN Index; - Index = 0; - __outdword (Port, Data); - while (Index < delayTime * 600000) { - __outdword (0xE0, 0); - Index ++; - } -} -#endif // defined (__GNUC__) -- cgit v1.2.3