From 8301d8348a0848d56fdf4dbd76acd6bdcd3fc944 Mon Sep 17 00:00:00 2001 From: stepan Date: Wed, 8 Dec 2010 07:07:33 +0000 Subject: second round name simplification. drop the _ prefix. the prefix was introduced in the early v2 tree many years ago because our old build system "newconfig" could not handle two files with the same name in different paths like /path/to/usb.c and /another/path/to/usb.c correctly. Only one of the files would end up being compiled into the final image. Since Kconfig (actually since shortly before we switched to Kconfig) we don't suffer from that problem anymore. So we could drop the sb700_ prefix from all those filenames (or, the _ prefix in general) - makes it easier to fork off a new chipset - makes it easier to diff against other chipsets - storing redundant information in filenames seems wrong Signed-off-by: Acked-by: Patrick Georgi Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/superio/fintek/f71805f/early_serial.c | 47 ++++++++ src/superio/fintek/f71805f/f71805f_early_serial.c | 47 -------- src/superio/fintek/f71859/early_serial.c | 47 ++++++++ src/superio/fintek/f71859/f71859_early_serial.c | 47 -------- src/superio/fintek/f71863fg/early_serial.c | 47 ++++++++ .../fintek/f71863fg/f71863fg_early_serial.c | 47 -------- src/superio/fintek/f71872/early_serial.c | 47 ++++++++ src/superio/fintek/f71872/f71872_early_serial.c | 47 -------- src/superio/fintek/f71889/early_serial.c | 46 ++++++++ src/superio/fintek/f71889/f71889_early_serial.c | 46 -------- src/superio/intel/i3100/early_serial.c | 56 ++++++++++ src/superio/intel/i3100/i3100_early_serial.c | 56 ---------- src/superio/ite/it8661f/early_serial.c | 79 +++++++++++++ src/superio/ite/it8661f/it8661f_early_serial.c | 79 ------------- src/superio/ite/it8671f/early_serial.c | 105 ++++++++++++++++++ src/superio/ite/it8671f/it8671f_early_serial.c | 105 ------------------ src/superio/ite/it8673f/early_serial.c | 90 +++++++++++++++ src/superio/ite/it8673f/it8673f_early_serial.c | 90 --------------- src/superio/ite/it8705f/early_serial.c | 82 ++++++++++++++ src/superio/ite/it8705f/it8705f_early_serial.c | 82 -------------- src/superio/ite/it8712f/early_serial.c | 117 ++++++++++++++++++++ src/superio/ite/it8712f/it8712f_early_serial.c | 117 -------------------- src/superio/ite/it8716f/early_init.c | 37 +++++++ src/superio/ite/it8716f/early_serial.c | 62 +++++++++++ src/superio/ite/it8716f/it8716f_early_init.c | 37 ------- src/superio/ite/it8716f/it8716f_early_serial.c | 62 ----------- src/superio/ite/it8718f/early_serial.c | 104 +++++++++++++++++ src/superio/ite/it8718f/it8718f_early_serial.c | 104 ----------------- src/superio/nsc/pc8374/early_init.c | 56 ++++++++++ src/superio/nsc/pc8374/pc8374_early_init.c | 56 ---------- src/superio/nsc/pc87309/early_serial.c | 30 +++++ src/superio/nsc/pc87309/pc87309_early_serial.c | 30 ----- src/superio/nsc/pc87351/early_serial.c | 31 ++++++ src/superio/nsc/pc87351/pc87351_early_serial.c | 31 ------ src/superio/nsc/pc87360/early_serial.c | 31 ++++++ src/superio/nsc/pc87360/pc87360_early_serial.c | 31 ------ src/superio/nsc/pc87366/early_serial.c | 31 ++++++ src/superio/nsc/pc87366/pc87366_early_serial.c | 31 ------ src/superio/nsc/pc87417/early_init.c | 54 +++++++++ src/superio/nsc/pc87417/early_serial.c | 38 +++++++ src/superio/nsc/pc87417/pc87417_early_init.c | 54 --------- src/superio/nsc/pc87417/pc87417_early_serial.c | 38 ------- src/superio/nsc/pc87427/early_init.c | 54 +++++++++ src/superio/nsc/pc87427/pc87427_early_init.c | 54 --------- src/superio/nsc/pc97317/early_serial.c | 49 ++++++++ src/superio/nsc/pc97317/pc97317_early_serial.c | 49 -------- src/superio/serverengines/pilot/early_init.c | 122 ++++++++++++++++++++ src/superio/serverengines/pilot/early_serial.c | 57 ++++++++++ src/superio/serverengines/pilot/pilot_early_init.c | 122 -------------------- .../serverengines/pilot/pilot_early_serial.c | 57 ---------- src/superio/smsc/fdc37m60x/early_serial.c | 77 +++++++++++++ .../smsc/fdc37m60x/fdc37m60x_early_serial.c | 77 ------------- src/superio/smsc/lpc47b272/early_serial.c | 53 +++++++++ .../smsc/lpc47b272/lpc47b272_early_serial.c | 53 --------- src/superio/smsc/lpc47b397/early_gpio.c | 49 ++++++++ src/superio/smsc/lpc47b397/early_serial.c | 46 ++++++++ src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c | 49 -------- .../smsc/lpc47b397/lpc47b397_early_serial.c | 46 -------- src/superio/smsc/lpc47m10x/early_serial.c | 51 +++++++++ .../smsc/lpc47m10x/lpc47m10x_early_serial.c | 51 --------- src/superio/smsc/lpc47m15x/early_serial.c | 45 ++++++++ .../smsc/lpc47m15x/lpc47m15x_early_serial.c | 45 -------- src/superio/smsc/lpc47n217/early_serial.c | 123 +++++++++++++++++++++ .../smsc/lpc47n217/lpc47n217_early_serial.c | 123 --------------------- src/superio/smsc/lpc47n227/early_serial.c | 122 ++++++++++++++++++++ .../smsc/lpc47n227/lpc47n227_early_serial.c | 122 -------------------- src/superio/smsc/smscsuperio/early_serial.c | 46 ++++++++ .../smsc/smscsuperio/smscsuperio_early_serial.c | 46 -------- src/superio/winbond/w83627dhg/early_serial.c | 46 ++++++++ .../winbond/w83627dhg/w83627dhg_early_serial.c | 46 -------- src/superio/winbond/w83627ehg/early_init.c | 38 +++++++ src/superio/winbond/w83627ehg/early_serial.c | 46 ++++++++ .../winbond/w83627ehg/w83627ehg_early_init.c | 38 ------- .../winbond/w83627ehg/w83627ehg_early_serial.c | 46 -------- src/superio/winbond/w83627hf/early_init.c | 38 +++++++ src/superio/winbond/w83627hf/early_serial.c | 59 ++++++++++ src/superio/winbond/w83627hf/w83627hf_early_init.c | 38 ------- .../winbond/w83627hf/w83627hf_early_serial.c | 59 ---------- src/superio/winbond/w83627thg/early_serial.c | 47 ++++++++ .../winbond/w83627thg/w83627thg_early_serial.c | 47 -------- src/superio/winbond/w83627uhg/early_serial.c | 58 ++++++++++ .../winbond/w83627uhg/w83627uhg_early_serial.c | 58 ---------- src/superio/winbond/w83697hf/early_serial.c | 57 ++++++++++ .../winbond/w83697hf/w83697hf_early_serial.c | 57 ---------- src/superio/winbond/w83977f/early_serial.c | 45 ++++++++ src/superio/winbond/w83977f/w83977f_early_serial.c | 45 -------- src/superio/winbond/w83977tf/early_serial.c | 47 ++++++++ .../winbond/w83977tf/w83977tf_early_serial.c | 47 -------- 88 files changed, 2612 insertions(+), 2612 deletions(-) create mode 100644 src/superio/fintek/f71805f/early_serial.c delete mode 100644 src/superio/fintek/f71805f/f71805f_early_serial.c create mode 100755 src/superio/fintek/f71859/early_serial.c delete mode 100755 src/superio/fintek/f71859/f71859_early_serial.c create mode 100644 src/superio/fintek/f71863fg/early_serial.c delete mode 100644 src/superio/fintek/f71863fg/f71863fg_early_serial.c create mode 100644 src/superio/fintek/f71872/early_serial.c delete mode 100644 src/superio/fintek/f71872/f71872_early_serial.c create mode 100644 src/superio/fintek/f71889/early_serial.c delete mode 100644 src/superio/fintek/f71889/f71889_early_serial.c create mode 100644 src/superio/intel/i3100/early_serial.c delete mode 100644 src/superio/intel/i3100/i3100_early_serial.c create mode 100644 src/superio/ite/it8661f/early_serial.c delete mode 100644 src/superio/ite/it8661f/it8661f_early_serial.c create mode 100644 src/superio/ite/it8671f/early_serial.c delete mode 100644 src/superio/ite/it8671f/it8671f_early_serial.c create mode 100644 src/superio/ite/it8673f/early_serial.c delete mode 100644 src/superio/ite/it8673f/it8673f_early_serial.c create mode 100644 src/superio/ite/it8705f/early_serial.c delete mode 100644 src/superio/ite/it8705f/it8705f_early_serial.c create mode 100644 src/superio/ite/it8712f/early_serial.c delete mode 100644 src/superio/ite/it8712f/it8712f_early_serial.c create mode 100644 src/superio/ite/it8716f/early_init.c create mode 100644 src/superio/ite/it8716f/early_serial.c delete mode 100644 src/superio/ite/it8716f/it8716f_early_init.c delete mode 100644 src/superio/ite/it8716f/it8716f_early_serial.c create mode 100644 src/superio/ite/it8718f/early_serial.c delete mode 100644 src/superio/ite/it8718f/it8718f_early_serial.c create mode 100644 src/superio/nsc/pc8374/early_init.c delete mode 100644 src/superio/nsc/pc8374/pc8374_early_init.c create mode 100644 src/superio/nsc/pc87309/early_serial.c delete mode 100644 src/superio/nsc/pc87309/pc87309_early_serial.c create mode 100644 src/superio/nsc/pc87351/early_serial.c delete mode 100644 src/superio/nsc/pc87351/pc87351_early_serial.c create mode 100644 src/superio/nsc/pc87360/early_serial.c delete mode 100644 src/superio/nsc/pc87360/pc87360_early_serial.c create mode 100644 src/superio/nsc/pc87366/early_serial.c delete mode 100644 src/superio/nsc/pc87366/pc87366_early_serial.c create mode 100644 src/superio/nsc/pc87417/early_init.c create mode 100644 src/superio/nsc/pc87417/early_serial.c delete mode 100644 src/superio/nsc/pc87417/pc87417_early_init.c delete mode 100644 src/superio/nsc/pc87417/pc87417_early_serial.c create mode 100644 src/superio/nsc/pc87427/early_init.c delete mode 100644 src/superio/nsc/pc87427/pc87427_early_init.c create mode 100644 src/superio/nsc/pc97317/early_serial.c delete mode 100644 src/superio/nsc/pc97317/pc97317_early_serial.c create mode 100644 src/superio/serverengines/pilot/early_init.c create mode 100644 src/superio/serverengines/pilot/early_serial.c delete mode 100644 src/superio/serverengines/pilot/pilot_early_init.c delete mode 100644 src/superio/serverengines/pilot/pilot_early_serial.c create mode 100644 src/superio/smsc/fdc37m60x/early_serial.c delete mode 100644 src/superio/smsc/fdc37m60x/fdc37m60x_early_serial.c create mode 100644 src/superio/smsc/lpc47b272/early_serial.c delete mode 100644 src/superio/smsc/lpc47b272/lpc47b272_early_serial.c create mode 100644 src/superio/smsc/lpc47b397/early_gpio.c create mode 100644 src/superio/smsc/lpc47b397/early_serial.c delete mode 100644 src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c delete mode 100644 src/superio/smsc/lpc47b397/lpc47b397_early_serial.c create mode 100644 src/superio/smsc/lpc47m10x/early_serial.c delete mode 100644 src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c create mode 100644 src/superio/smsc/lpc47m15x/early_serial.c delete mode 100644 src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c create mode 100644 src/superio/smsc/lpc47n217/early_serial.c delete mode 100644 src/superio/smsc/lpc47n217/lpc47n217_early_serial.c create mode 100644 src/superio/smsc/lpc47n227/early_serial.c delete mode 100644 src/superio/smsc/lpc47n227/lpc47n227_early_serial.c create mode 100644 src/superio/smsc/smscsuperio/early_serial.c delete mode 100644 src/superio/smsc/smscsuperio/smscsuperio_early_serial.c create mode 100644 src/superio/winbond/w83627dhg/early_serial.c delete mode 100644 src/superio/winbond/w83627dhg/w83627dhg_early_serial.c create mode 100644 src/superio/winbond/w83627ehg/early_init.c create mode 100644 src/superio/winbond/w83627ehg/early_serial.c delete mode 100644 src/superio/winbond/w83627ehg/w83627ehg_early_init.c delete mode 100644 src/superio/winbond/w83627ehg/w83627ehg_early_serial.c create mode 100644 src/superio/winbond/w83627hf/early_init.c create mode 100644 src/superio/winbond/w83627hf/early_serial.c delete mode 100644 src/superio/winbond/w83627hf/w83627hf_early_init.c delete mode 100644 src/superio/winbond/w83627hf/w83627hf_early_serial.c create mode 100644 src/superio/winbond/w83627thg/early_serial.c delete mode 100644 src/superio/winbond/w83627thg/w83627thg_early_serial.c create mode 100644 src/superio/winbond/w83627uhg/early_serial.c delete mode 100644 src/superio/winbond/w83627uhg/w83627uhg_early_serial.c create mode 100644 src/superio/winbond/w83697hf/early_serial.c delete mode 100644 src/superio/winbond/w83697hf/w83697hf_early_serial.c create mode 100644 src/superio/winbond/w83977f/early_serial.c delete mode 100644 src/superio/winbond/w83977f/w83977f_early_serial.c create mode 100644 src/superio/winbond/w83977tf/early_serial.c delete mode 100644 src/superio/winbond/w83977tf/w83977tf_early_serial.c (limited to 'src/superio') diff --git a/src/superio/fintek/f71805f/early_serial.c b/src/superio/fintek/f71805f/early_serial.c new file mode 100644 index 0000000000..dd82e8352b --- /dev/null +++ b/src/superio/fintek/f71805f/early_serial.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Corey Osgood + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for the Fintek F71805F/FG Super I/O chip. */ + +#include +#include "f71805f.h" + +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +static void f71805f_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/fintek/f71805f/f71805f_early_serial.c b/src/superio/fintek/f71805f/f71805f_early_serial.c deleted file mode 100644 index dd82e8352b..0000000000 --- a/src/superio/fintek/f71805f/f71805f_early_serial.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the Fintek F71805F/FG Super I/O chip. */ - -#include -#include "f71805f.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -static void f71805f_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/fintek/f71859/early_serial.c b/src/superio/fintek/f71859/early_serial.c new file mode 100755 index 0000000000..14d22a6310 --- /dev/null +++ b/src/superio/fintek/f71859/early_serial.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Marc Jones + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for the Fintek F71859 Super I/O chip. */ + +#include +#include "f71859.h" + +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +static void f71859_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/fintek/f71859/f71859_early_serial.c b/src/superio/fintek/f71859/f71859_early_serial.c deleted file mode 100755 index 14d22a6310..0000000000 --- a/src/superio/fintek/f71859/f71859_early_serial.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Marc Jones - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the Fintek F71859 Super I/O chip. */ - -#include -#include "f71859.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -static void f71859_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/fintek/f71863fg/early_serial.c b/src/superio/fintek/f71863fg/early_serial.c new file mode 100644 index 0000000000..d410ef6031 --- /dev/null +++ b/src/superio/fintek/f71863fg/early_serial.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Corey Osgood + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for the Fintek F71863FG Super I/O chip. */ + +#include +#include "f71863fg.h" + +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +static void f71863fg_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/fintek/f71863fg/f71863fg_early_serial.c b/src/superio/fintek/f71863fg/f71863fg_early_serial.c deleted file mode 100644 index d410ef6031..0000000000 --- a/src/superio/fintek/f71863fg/f71863fg_early_serial.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the Fintek F71863FG Super I/O chip. */ - -#include -#include "f71863fg.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -static void f71863fg_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/fintek/f71872/early_serial.c b/src/superio/fintek/f71872/early_serial.c new file mode 100644 index 0000000000..474917a400 --- /dev/null +++ b/src/superio/fintek/f71872/early_serial.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Corey Osgood + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for the Fintek F71872F/FG Super I/O chip. */ + +#include +#include "f71872.h" + +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +static void f71872_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/fintek/f71872/f71872_early_serial.c b/src/superio/fintek/f71872/f71872_early_serial.c deleted file mode 100644 index 474917a400..0000000000 --- a/src/superio/fintek/f71872/f71872_early_serial.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the Fintek F71872F/FG Super I/O chip. */ - -#include -#include "f71872.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -static void f71872_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/fintek/f71889/early_serial.c b/src/superio/fintek/f71889/early_serial.c new file mode 100644 index 0000000000..29042ae817 --- /dev/null +++ b/src/superio/fintek/f71889/early_serial.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Alec Ari + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include "f71889.h" + +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +static void f71889_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/fintek/f71889/f71889_early_serial.c b/src/superio/fintek/f71889/f71889_early_serial.c deleted file mode 100644 index 29042ae817..0000000000 --- a/src/superio/fintek/f71889/f71889_early_serial.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Alec Ari - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include "f71889.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -static void f71889_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/intel/i3100/early_serial.c b/src/superio/intel/i3100/early_serial.c new file mode 100644 index 0000000000..23f8cab5ab --- /dev/null +++ b/src/superio/intel/i3100/early_serial.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Arastra, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "i3100.h" + +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + + outb(0x80, port); + outb(0x86, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + + outb(0x68, port); + outb(0x08, port); +} + +/* Enable device interrupts, set UART_CLK predivide. */ +static void i3100_configure_uart_clk(device_t dev, u8 predivide) +{ + pnp_enter_ext_func_mode(dev); + pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1); + pnp_exit_ext_func_mode(dev); +} + +static void i3100_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); +} diff --git a/src/superio/intel/i3100/i3100_early_serial.c b/src/superio/intel/i3100/i3100_early_serial.c deleted file mode 100644 index 23f8cab5ab..0000000000 --- a/src/superio/intel/i3100/i3100_early_serial.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "i3100.h" - -static void pnp_enter_ext_func_mode(device_t dev) -{ - u16 port = dev >> 8; - - outb(0x80, port); - outb(0x86, port); -} - -static void pnp_exit_ext_func_mode(device_t dev) -{ - u16 port = dev >> 8; - - outb(0x68, port); - outb(0x08, port); -} - -/* Enable device interrupts, set UART_CLK predivide. */ -static void i3100_configure_uart_clk(device_t dev, u8 predivide) -{ - pnp_enter_ext_func_mode(dev); - pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1); - pnp_exit_ext_func_mode(dev); -} - -static void i3100_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} diff --git a/src/superio/ite/it8661f/early_serial.c b/src/superio/ite/it8661f/early_serial.c new file mode 100644 index 0000000000..c3edddcf4b --- /dev/null +++ b/src/superio/ite/it8661f/early_serial.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "it8661f.h" + +/* Perform MB PnP setup to put the SIO chip at 0x3f0. */ +/* Base address 0x3f0: 0x86 0x80 0x55 0x55. */ +/* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */ +/* Base address 0x370: 0x86 0x80 0xaa 0x55. */ +static void pnp_enter_ext_func_mode(device_t dev) +{ + int i; + u16 port = dev >> 8; + + /* TODO: Don't hardcode Super I/O config port to 0x3f0. */ + outb(0x86, IT8661F_ISA_PNP_PORT); + outb(0x80, IT8661F_ISA_PNP_PORT); + outb(0x55, IT8661F_ISA_PNP_PORT); + outb(0x55, IT8661F_ISA_PNP_PORT); + + /* Sequentially write the 32 special values. */ + for (i = 0; i < 32; i++) + outb(init_values[i], port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + pnp_write_config(dev, IT8661F_REG_CC, (1 << 1)); +} + +/* + * The logical devices will only be involved in the ISA PnP sequence if their + * respective enable bits in IT8661F_REG_LDE are set. + * + * TODO: Find out if we actually need this (we use MB PnP mode). + * + * Bits: FDC (0), Com1 (1), Com2 (2), PP (3), IR (4). Bits 5-7 are reserved. + */ +static void it8661f_enable_logical_devices(device_t dev) +{ + pnp_enter_ext_func_mode(dev); + pnp_write_config(dev, IT8661F_REG_LDE, 0x1f); + pnp_exit_ext_func_mode(dev); +} + +static void it8661f_set_clkin(device_t dev, u8 clkin) +{ + pnp_enter_ext_func_mode(dev); + pnp_write_config(dev, IT8661F_REG_SWSUSP, (clkin << 1)); + pnp_exit_ext_func_mode(dev); +} + +static void it8661f_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); +} diff --git a/src/superio/ite/it8661f/it8661f_early_serial.c b/src/superio/ite/it8661f/it8661f_early_serial.c deleted file mode 100644 index c3edddcf4b..0000000000 --- a/src/superio/ite/it8661f/it8661f_early_serial.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "it8661f.h" - -/* Perform MB PnP setup to put the SIO chip at 0x3f0. */ -/* Base address 0x3f0: 0x86 0x80 0x55 0x55. */ -/* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */ -/* Base address 0x370: 0x86 0x80 0xaa 0x55. */ -static void pnp_enter_ext_func_mode(device_t dev) -{ - int i; - u16 port = dev >> 8; - - /* TODO: Don't hardcode Super I/O config port to 0x3f0. */ - outb(0x86, IT8661F_ISA_PNP_PORT); - outb(0x80, IT8661F_ISA_PNP_PORT); - outb(0x55, IT8661F_ISA_PNP_PORT); - outb(0x55, IT8661F_ISA_PNP_PORT); - - /* Sequentially write the 32 special values. */ - for (i = 0; i < 32; i++) - outb(init_values[i], port); -} - -static void pnp_exit_ext_func_mode(device_t dev) -{ - pnp_write_config(dev, IT8661F_REG_CC, (1 << 1)); -} - -/* - * The logical devices will only be involved in the ISA PnP sequence if their - * respective enable bits in IT8661F_REG_LDE are set. - * - * TODO: Find out if we actually need this (we use MB PnP mode). - * - * Bits: FDC (0), Com1 (1), Com2 (2), PP (3), IR (4). Bits 5-7 are reserved. - */ -static void it8661f_enable_logical_devices(device_t dev) -{ - pnp_enter_ext_func_mode(dev); - pnp_write_config(dev, IT8661F_REG_LDE, 0x1f); - pnp_exit_ext_func_mode(dev); -} - -static void it8661f_set_clkin(device_t dev, u8 clkin) -{ - pnp_enter_ext_func_mode(dev); - pnp_write_config(dev, IT8661F_REG_SWSUSP, (clkin << 1)); - pnp_exit_ext_func_mode(dev); -} - -static void it8661f_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} diff --git a/src/superio/ite/it8671f/early_serial.c b/src/superio/ite/it8671f/early_serial.c new file mode 100644 index 0000000000..68062ec813 --- /dev/null +++ b/src/superio/ite/it8671f/early_serial.c @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "it8671f.h" + +/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */ +#define SIO_BASE 0x3f0 +#define SIO_INDEX SIO_BASE +#define SIO_DATA (SIO_BASE + 1) + +/* Global configuration registers. */ +#define IT8671F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define IT8671F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define IT8671F_CONFIG_REG_LDE 0x23 /* PnP Logical Device Enable. */ +#define IT8671F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend. */ + +#define IT8671F_CONFIGURATION_PORT 0x0279 /* Write-only. */ + +/* + * Special values used for entering MB PnP mode. The first four bytes of + * each line determine the address port, the last four are data. + */ +static const u8 init_values[] = { + 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe, + 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61, + 0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1, + 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39, +}; + +static void it8671f_sio_write(u8 ldn, u8 index, u8 value) +{ + outb(IT8671F_CONFIG_REG_LDN, SIO_BASE); + outb(ldn, SIO_DATA); + outb(index, SIO_BASE); + outb(value, SIO_DATA); +} + +/* Enter the configuration state (MB PnP mode). */ +static void it8671f_enter_conf(void) +{ + int i; + + /* Perform MB PnP setup to put the SIO chip at 0x3f0. */ + /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */ + /* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */ + /* Base address 0x370: 0x86 0x80 0xaa 0x55. */ + outb(0x86, IT8671F_CONFIGURATION_PORT); + outb(0x80, IT8671F_CONFIGURATION_PORT); + outb(0x55, IT8671F_CONFIGURATION_PORT); + outb(0x55, IT8671F_CONFIGURATION_PORT); + + /* Sequentially write the 32 special values. */ + for (i = 0; i < 32; i++) + outb(init_values[i], SIO_BASE); +} + +/* Exit the configuration state (MB PnP mode). */ +static void it8671f_exit_conf(void) +{ + it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02); +} + +/* Select 48MHz CLKIN (24MHz is the default). */ +void it8671f_48mhz_clkin(void) +{ + it8671f_enter_conf(); + it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, (1 << 6)); + it8671f_exit_conf(); +} + +/* Enable the serial port(s). */ +static void it8671f_enable_serial(device_t dev, u16 iobase) +{ + it8671f_enter_conf(); + + /* + * Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2), + * PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7). + */ + it8671f_sio_write(0x00, IT8671F_CONFIG_REG_LDE, 0x6f); + + /* Enable serial port(s). */ + it8671f_sio_write(IT8671F_SP1, 0x30, 0x01); /* Serial port 1 */ + it8671f_sio_write(IT8671F_SP2, 0x30, 0x01); /* Serial port 2 */ + + it8671f_exit_conf(); +} diff --git a/src/superio/ite/it8671f/it8671f_early_serial.c b/src/superio/ite/it8671f/it8671f_early_serial.c deleted file mode 100644 index 68062ec813..0000000000 --- a/src/superio/ite/it8671f/it8671f_early_serial.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "it8671f.h" - -/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */ -#define SIO_BASE 0x3f0 -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - -/* Global configuration registers. */ -#define IT8671F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8671F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define IT8671F_CONFIG_REG_LDE 0x23 /* PnP Logical Device Enable. */ -#define IT8671F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend. */ - -#define IT8671F_CONFIGURATION_PORT 0x0279 /* Write-only. */ - -/* - * Special values used for entering MB PnP mode. The first four bytes of - * each line determine the address port, the last four are data. - */ -static const u8 init_values[] = { - 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe, - 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61, - 0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1, - 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39, -}; - -static void it8671f_sio_write(u8 ldn, u8 index, u8 value) -{ - outb(IT8671F_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); -} - -/* Enter the configuration state (MB PnP mode). */ -static void it8671f_enter_conf(void) -{ - int i; - - /* Perform MB PnP setup to put the SIO chip at 0x3f0. */ - /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */ - /* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */ - /* Base address 0x370: 0x86 0x80 0xaa 0x55. */ - outb(0x86, IT8671F_CONFIGURATION_PORT); - outb(0x80, IT8671F_CONFIGURATION_PORT); - outb(0x55, IT8671F_CONFIGURATION_PORT); - outb(0x55, IT8671F_CONFIGURATION_PORT); - - /* Sequentially write the 32 special values. */ - for (i = 0; i < 32; i++) - outb(init_values[i], SIO_BASE); -} - -/* Exit the configuration state (MB PnP mode). */ -static void it8671f_exit_conf(void) -{ - it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02); -} - -/* Select 48MHz CLKIN (24MHz is the default). */ -void it8671f_48mhz_clkin(void) -{ - it8671f_enter_conf(); - it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, (1 << 6)); - it8671f_exit_conf(); -} - -/* Enable the serial port(s). */ -static void it8671f_enable_serial(device_t dev, u16 iobase) -{ - it8671f_enter_conf(); - - /* - * Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2), - * PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7). - */ - it8671f_sio_write(0x00, IT8671F_CONFIG_REG_LDE, 0x6f); - - /* Enable serial port(s). */ - it8671f_sio_write(IT8671F_SP1, 0x30, 0x01); /* Serial port 1 */ - it8671f_sio_write(IT8671F_SP2, 0x30, 0x01); /* Serial port 2 */ - - it8671f_exit_conf(); -} diff --git a/src/superio/ite/it8673f/early_serial.c b/src/superio/ite/it8673f/early_serial.c new file mode 100644 index 0000000000..37d4c74f1d --- /dev/null +++ b/src/superio/ite/it8673f/early_serial.c @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "it8673f.h" + +/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */ +#define SIO_BASE 0x3f0 +#define SIO_INDEX SIO_BASE +#define SIO_DATA (SIO_BASE + 1) + +/* Global configuration registers. */ +#define IT8673F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define IT8673F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define IT8673F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ +#define IT8673F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend. */ + +#define IT8673F_CONFIGURATION_PORT 0x0279 /* Write-only. */ + +/* + * Special values used for entering MB PnP mode. The first four bytes of + * each line determine the address port, the last four are data. + */ +static const u8 init_values[] = { + 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe, + 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61, + 0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1, + 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39, +}; + +static void it8673f_sio_write(u8 ldn, u8 index, u8 value) +{ + outb(IT8673F_CONFIG_REG_LDN, SIO_BASE); + outb(ldn, SIO_DATA); + outb(index, SIO_BASE); + outb(value, SIO_DATA); +} + +/* Enable the serial port(s). */ +static void it8673f_enable_serial(device_t dev, u16 iobase) +{ + int i; + + /* (1) Enter the configuration state (MB PnP mode). */ + + /* Perform MB PnP setup to put the SIO chip at 0x3f0. */ + /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */ + /* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */ + /* Base address 0x370: 0x86 0x80 0xaa 0x55. */ + outb(0x86, IT8673F_CONFIGURATION_PORT); + outb(0x80, IT8673F_CONFIGURATION_PORT); + outb(0x55, IT8673F_CONFIGURATION_PORT); + outb(0x55, IT8673F_CONFIGURATION_PORT); + + /* Sequentially write the 32 special values. */ + for (i = 0; i < 32; i++) + outb(init_values[i], SIO_BASE); + + /* (2) Modify the data of configuration registers. */ + + /* Enable all devices. */ + it8673f_sio_write(IT8673F_SP1, 0x30, 0x1); /* Serial port 1 */ + it8673f_sio_write(IT8673F_SP2, 0x30, 0x1); /* Serial port 2 */ + + /* Select 24MHz CLKIN (clear bit 0). */ + it8673f_sio_write(0x00, IT8673F_CONFIG_REG_CLOCKSEL, 0x00); + + /* Clear software suspend mode (clear bit 0). */ + it8673f_sio_write(0x00, IT8673F_CONFIG_REG_SWSUSP, 0x00); + + /* (3) Exit the configuration state (MB PnP mode). */ + it8673f_sio_write(0x00, IT8673F_CONFIG_REG_CC, 0x02); +} diff --git a/src/superio/ite/it8673f/it8673f_early_serial.c b/src/superio/ite/it8673f/it8673f_early_serial.c deleted file mode 100644 index 37d4c74f1d..0000000000 --- a/src/superio/ite/it8673f/it8673f_early_serial.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "it8673f.h" - -/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */ -#define SIO_BASE 0x3f0 -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - -/* Global configuration registers. */ -#define IT8673F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8673F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define IT8673F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ -#define IT8673F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend. */ - -#define IT8673F_CONFIGURATION_PORT 0x0279 /* Write-only. */ - -/* - * Special values used for entering MB PnP mode. The first four bytes of - * each line determine the address port, the last four are data. - */ -static const u8 init_values[] = { - 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe, - 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61, - 0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1, - 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39, -}; - -static void it8673f_sio_write(u8 ldn, u8 index, u8 value) -{ - outb(IT8673F_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); -} - -/* Enable the serial port(s). */ -static void it8673f_enable_serial(device_t dev, u16 iobase) -{ - int i; - - /* (1) Enter the configuration state (MB PnP mode). */ - - /* Perform MB PnP setup to put the SIO chip at 0x3f0. */ - /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */ - /* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */ - /* Base address 0x370: 0x86 0x80 0xaa 0x55. */ - outb(0x86, IT8673F_CONFIGURATION_PORT); - outb(0x80, IT8673F_CONFIGURATION_PORT); - outb(0x55, IT8673F_CONFIGURATION_PORT); - outb(0x55, IT8673F_CONFIGURATION_PORT); - - /* Sequentially write the 32 special values. */ - for (i = 0; i < 32; i++) - outb(init_values[i], SIO_BASE); - - /* (2) Modify the data of configuration registers. */ - - /* Enable all devices. */ - it8673f_sio_write(IT8673F_SP1, 0x30, 0x1); /* Serial port 1 */ - it8673f_sio_write(IT8673F_SP2, 0x30, 0x1); /* Serial port 2 */ - - /* Select 24MHz CLKIN (clear bit 0). */ - it8673f_sio_write(0x00, IT8673F_CONFIG_REG_CLOCKSEL, 0x00); - - /* Clear software suspend mode (clear bit 0). */ - it8673f_sio_write(0x00, IT8673F_CONFIG_REG_SWSUSP, 0x00); - - /* (3) Exit the configuration state (MB PnP mode). */ - it8673f_sio_write(0x00, IT8673F_CONFIG_REG_CC, 0x02); -} diff --git a/src/superio/ite/it8705f/early_serial.c b/src/superio/ite/it8705f/early_serial.c new file mode 100644 index 0000000000..7971582f9d --- /dev/null +++ b/src/superio/ite/it8705f/early_serial.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "it8705f.h" + +/* The base address is 0x2e or 0x4e, depending on config bytes. */ +#define SIO_BASE 0x2e +#define SIO_INDEX SIO_BASE +#define SIO_DATA (SIO_BASE + 1) + +/* Global configuration registers. */ +#define IT8705F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define IT8705F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define IT8705F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ + +/* WTF? 0x23 and 0x24 are swapped here (when compared to other IT87xx). */ +#define IT8705F_CONFIG_REG_CLOCKSEL 0x24 /* Clock Selection, Flash I/F. */ +#define IT8705F_CONFIG_REG_SWSUSP 0x23 /* Software Suspend. */ + +#define IT8705F_CONFIGURATION_PORT 0x2e /* Write-only. */ + +static void it8705f_sio_write(u8 ldn, u8 index, u8 value) +{ + outb(IT8705F_CONFIG_REG_LDN, SIO_BASE); + outb(ldn, SIO_DATA); + outb(index, SIO_BASE); + outb(value, SIO_DATA); +} + +/* Enable the serial port(s). */ +static void it8705f_enable_serial(device_t dev, u16 iobase) +{ + /* (1) Enter the configuration state (MB PnP mode). */ + + /* Perform MB PnP setup to put the SIO chip at 0x2e. */ + /* Base address 0x2e: 0x87 0x01 0x55 0x55. */ + /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ + outb(0x87, IT8705F_CONFIGURATION_PORT); + outb(0x01, IT8705F_CONFIGURATION_PORT); + outb(0x55, IT8705F_CONFIGURATION_PORT); + outb(0x55, IT8705F_CONFIGURATION_PORT); + + /* (2) Modify the data of configuration registers. */ + + /* + * Select the chip to configure (if there's more than one). + * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. + * If this register is not written, both chips are configured. + */ + /* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CONFIGSEL, 0x00); */ + + /* Enable serial port(s). */ + it8705f_sio_write(IT8705F_SP1, 0x30, 0x1); /* Serial port 1 */ + it8705f_sio_write(IT8705F_SP2, 0x30, 0x1); /* Serial port 2 */ + + /* Select 24MHz CLKIN (set bit 0). */ + it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CLOCKSEL, 0x01); + + /* Clear software suspend mode (clear bit 0). TODO: Needed? */ + /* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_SWSUSP, 0x00); */ + + /* (3) Exit the configuration state (MB PnP mode). */ + it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CC, 0x02); +} diff --git a/src/superio/ite/it8705f/it8705f_early_serial.c b/src/superio/ite/it8705f/it8705f_early_serial.c deleted file mode 100644 index 7971582f9d..0000000000 --- a/src/superio/ite/it8705f/it8705f_early_serial.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "it8705f.h" - -/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - -/* Global configuration registers. */ -#define IT8705F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8705F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define IT8705F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ - -/* WTF? 0x23 and 0x24 are swapped here (when compared to other IT87xx). */ -#define IT8705F_CONFIG_REG_CLOCKSEL 0x24 /* Clock Selection, Flash I/F. */ -#define IT8705F_CONFIG_REG_SWSUSP 0x23 /* Software Suspend. */ - -#define IT8705F_CONFIGURATION_PORT 0x2e /* Write-only. */ - -static void it8705f_sio_write(u8 ldn, u8 index, u8 value) -{ - outb(IT8705F_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); -} - -/* Enable the serial port(s). */ -static void it8705f_enable_serial(device_t dev, u16 iobase) -{ - /* (1) Enter the configuration state (MB PnP mode). */ - - /* Perform MB PnP setup to put the SIO chip at 0x2e. */ - /* Base address 0x2e: 0x87 0x01 0x55 0x55. */ - /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ - outb(0x87, IT8705F_CONFIGURATION_PORT); - outb(0x01, IT8705F_CONFIGURATION_PORT); - outb(0x55, IT8705F_CONFIGURATION_PORT); - outb(0x55, IT8705F_CONFIGURATION_PORT); - - /* (2) Modify the data of configuration registers. */ - - /* - * Select the chip to configure (if there's more than one). - * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. - * If this register is not written, both chips are configured. - */ - /* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CONFIGSEL, 0x00); */ - - /* Enable serial port(s). */ - it8705f_sio_write(IT8705F_SP1, 0x30, 0x1); /* Serial port 1 */ - it8705f_sio_write(IT8705F_SP2, 0x30, 0x1); /* Serial port 2 */ - - /* Select 24MHz CLKIN (set bit 0). */ - it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CLOCKSEL, 0x01); - - /* Clear software suspend mode (clear bit 0). TODO: Needed? */ - /* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_SWSUSP, 0x00); */ - - /* (3) Exit the configuration state (MB PnP mode). */ - it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CC, 0x02); -} diff --git a/src/superio/ite/it8712f/early_serial.c b/src/superio/ite/it8712f/early_serial.c new file mode 100644 index 0000000000..ebc8e0a7f1 --- /dev/null +++ b/src/superio/ite/it8712f/early_serial.c @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "it8712f.h" + +/* The base address is 0x2e or 0x4e, depending on config bytes. */ +#define SIO_BASE 0x2e +#define SIO_INDEX SIO_BASE +#define SIO_DATA (SIO_BASE + 1) + +/* Global configuration registers. */ +#define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ +#define IT8712F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ +#define IT8712F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ +#define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */ +#define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */ + +static void it8712f_sio_write(u8 ldn, u8 index, u8 value) +{ + outb(IT8712F_CONFIG_REG_LDN, SIO_BASE); + outb(ldn, SIO_DATA); + outb(index, SIO_BASE); + outb(value, SIO_DATA); +} + +static void it8712f_enter_conf(void) +{ + u16 port = 0x2e; /* TODO: Don't hardcode! */ + + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); +} + +static void it8712f_exit_conf(void) +{ + it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); +} + +/* Select 24MHz CLKIN (48MHz is the default). */ +void it8712f_24mhz_clkin(void) +{ + it8712f_enter_conf(); + it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x1); + it8712f_exit_conf(); +} + +/* + * We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2! + * + * LDN 7, reg 0x2a - needed for S3, or memory power will be cut off. + * + * Enable 3VSBSW#. (For System Suspend-to-RAM) + * 0: 3VSBSW# will be always inactive. + * 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#. + */ +void it8712f_enable_3vsbsw(void) +{ + it8712f_enter_conf(); + it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_MFC, 0x80); + it8712f_exit_conf(); +} + +void it8712f_kill_watchdog(void) +{ + it8712f_enter_conf(); + it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_WATCHDOG, 0x00); + it8712f_exit_conf(); +} + +/* Enable the serial port(s). */ +void it8712f_enable_serial(device_t dev, u16 iobase) +{ + /* (1) Enter the configuration state (MB PnP mode). */ + it8712f_enter_conf(); + + /* (2) Modify the data of configuration registers. */ + + /* + * Select the chip to configure (if there's more than one). + * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. + * If this register is not written, both chips are configured. + */ + + /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CONFIGSEL, 0x00); */ + + /* Enable serial port(s). */ + it8712f_sio_write(IT8712F_SP1, 0x30, 0x1); /* Serial port 1 */ + it8712f_sio_write(IT8712F_SP2, 0x30, 0x1); /* Serial port 2 */ + + /* Clear software suspend mode (clear bit 0). TODO: Needed? */ + /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_SWSUSP, 0x00); */ + + /* (3) Exit the configuration state (MB PnP mode). */ + it8712f_exit_conf(); +} diff --git a/src/superio/ite/it8712f/it8712f_early_serial.c b/src/superio/ite/it8712f/it8712f_early_serial.c deleted file mode 100644 index ebc8e0a7f1..0000000000 --- a/src/superio/ite/it8712f/it8712f_early_serial.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "it8712f.h" - -/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - -/* Global configuration registers. */ -#define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ -#define IT8712F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ -#define IT8712F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ -#define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */ -#define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */ - -static void it8712f_sio_write(u8 ldn, u8 index, u8 value) -{ - outb(IT8712F_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); -} - -static void it8712f_enter_conf(void) -{ - u16 port = 0x2e; /* TODO: Don't hardcode! */ - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} - -static void it8712f_exit_conf(void) -{ - it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); -} - -/* Select 24MHz CLKIN (48MHz is the default). */ -void it8712f_24mhz_clkin(void) -{ - it8712f_enter_conf(); - it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x1); - it8712f_exit_conf(); -} - -/* - * We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2! - * - * LDN 7, reg 0x2a - needed for S3, or memory power will be cut off. - * - * Enable 3VSBSW#. (For System Suspend-to-RAM) - * 0: 3VSBSW# will be always inactive. - * 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#. - */ -void it8712f_enable_3vsbsw(void) -{ - it8712f_enter_conf(); - it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_MFC, 0x80); - it8712f_exit_conf(); -} - -void it8712f_kill_watchdog(void) -{ - it8712f_enter_conf(); - it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_WATCHDOG, 0x00); - it8712f_exit_conf(); -} - -/* Enable the serial port(s). */ -void it8712f_enable_serial(device_t dev, u16 iobase) -{ - /* (1) Enter the configuration state (MB PnP mode). */ - it8712f_enter_conf(); - - /* (2) Modify the data of configuration registers. */ - - /* - * Select the chip to configure (if there's more than one). - * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. - * If this register is not written, both chips are configured. - */ - - /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CONFIGSEL, 0x00); */ - - /* Enable serial port(s). */ - it8712f_sio_write(IT8712F_SP1, 0x30, 0x1); /* Serial port 1 */ - it8712f_sio_write(IT8712F_SP2, 0x30, 0x1); /* Serial port 2 */ - - /* Clear software suspend mode (clear bit 0). TODO: Needed? */ - /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_SWSUSP, 0x00); */ - - /* (3) Exit the configuration state (MB PnP mode). */ - it8712f_exit_conf(); -} diff --git a/src/superio/ite/it8716f/early_init.c b/src/superio/ite/it8716f/early_init.c new file mode 100644 index 0000000000..5023dd865b --- /dev/null +++ b/src/superio/ite/it8716f/early_init.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "it8716f.h" + +void it8716f_disable_dev(device_t dev) +{ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); +} + +void it8716f_enable_dev(device_t dev, u16 iobase) +{ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); +} diff --git a/src/superio/ite/it8716f/early_serial.c b/src/superio/ite/it8716f/early_serial.c new file mode 100644 index 0000000000..747ca3074e --- /dev/null +++ b/src/superio/ite/it8716f/early_serial.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "it8716f.h" + +/* The base address is 0x2e or 0x4e, depending on config bytes. */ +#define SIO_BASE 0x2e +#define SIO_INDEX SIO_BASE +#define SIO_DATA (SIO_BASE + 1) + +/* Global configuration registers. */ +#define IT8716F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define IT8716F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define IT8716F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ +#define IT8716F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ +#define IT8716F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ + +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + pnp_write_config(dev, IT8716F_CONFIG_REG_CC, 0x02); +} + +void it8716f_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); +} diff --git a/src/superio/ite/it8716f/it8716f_early_init.c b/src/superio/ite/it8716f/it8716f_early_init.c deleted file mode 100644 index 5023dd865b..0000000000 --- a/src/superio/ite/it8716f/it8716f_early_init.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "it8716f.h" - -void it8716f_disable_dev(device_t dev) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); -} - -void it8716f_enable_dev(device_t dev, u16 iobase) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); -} diff --git a/src/superio/ite/it8716f/it8716f_early_serial.c b/src/superio/ite/it8716f/it8716f_early_serial.c deleted file mode 100644 index 747ca3074e..0000000000 --- a/src/superio/ite/it8716f/it8716f_early_serial.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "it8716f.h" - -/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - -/* Global configuration registers. */ -#define IT8716F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8716F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define IT8716F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ -#define IT8716F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ -#define IT8716F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ - -static void pnp_enter_ext_func_mode(device_t dev) -{ - u16 port = dev >> 8; - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} - -static void pnp_exit_ext_func_mode(device_t dev) -{ - pnp_write_config(dev, IT8716F_CONFIG_REG_CC, 0x02); -} - -void it8716f_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} diff --git a/src/superio/ite/it8718f/early_serial.c b/src/superio/ite/it8718f/early_serial.c new file mode 100644 index 0000000000..76f9b0daf6 --- /dev/null +++ b/src/superio/ite/it8718f/early_serial.c @@ -0,0 +1,104 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "it8718f.h" + +/* The base address is 0x2e or 0x4e, depending on config bytes. */ +#define SIO_BASE 0x2e +#define SIO_INDEX SIO_BASE +#define SIO_DATA (SIO_BASE + 1) + +/* Global configuration registers. */ +#define IT8718F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define IT8718F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define IT8718F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ +#define IT8718F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ +#define IT8718F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ + +static void it8718f_sio_write(u8 ldn, u8 index, u8 value) +{ + outb(IT8718F_CONFIG_REG_LDN, SIO_BASE); + outb(ldn, SIO_DATA); + outb(index, SIO_BASE); + outb(value, SIO_DATA); +} + +static void it8718f_enter_conf(void) +{ + u16 port = 0x2e; /* TODO: Don't hardcode! */ + + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); +} + +static void it8718f_exit_conf(void) +{ + it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02); +} + +/* Select 24MHz CLKIN (48MHz default). */ +void it8718f_24mhz_clkin(void) +{ + it8718f_enter_conf(); + it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x1); + it8718f_exit_conf(); +} + +/* + * GIGABYTE uses a special Super I/O register to protect its Dual BIOS + * mechanism. It lives in the GPIO LDN. However, register 0xEF is not + * mentioned in the IT8718F datasheet so just hardcode it to 0x7E for now. + */ +void it8718f_disable_reboot(void) +{ + it8718f_enter_conf(); + it8718f_sio_write(IT8718F_GPIO, 0xEF, 0x7E); + it8718f_exit_conf(); +} + +/* Enable the serial port(s). */ +void it8718f_enable_serial(device_t dev, u16 iobase) +{ + /* (1) Enter the configuration state (MB PnP mode). */ + it8718f_enter_conf(); + + /* (2) Modify the data of configuration registers. */ + + /* + * Select the chip to configure (if there's more than one). + * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. + * If this register is not written, both chips are configured. + */ + + /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */ + + /* Enable serial port(s). */ + it8718f_sio_write(IT8718F_SP1, 0x30, 0x1); /* Serial port 1 */ + it8718f_sio_write(IT8718F_SP2, 0x30, 0x1); /* Serial port 2 */ + + /* Clear software suspend mode (clear bit 0). TODO: Needed? */ + /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */ + + /* (3) Exit the configuration state (MB PnP mode). */ + it8718f_exit_conf(); +} diff --git a/src/superio/ite/it8718f/it8718f_early_serial.c b/src/superio/ite/it8718f/it8718f_early_serial.c deleted file mode 100644 index 76f9b0daf6..0000000000 --- a/src/superio/ite/it8718f/it8718f_early_serial.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "it8718f.h" - -/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - -/* Global configuration registers. */ -#define IT8718F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8718F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define IT8718F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ -#define IT8718F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ -#define IT8718F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ - -static void it8718f_sio_write(u8 ldn, u8 index, u8 value) -{ - outb(IT8718F_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); -} - -static void it8718f_enter_conf(void) -{ - u16 port = 0x2e; /* TODO: Don't hardcode! */ - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} - -static void it8718f_exit_conf(void) -{ - it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02); -} - -/* Select 24MHz CLKIN (48MHz default). */ -void it8718f_24mhz_clkin(void) -{ - it8718f_enter_conf(); - it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x1); - it8718f_exit_conf(); -} - -/* - * GIGABYTE uses a special Super I/O register to protect its Dual BIOS - * mechanism. It lives in the GPIO LDN. However, register 0xEF is not - * mentioned in the IT8718F datasheet so just hardcode it to 0x7E for now. - */ -void it8718f_disable_reboot(void) -{ - it8718f_enter_conf(); - it8718f_sio_write(IT8718F_GPIO, 0xEF, 0x7E); - it8718f_exit_conf(); -} - -/* Enable the serial port(s). */ -void it8718f_enable_serial(device_t dev, u16 iobase) -{ - /* (1) Enter the configuration state (MB PnP mode). */ - it8718f_enter_conf(); - - /* (2) Modify the data of configuration registers. */ - - /* - * Select the chip to configure (if there's more than one). - * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. - * If this register is not written, both chips are configured. - */ - - /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */ - - /* Enable serial port(s). */ - it8718f_sio_write(IT8718F_SP1, 0x30, 0x1); /* Serial port 1 */ - it8718f_sio_write(IT8718F_SP2, 0x30, 0x1); /* Serial port 2 */ - - /* Clear software suspend mode (clear bit 0). TODO: Needed? */ - /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */ - - /* (3) Exit the configuration state (MB PnP mode). */ - it8718f_exit_conf(); -} diff --git a/src/superio/nsc/pc8374/early_init.c b/src/superio/nsc/pc8374/early_init.c new file mode 100644 index 0000000000..29b57e43a9 --- /dev/null +++ b/src/superio/nsc/pc8374/early_init.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "pc8374.h" + +static void pc8374_enable(u16 iobase, u8 *init) +{ + u8 val, count; + + outb(0x29, iobase); + val = inb(iobase + 1); + val |= 0x91; + outb(val, iobase + 1); + + for (count = 0; count < 255; count++) + if (inb(iobase + 1) == 0x91) + break; + + for (; *init; init++) { + outb(*init, iobase); + val = inb(iobase + 1); + init++; + val &= *init; + init++; + val |= *init; + outb(val, iobase + 1); + } +} + +static void pc8374_enable_dev(device_t dev, u16 iobase) +{ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + if (iobase) + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); +} diff --git a/src/superio/nsc/pc8374/pc8374_early_init.c b/src/superio/nsc/pc8374/pc8374_early_init.c deleted file mode 100644 index 29b57e43a9..0000000000 --- a/src/superio/nsc/pc8374/pc8374_early_init.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "pc8374.h" - -static void pc8374_enable(u16 iobase, u8 *init) -{ - u8 val, count; - - outb(0x29, iobase); - val = inb(iobase + 1); - val |= 0x91; - outb(val, iobase + 1); - - for (count = 0; count < 255; count++) - if (inb(iobase + 1) == 0x91) - break; - - for (; *init; init++) { - outb(*init, iobase); - val = inb(iobase + 1); - init++; - val &= *init; - init++; - val |= *init; - outb(val, iobase + 1); - } -} - -static void pc8374_enable_dev(device_t dev, u16 iobase) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - if (iobase) - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); -} diff --git a/src/superio/nsc/pc87309/early_serial.c b/src/superio/nsc/pc87309/early_serial.c new file mode 100644 index 0000000000..14c755d365 --- /dev/null +++ b/src/superio/nsc/pc87309/early_serial.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "pc87309.h" + +static void pc87309_enable_serial(device_t dev, u16 iobase) +{ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); +} diff --git a/src/superio/nsc/pc87309/pc87309_early_serial.c b/src/superio/nsc/pc87309/pc87309_early_serial.c deleted file mode 100644 index 14c755d365..0000000000 --- a/src/superio/nsc/pc87309/pc87309_early_serial.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "pc87309.h" - -static void pc87309_enable_serial(device_t dev, u16 iobase) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); -} diff --git a/src/superio/nsc/pc87351/early_serial.c b/src/superio/nsc/pc87351/early_serial.c new file mode 100644 index 0000000000..ef55e37d78 --- /dev/null +++ b/src/superio/nsc/pc87351/early_serial.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "pc87351.h" + +static void pc87351_enable_serial(device_t dev, u16 iobase) +{ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); +} diff --git a/src/superio/nsc/pc87351/pc87351_early_serial.c b/src/superio/nsc/pc87351/pc87351_early_serial.c deleted file mode 100644 index ef55e37d78..0000000000 --- a/src/superio/nsc/pc87351/pc87351_early_serial.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "pc87351.h" - -static void pc87351_enable_serial(device_t dev, u16 iobase) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); -} diff --git a/src/superio/nsc/pc87360/early_serial.c b/src/superio/nsc/pc87360/early_serial.c new file mode 100644 index 0000000000..6c468129a7 --- /dev/null +++ b/src/superio/nsc/pc87360/early_serial.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "pc87360.h" + +static void pc87360_enable_serial(device_t dev, u16 iobase) +{ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); +} diff --git a/src/superio/nsc/pc87360/pc87360_early_serial.c b/src/superio/nsc/pc87360/pc87360_early_serial.c deleted file mode 100644 index 6c468129a7..0000000000 --- a/src/superio/nsc/pc87360/pc87360_early_serial.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "pc87360.h" - -static void pc87360_enable_serial(device_t dev, u16 iobase) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); -} diff --git a/src/superio/nsc/pc87366/early_serial.c b/src/superio/nsc/pc87366/early_serial.c new file mode 100644 index 0000000000..4620d228b0 --- /dev/null +++ b/src/superio/nsc/pc87366/early_serial.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "pc87366.h" + +static void pc87366_enable_serial(device_t dev, u16 iobase) +{ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); +} diff --git a/src/superio/nsc/pc87366/pc87366_early_serial.c b/src/superio/nsc/pc87366/pc87366_early_serial.c deleted file mode 100644 index 4620d228b0..0000000000 --- a/src/superio/nsc/pc87366/pc87366_early_serial.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "pc87366.h" - -static void pc87366_enable_serial(device_t dev, u16 iobase) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); -} diff --git a/src/superio/nsc/pc87417/early_init.c b/src/superio/nsc/pc87417/early_init.c new file mode 100644 index 0000000000..a635beb61d --- /dev/null +++ b/src/superio/nsc/pc87417/early_init.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "pc87417.h" + +static void pc87417_disable_dev(device_t dev) +{ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); +} + +static void pc87417_enable_dev(device_t dev, u16 iobase) +{ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); +} + +static void xbus_cfg(device_t dev) +{ + u8 i, data; + u16 xbus_index; + + pnp_set_logical_device(dev); + /* Select proper BIOS size (4MB). */ + pnp_write_config(dev, PC87417_XMEMCNF2, + (pnp_read_config(dev, PC87417_XMEMCNF2)) | 0x04); + xbus_index = pnp_read_iobase(dev, 0x60); + + /* Enable writes to devices attached to XCS0 (XBUS Chip Select 0). */ + for (i = 0; i <= 0xf; i++) + outb((i << 4), xbus_index + PC87417_HAP0); +} diff --git a/src/superio/nsc/pc87417/early_serial.c b/src/superio/nsc/pc87417/early_serial.c new file mode 100644 index 0000000000..c30d9487a8 --- /dev/null +++ b/src/superio/nsc/pc87417/early_serial.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "pc87417.h" + +void pc87417_enable_serial(device_t dev, u16 iobase) +{ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); +} + +void pc87417_enable_dev(device_t dev) +{ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); +} diff --git a/src/superio/nsc/pc87417/pc87417_early_init.c b/src/superio/nsc/pc87417/pc87417_early_init.c deleted file mode 100644 index a635beb61d..0000000000 --- a/src/superio/nsc/pc87417/pc87417_early_init.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "pc87417.h" - -static void pc87417_disable_dev(device_t dev) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); -} - -static void pc87417_enable_dev(device_t dev, u16 iobase) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); -} - -static void xbus_cfg(device_t dev) -{ - u8 i, data; - u16 xbus_index; - - pnp_set_logical_device(dev); - /* Select proper BIOS size (4MB). */ - pnp_write_config(dev, PC87417_XMEMCNF2, - (pnp_read_config(dev, PC87417_XMEMCNF2)) | 0x04); - xbus_index = pnp_read_iobase(dev, 0x60); - - /* Enable writes to devices attached to XCS0 (XBUS Chip Select 0). */ - for (i = 0; i <= 0xf; i++) - outb((i << 4), xbus_index + PC87417_HAP0); -} diff --git a/src/superio/nsc/pc87417/pc87417_early_serial.c b/src/superio/nsc/pc87417/pc87417_early_serial.c deleted file mode 100644 index c30d9487a8..0000000000 --- a/src/superio/nsc/pc87417/pc87417_early_serial.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "pc87417.h" - -void pc87417_enable_serial(device_t dev, u16 iobase) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); -} - -void pc87417_enable_dev(device_t dev) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 1); -} diff --git a/src/superio/nsc/pc87427/early_init.c b/src/superio/nsc/pc87427/early_init.c new file mode 100644 index 0000000000..8c1f47d161 --- /dev/null +++ b/src/superio/nsc/pc87427/early_init.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "pc87427.h" + +static void pc87427_disable_dev(device_t dev) +{ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); +} + +static void pc87427_enable_dev(device_t dev, u16 iobase) +{ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); +} + +static void xbus_cfg(device_t dev) +{ + u8 i, data; + u16 xbus_index; + + pnp_set_logical_device(dev); + + /* Select proper BIOS size (4MB). */ + pnp_write_config(dev, PC87427_XMEMCNF2, + (pnp_read_config(dev, PC87427_XMEMCNF2)) | 0x04); + xbus_index = pnp_read_iobase(dev, 0x60); + + /* Enable writes to devices attached to XCS0 (XBUS Chip Select 0). */ + for (i = 0; i <= 0xf; i++) + outb((i << 4), xbus_index + PC87427_HAP0); +} diff --git a/src/superio/nsc/pc87427/pc87427_early_init.c b/src/superio/nsc/pc87427/pc87427_early_init.c deleted file mode 100644 index 8c1f47d161..0000000000 --- a/src/superio/nsc/pc87427/pc87427_early_init.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "pc87427.h" - -static void pc87427_disable_dev(device_t dev) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); -} - -static void pc87427_enable_dev(device_t dev, u16 iobase) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); -} - -static void xbus_cfg(device_t dev) -{ - u8 i, data; - u16 xbus_index; - - pnp_set_logical_device(dev); - - /* Select proper BIOS size (4MB). */ - pnp_write_config(dev, PC87427_XMEMCNF2, - (pnp_read_config(dev, PC87427_XMEMCNF2)) | 0x04); - xbus_index = pnp_read_iobase(dev, 0x60); - - /* Enable writes to devices attached to XCS0 (XBUS Chip Select 0). */ - for (i = 0; i <= 0xf; i++) - outb((i << 4), xbus_index + PC87427_HAP0); -} diff --git a/src/superio/nsc/pc97317/early_serial.c b/src/superio/nsc/pc97317/early_serial.c new file mode 100644 index 0000000000..00a92b3be6 --- /dev/null +++ b/src/superio/nsc/pc97317/early_serial.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "pc97317.h" + +#define PM_DEV PNP_DEV(0x2e, PC97317_PM) +#define PM_BASE 0xe8 + +/* The PC97317 needs clocks to be set up before the serial port will operate. */ +static void pc97317_enable_serial(device_t dev, u16 iobase) +{ + /* Set base address of power management unit. */ + pnp_set_logical_device(PM_DEV); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, PM_BASE); + pnp_set_enable(dev, 1); + + /* Use on-chip clock multiplier. */ + outb(0x03, PM_BASE); + outb(inb(PM_BASE + 1) | 0x07, PM_BASE + 1); + + /* Wait for the clock to stabilise. */ + while(!(inb(PM_BASE + 1) & 0x80)) + ; + + /* Set the base address of the port. */ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); +} diff --git a/src/superio/nsc/pc97317/pc97317_early_serial.c b/src/superio/nsc/pc97317/pc97317_early_serial.c deleted file mode 100644 index 00a92b3be6..0000000000 --- a/src/superio/nsc/pc97317/pc97317_early_serial.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "pc97317.h" - -#define PM_DEV PNP_DEV(0x2e, PC97317_PM) -#define PM_BASE 0xe8 - -/* The PC97317 needs clocks to be set up before the serial port will operate. */ -static void pc97317_enable_serial(device_t dev, u16 iobase) -{ - /* Set base address of power management unit. */ - pnp_set_logical_device(PM_DEV); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, PM_BASE); - pnp_set_enable(dev, 1); - - /* Use on-chip clock multiplier. */ - outb(0x03, PM_BASE); - outb(inb(PM_BASE + 1) | 0x07, PM_BASE + 1); - - /* Wait for the clock to stabilise. */ - while(!(inb(PM_BASE + 1) & 0x80)) - ; - - /* Set the base address of the port. */ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); -} diff --git a/src/superio/serverengines/pilot/early_init.c b/src/superio/serverengines/pilot/early_init.c new file mode 100644 index 0000000000..e88c5d4198 --- /dev/null +++ b/src/superio/serverengines/pilot/early_init.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 University of Heidelberg + * Written by Mondrian Nuessle for Univ. Heidelberg + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* PILOT Super I/O is only based on LPC observation done on factory system. */ + +#define BLUBB_DEV PNP_DEV(port, 0x04) + +/* + * Logical device 4, 5 and 7 are being deactivated. Logical Device 1 seems to + * be another serial (?), it is also deactivated on the HP machine. + */ +static void pilot_early_init(device_t dev) +{ + u16 port = dev >> 8; + + print_debug("Using port: "); + print_debug_hex16(port); + print_debug("\n"); + pilot_disable_serial(PNP_DEV(port, 0x1)); + print_debug("disable serial 1\n"); + + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(PNP_DEV(port, 0x3)); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, 0x60, 0x0b00); + pnp_set_iobase(dev, 0x62, 0x0b80); + pnp_set_iobase(dev, 0x64, 0x0b84); + pnp_set_iobase(dev, 0x66, 0x0b86); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); + +/* + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(PNP_DEV(port, 0x3)); + pnp_exit_ext_func_mode(dev); + pnp_enter_ext_func_mode(dev); + pnp_set_enable(PNP_DEV(port, 0x3), 0); + pnp_exit_ext_func_mode(dev); +*/ + + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(PNP_DEV(port, 0x4)); + pnp_exit_ext_func_mode(dev); + pnp_enter_ext_func_mode(dev); + pnp_set_enable( PNP_DEV(port, 0x4), 0); + pnp_exit_ext_func_mode(dev); + + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(PNP_DEV(port, 0x5)); + pnp_exit_ext_func_mode(dev); + pnp_enter_ext_func_mode(dev); + pnp_set_enable(PNP_DEV(port, 0x5), 0); + pnp_exit_ext_func_mode(dev); + + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(PNP_DEV(port, 0x6)); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); + pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); + pnp_set_irq(dev, PNP_IDX_IRQ0, 1); + pnp_set_drq(dev, 0x71, 3); + pnp_set_enable(dev, 0); + pnp_exit_ext_func_mode(dev); + + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(PNP_DEV(port, 0xe)); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x70); + pnp_set_iobase(dev, PNP_IDX_IO1, 0x72); + pnp_set_irq(dev, PNP_IDX_IRQ0, 8); + pnp_set_drq(dev, 0x71, 3); + pnp_set_enable(dev, 0); + pnp_exit_ext_func_mode(dev); + + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(PNP_DEV(port, 0x7)); + pnp_exit_ext_func_mode(dev); + pnp_enter_ext_func_mode(dev); + pnp_set_enable(PNP_DEV(port, 0x7), 0); + pnp_exit_ext_func_mode(dev); + +/* + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(PNP_DEV(port, 0x8)); + pnp_exit_ext_func_mode(dev); + pnp_enter_ext_func_mode(dev); + pnp_set_enable(PNP_DEV(port, 0x8), 0); + pnp_exit_ext_func_mode(dev); + + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(PNP_DEV(port, 0x9)); + pnp_exit_ext_func_mode(dev); + pnp_enter_ext_func_mode(dev); + pnp_set_enable(PNP_DEV(port, 0x9), 0); + pnp_exit_ext_func_mode(dev); + + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(PNP_DEV(port, 0x10)); + pnp_exit_ext_func_mode(dev); + pnp_enter_ext_func_mode(dev); + pnp_set_enable(PNP_DEV(port, 0x10), 0); + pnp_exit_ext_func_mode(dev); +*/ +} diff --git a/src/superio/serverengines/pilot/early_serial.c b/src/superio/serverengines/pilot/early_serial.c new file mode 100644 index 0000000000..a2bbec481e --- /dev/null +++ b/src/superio/serverengines/pilot/early_serial.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 University of Heidelberg + * Written by Mondrian Nuessle for Univ. Heidelberg + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* PILOT Super I/O is only based on LPC observation done on factory system. */ + +#include +#include "pilot.h" + +/* Pilot uses 0x5A/0xA5 pattern to actiavte deactivate config access. */ +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x5A, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xA5, port); +} + +/* Serial config is a fairly standard procedure. */ +static void pilot_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); +} + +static void pilot_disable_serial(device_t dev) +{ + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x0000); + pnp_set_enable(dev, 0); + pnp_exit_ext_func_mode(dev); +} diff --git a/src/superio/serverengines/pilot/pilot_early_init.c b/src/superio/serverengines/pilot/pilot_early_init.c deleted file mode 100644 index e88c5d4198..0000000000 --- a/src/superio/serverengines/pilot/pilot_early_init.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 University of Heidelberg - * Written by Mondrian Nuessle for Univ. Heidelberg - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* PILOT Super I/O is only based on LPC observation done on factory system. */ - -#define BLUBB_DEV PNP_DEV(port, 0x04) - -/* - * Logical device 4, 5 and 7 are being deactivated. Logical Device 1 seems to - * be another serial (?), it is also deactivated on the HP machine. - */ -static void pilot_early_init(device_t dev) -{ - u16 port = dev >> 8; - - print_debug("Using port: "); - print_debug_hex16(port); - print_debug("\n"); - pilot_disable_serial(PNP_DEV(port, 0x1)); - print_debug("disable serial 1\n"); - - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(PNP_DEV(port, 0x3)); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, 0x60, 0x0b00); - pnp_set_iobase(dev, 0x62, 0x0b80); - pnp_set_iobase(dev, 0x64, 0x0b84); - pnp_set_iobase(dev, 0x66, 0x0b86); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); - -/* - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(PNP_DEV(port, 0x3)); - pnp_exit_ext_func_mode(dev); - pnp_enter_ext_func_mode(dev); - pnp_set_enable(PNP_DEV(port, 0x3), 0); - pnp_exit_ext_func_mode(dev); -*/ - - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(PNP_DEV(port, 0x4)); - pnp_exit_ext_func_mode(dev); - pnp_enter_ext_func_mode(dev); - pnp_set_enable( PNP_DEV(port, 0x4), 0); - pnp_exit_ext_func_mode(dev); - - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(PNP_DEV(port, 0x5)); - pnp_exit_ext_func_mode(dev); - pnp_enter_ext_func_mode(dev); - pnp_set_enable(PNP_DEV(port, 0x5), 0); - pnp_exit_ext_func_mode(dev); - - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(PNP_DEV(port, 0x6)); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); - pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); - pnp_set_irq(dev, PNP_IDX_IRQ0, 1); - pnp_set_drq(dev, 0x71, 3); - pnp_set_enable(dev, 0); - pnp_exit_ext_func_mode(dev); - - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(PNP_DEV(port, 0xe)); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x70); - pnp_set_iobase(dev, PNP_IDX_IO1, 0x72); - pnp_set_irq(dev, PNP_IDX_IRQ0, 8); - pnp_set_drq(dev, 0x71, 3); - pnp_set_enable(dev, 0); - pnp_exit_ext_func_mode(dev); - - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(PNP_DEV(port, 0x7)); - pnp_exit_ext_func_mode(dev); - pnp_enter_ext_func_mode(dev); - pnp_set_enable(PNP_DEV(port, 0x7), 0); - pnp_exit_ext_func_mode(dev); - -/* - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(PNP_DEV(port, 0x8)); - pnp_exit_ext_func_mode(dev); - pnp_enter_ext_func_mode(dev); - pnp_set_enable(PNP_DEV(port, 0x8), 0); - pnp_exit_ext_func_mode(dev); - - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(PNP_DEV(port, 0x9)); - pnp_exit_ext_func_mode(dev); - pnp_enter_ext_func_mode(dev); - pnp_set_enable(PNP_DEV(port, 0x9), 0); - pnp_exit_ext_func_mode(dev); - - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(PNP_DEV(port, 0x10)); - pnp_exit_ext_func_mode(dev); - pnp_enter_ext_func_mode(dev); - pnp_set_enable(PNP_DEV(port, 0x10), 0); - pnp_exit_ext_func_mode(dev); -*/ -} diff --git a/src/superio/serverengines/pilot/pilot_early_serial.c b/src/superio/serverengines/pilot/pilot_early_serial.c deleted file mode 100644 index a2bbec481e..0000000000 --- a/src/superio/serverengines/pilot/pilot_early_serial.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 University of Heidelberg - * Written by Mondrian Nuessle for Univ. Heidelberg - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* PILOT Super I/O is only based on LPC observation done on factory system. */ - -#include -#include "pilot.h" - -/* Pilot uses 0x5A/0xA5 pattern to actiavte deactivate config access. */ -static void pnp_enter_ext_func_mode(device_t dev) -{ - u16 port = dev >> 8; - outb(0x5A, port); -} - -static void pnp_exit_ext_func_mode(device_t dev) -{ - u16 port = dev >> 8; - outb(0xA5, port); -} - -/* Serial config is a fairly standard procedure. */ -static void pilot_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} - -static void pilot_disable_serial(device_t dev) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x0000); - pnp_set_enable(dev, 0); - pnp_exit_ext_func_mode(dev); -} diff --git a/src/superio/smsc/fdc37m60x/early_serial.c b/src/superio/smsc/fdc37m60x/early_serial.c new file mode 100644 index 0000000000..d8cd8c683d --- /dev/null +++ b/src/superio/smsc/fdc37m60x/early_serial.c @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "fdc37m60x.h" + +/* The base address is 0x3f0 or 0x370, depending on the SYSOPT pin. */ +#define SIO_BASE 0x3f0 +#define SIO_INDEX SIO_BASE +#define SIO_DATA (SIO_BASE + 1) + +/* Global configuration registers. */ +#define FDC37M60X_CONFIG_REG_CC 0x02 /* Configure Control. */ +#define FDC37M60X_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define FDC37M60X_CONFIG_POWER_CONTROL 0x22 /* Power Control. */ +#define FDC37M60X_CONFIG_POWER_MGMT 0x23 /* Intelligent Power Mgmt. */ +#define FDC37M60X_CONFIG_OSC 0x24 /* OSC. */ + +#define FDC37M60X_CONFIGURATION_PORT 0x3f0 /* Write-only. */ + +/* The content of FDC37M60X_CONFIG_REG_LDN (index 0x07) must be set to the + LDN the register belongs to, before you can access the register. */ +static void fdc37m60x_sio_write(uint8_t ldn, u8 index, u8 value) +{ + outb(FDC37M60X_CONFIG_REG_LDN, SIO_BASE); + outb(ldn, SIO_DATA); + outb(index, SIO_BASE); + outb(value, SIO_DATA); +} + +/* Enable the peripheral devices on the FDC37M60X Super I/O chip. */ +static void fdc37m60x_enable_serial(device_t dev, u16 iobase) +{ + /* (1) Enter the configuration state. */ + outb(0x55, FDC37M60X_CONFIGURATION_PORT); + + /* (2) Modify the data of configuration registers. */ + + /* Power on all devices by setting the respective bit. + Bits: 0 (FDC), 3 (PP), 4 (Com1), 5 (Com2). The rest is reserved. */ + fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_POWER_CONTROL, 0x39); + + /* Disable intelligent power management. */ + fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_POWER_MGMT, 0x00); + + /* Turn on OSC, turn on BRG clock. */ + fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_OSC, 0x04); + + /* Configure serial port 1. */ + fdc37m60x_sio_write(FDC37M60X_SP1, 0x60, 0x03); + fdc37m60x_sio_write(FDC37M60X_SP1, 0x61, 0xf8); /* I/O 0x3f8 */ + fdc37m60x_sio_write(FDC37M60X_SP1, 0x70, 0x04); /* IRQ 4 */ + fdc37m60x_sio_write(FDC37M60X_SP1, 0xf0, 0x00); /* Normal */ + + /* Enable serial port 1. */ + fdc37m60x_sio_write(FDC37M60X_SP1, 0x30, 0x01); + + /* (3) Exit the configuration state. */ + outb(0xaa, FDC37M60X_CONFIGURATION_PORT); +} diff --git a/src/superio/smsc/fdc37m60x/fdc37m60x_early_serial.c b/src/superio/smsc/fdc37m60x/fdc37m60x_early_serial.c deleted file mode 100644 index d8cd8c683d..0000000000 --- a/src/superio/smsc/fdc37m60x/fdc37m60x_early_serial.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "fdc37m60x.h" - -/* The base address is 0x3f0 or 0x370, depending on the SYSOPT pin. */ -#define SIO_BASE 0x3f0 -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - -/* Global configuration registers. */ -#define FDC37M60X_CONFIG_REG_CC 0x02 /* Configure Control. */ -#define FDC37M60X_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define FDC37M60X_CONFIG_POWER_CONTROL 0x22 /* Power Control. */ -#define FDC37M60X_CONFIG_POWER_MGMT 0x23 /* Intelligent Power Mgmt. */ -#define FDC37M60X_CONFIG_OSC 0x24 /* OSC. */ - -#define FDC37M60X_CONFIGURATION_PORT 0x3f0 /* Write-only. */ - -/* The content of FDC37M60X_CONFIG_REG_LDN (index 0x07) must be set to the - LDN the register belongs to, before you can access the register. */ -static void fdc37m60x_sio_write(uint8_t ldn, u8 index, u8 value) -{ - outb(FDC37M60X_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); -} - -/* Enable the peripheral devices on the FDC37M60X Super I/O chip. */ -static void fdc37m60x_enable_serial(device_t dev, u16 iobase) -{ - /* (1) Enter the configuration state. */ - outb(0x55, FDC37M60X_CONFIGURATION_PORT); - - /* (2) Modify the data of configuration registers. */ - - /* Power on all devices by setting the respective bit. - Bits: 0 (FDC), 3 (PP), 4 (Com1), 5 (Com2). The rest is reserved. */ - fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_POWER_CONTROL, 0x39); - - /* Disable intelligent power management. */ - fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_POWER_MGMT, 0x00); - - /* Turn on OSC, turn on BRG clock. */ - fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_OSC, 0x04); - - /* Configure serial port 1. */ - fdc37m60x_sio_write(FDC37M60X_SP1, 0x60, 0x03); - fdc37m60x_sio_write(FDC37M60X_SP1, 0x61, 0xf8); /* I/O 0x3f8 */ - fdc37m60x_sio_write(FDC37M60X_SP1, 0x70, 0x04); /* IRQ 4 */ - fdc37m60x_sio_write(FDC37M60X_SP1, 0xf0, 0x00); /* Normal */ - - /* Enable serial port 1. */ - fdc37m60x_sio_write(FDC37M60X_SP1, 0x30, 0x01); - - /* (3) Exit the configuration state. */ - outb(0xaa, FDC37M60X_CONFIGURATION_PORT); -} diff --git a/src/superio/smsc/lpc47b272/early_serial.c b/src/superio/smsc/lpc47b272/early_serial.c new file mode 100644 index 0000000000..75093ea0a9 --- /dev/null +++ b/src/superio/smsc/lpc47b272/early_serial.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Digital Design Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for SMSC LPC47B272 Super I/O chip. */ + +#include +#include "lpc47b272.h" + +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +/** + * Configure the base I/O port of the specified serial device and enable the + * serial device. + * + * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. + * @param iobase Processor I/O port address to assign to this serial device. + */ +static void lpc47b272_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c b/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c deleted file mode 100644 index 75093ea0a9..0000000000 --- a/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Digital Design Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for SMSC LPC47B272 Super I/O chip. */ - -#include -#include "lpc47b272.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x55, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -/** - * Configure the base I/O port of the specified serial device and enable the - * serial device. - * - * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. - * @param iobase Processor I/O port address to assign to this serial device. - */ -static void lpc47b272_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/smsc/lpc47b397/early_gpio.c b/src/superio/smsc/lpc47b397/early_gpio.c new file mode 100644 index 0000000000..16066b75cd --- /dev/null +++ b/src/superio/smsc/lpc47b397/early_gpio.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static void lpc47b397_gpio_offset_out(u16 iobase, u16 offset, u8 value) +{ + outb(value, iobase + offset); +} + +static u8 lpc47b397_gpio_offset_in(u16 iobase, u16 offset) +{ + return inb(iobase+offset); +} + +#if 0 +/* For GP60-GP64, GP66-GP85. */ +#define LPC47B397_GPIO_CNTL_INDEX 0x70 +#define LPC47B397_GPIO_CNTL_DATA 0x71 + +static void lpc47b397_gpio_index_out(u16 iobase, u8 index, u8 value) +{ + outb(index, iobase + LPC47B397_GPIO_CNTL_INDEX); + outb(value, iobase + LPC47B397_GPIO_CNTL_DATA); +} + +static u8 lpc47b397_gpio_index_in(u16 iobase, u8 index) +{ + outb(index, iobase + LPC47B397_GPIO_CNTL_INDEX); + return inb(iobase + LPC47B397_GPIO_CNTL_DATA); +} +#endif diff --git a/src/superio/smsc/lpc47b397/early_serial.c b/src/superio/smsc/lpc47b397/early_serial.c new file mode 100644 index 0000000000..bea97b45f7 --- /dev/null +++ b/src/superio/smsc/lpc47b397/early_serial.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "lpc47b397.h" + +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +static void lpc47b397_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c b/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c deleted file mode 100644 index 16066b75cd..0000000000 --- a/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -static void lpc47b397_gpio_offset_out(u16 iobase, u16 offset, u8 value) -{ - outb(value, iobase + offset); -} - -static u8 lpc47b397_gpio_offset_in(u16 iobase, u16 offset) -{ - return inb(iobase+offset); -} - -#if 0 -/* For GP60-GP64, GP66-GP85. */ -#define LPC47B397_GPIO_CNTL_INDEX 0x70 -#define LPC47B397_GPIO_CNTL_DATA 0x71 - -static void lpc47b397_gpio_index_out(u16 iobase, u8 index, u8 value) -{ - outb(index, iobase + LPC47B397_GPIO_CNTL_INDEX); - outb(value, iobase + LPC47B397_GPIO_CNTL_DATA); -} - -static u8 lpc47b397_gpio_index_in(u16 iobase, u8 index) -{ - outb(index, iobase + LPC47B397_GPIO_CNTL_INDEX); - return inb(iobase + LPC47B397_GPIO_CNTL_DATA); -} -#endif diff --git a/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c b/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c deleted file mode 100644 index bea97b45f7..0000000000 --- a/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "lpc47b397.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x55, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -static void lpc47b397_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/smsc/lpc47m10x/early_serial.c b/src/superio/smsc/lpc47m10x/early_serial.c new file mode 100644 index 0000000000..06cf7d4030 --- /dev/null +++ b/src/superio/smsc/lpc47m10x/early_serial.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Digital Design Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "lpc47m10x.h" + +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +/** + * Configure the base I/O port of the specified serial device and enable the + * serial device. + * + * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. + * @param iobase Processor I/O port address to assign to this serial device. + */ +static void lpc47m10x_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c b/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c deleted file mode 100644 index 06cf7d4030..0000000000 --- a/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Digital Design Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "lpc47m10x.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x55, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -/** - * Configure the base I/O port of the specified serial device and enable the - * serial device. - * - * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. - * @param iobase Processor I/O port address to assign to this serial device. - */ -static void lpc47m10x_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/smsc/lpc47m15x/early_serial.c b/src/superio/smsc/lpc47m15x/early_serial.c new file mode 100644 index 0000000000..bc417d86ef --- /dev/null +++ b/src/superio/smsc/lpc47m15x/early_serial.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for the SMSC LPC47M15X Super I/O chip */ + +#include +#include "lpc47m15x.h" + +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +static inline void lpc47m15x_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c b/src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c deleted file mode 100644 index bc417d86ef..0000000000 --- a/src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the SMSC LPC47M15X Super I/O chip */ - -#include -#include "lpc47m15x.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x55, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -static inline void lpc47m15x_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/smsc/lpc47n217/early_serial.c b/src/superio/smsc/lpc47n217/early_serial.c new file mode 100644 index 0000000000..ce79db8f0c --- /dev/null +++ b/src/superio/smsc/lpc47n217/early_serial.c @@ -0,0 +1,123 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Digital Design Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for SMSC LPC47N217 Super I/O chip. */ + +#include +#include +#include "lpc47n217.h" + +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +/** + * Program the base I/O port for the specified logical device. + * + * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. + * @param iobase Base I/O port for the logical device. + */ +void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase) +{ + /* LPC47N217 requires base ports to be a multiple of 4. */ + ASSERT(!(iobase & 0x3)); + + switch(dev & 0xFF) { + case LPC47N217_PP: + pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff); + break; + case LPC47N217_SP1: + pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff); + break; + case LPC47N217_SP2: + pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff); + break; + default: + break; + } +} + +/** + * Enable or disable the specified logical device. + * + * Technically, a full disable requires setting the device's base I/O port + * below 0x100. We don't do that here, because we don't have access to a data + * structure that specifies what the 'real' base port is (when asked to enable + * the device). Also the function is used only to disable the device while its + * true base port is programmed (see lpc47n217_enable_serial() below). + * + * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. + * @param enable 0 to disable, anythig else to enable. + */ +void lpc47n217_pnp_set_enable(device_t dev, int enable) +{ + u8 power_register = 0, power_mask = 0, current_power, new_power; + + switch(dev & 0xFF) { + case LPC47N217_PP: + power_register = 0x01; + power_mask = 0x04; + break; + case LPC47N217_SP1: + power_register = 0x02; + power_mask = 0x08; + break; + case LPC47N217_SP2: + power_register = 0x02; + power_mask = 0x80; + break; + default: + return; + } + + current_power = pnp_read_config(dev, power_register); + new_power = current_power & ~power_mask; /* Disable by default. */ + if (enable) + new_power |= power_mask; /* Enable. */ + pnp_write_config(dev, power_register, new_power); +} + +/** + * Configure the base I/O port of the specified serial device and enable the + * serial device. + * + * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. + * @param iobase Processor I/O port address to assign to this serial device. + */ +static void lpc47n217_enable_serial(device_t dev, u16 iobase) +{ + /* + * NOTE: Cannot use pnp_set_XXX() here because they assume chip + * support for logical devices, which the LPC47N217 doesn't have. + */ + pnp_enter_conf_state(dev); + lpc47n217_pnp_set_enable(dev, 0); + lpc47n217_pnp_set_iobase(dev, iobase); + lpc47n217_pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c b/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c deleted file mode 100644 index ce79db8f0c..0000000000 --- a/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Digital Design Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for SMSC LPC47N217 Super I/O chip. */ - -#include -#include -#include "lpc47n217.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x55, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -/** - * Program the base I/O port for the specified logical device. - * - * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. - * @param iobase Base I/O port for the logical device. - */ -void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase) -{ - /* LPC47N217 requires base ports to be a multiple of 4. */ - ASSERT(!(iobase & 0x3)); - - switch(dev & 0xFF) { - case LPC47N217_PP: - pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff); - break; - case LPC47N217_SP1: - pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff); - break; - case LPC47N217_SP2: - pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff); - break; - default: - break; - } -} - -/** - * Enable or disable the specified logical device. - * - * Technically, a full disable requires setting the device's base I/O port - * below 0x100. We don't do that here, because we don't have access to a data - * structure that specifies what the 'real' base port is (when asked to enable - * the device). Also the function is used only to disable the device while its - * true base port is programmed (see lpc47n217_enable_serial() below). - * - * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. - * @param enable 0 to disable, anythig else to enable. - */ -void lpc47n217_pnp_set_enable(device_t dev, int enable) -{ - u8 power_register = 0, power_mask = 0, current_power, new_power; - - switch(dev & 0xFF) { - case LPC47N217_PP: - power_register = 0x01; - power_mask = 0x04; - break; - case LPC47N217_SP1: - power_register = 0x02; - power_mask = 0x08; - break; - case LPC47N217_SP2: - power_register = 0x02; - power_mask = 0x80; - break; - default: - return; - } - - current_power = pnp_read_config(dev, power_register); - new_power = current_power & ~power_mask; /* Disable by default. */ - if (enable) - new_power |= power_mask; /* Enable. */ - pnp_write_config(dev, power_register, new_power); -} - -/** - * Configure the base I/O port of the specified serial device and enable the - * serial device. - * - * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. - * @param iobase Processor I/O port address to assign to this serial device. - */ -static void lpc47n217_enable_serial(device_t dev, u16 iobase) -{ - /* - * NOTE: Cannot use pnp_set_XXX() here because they assume chip - * support for logical devices, which the LPC47N217 doesn't have. - */ - pnp_enter_conf_state(dev); - lpc47n217_pnp_set_enable(dev, 0); - lpc47n217_pnp_set_iobase(dev, iobase); - lpc47n217_pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/smsc/lpc47n227/early_serial.c b/src/superio/smsc/lpc47n227/early_serial.c new file mode 100644 index 0000000000..32bd3e3680 --- /dev/null +++ b/src/superio/smsc/lpc47n227/early_serial.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Digital Design Corporation + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for SMSC LPC47N227 Super I/O chip. */ + +#include +#include "lpc47n227.h" + +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +/** + * Program the base I/O port for the specified logical device. + * + * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. + * @param iobase Base I/O port for the logical device. + */ +void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase) +{ + /* LPC47N227 requires base ports to be a multiple of 4. */ + ASSERT(!(iobase & 0x3)); + + switch (dev & 0xFF) { + case LPC47N227_PP: + pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff); + break; + case LPC47N227_SP1: + pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff); + break; + case LPC47N227_SP2: + pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff); + break; + default: + break; + } +} + +/** + * Enable or disable the specified logical device. + * + * Technically, a full disable requires setting the device's base I/O port + * below 0x100. We don't do that here, because we don't have access to a data + * structure that specifies what the 'real' base port is (when asked to enable + * the device). Also the function is used only to disable the device while its + * true base port is programmed (see lpc47n227_enable_serial() below). + * + * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. + * @param enable 0 to disable, anythig else to enable. + */ +void lpc47n227_pnp_set_enable(device_t dev, int enable) +{ + u8 power_register = 0, power_mask = 0, current_power, new_power; + + switch (dev & 0xFF) { + case LPC47N227_PP: + power_register = 0x01; + power_mask = 0x04; + break; + case LPC47N227_SP1: + power_register = 0x02; + power_mask = 0x08; + break; + case LPC47N227_SP2: + power_register = 0x02; + power_mask = 0x80; + break; + default: + return; + } + + current_power = pnp_read_config(dev, power_register); + new_power = current_power & ~power_mask; /* Disable by default. */ + if (enable) + new_power |= power_mask; /* Enable. */ + pnp_write_config(dev, power_register, new_power); +} + +/** + * Configure the base I/O port of the specified serial device and enable the + * serial device. + * + * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. + * @param iobase Processor I/O port address to assign to this serial device. + */ +static void lpc47n227_enable_serial(device_t dev, u16 iobase) +{ + /* + * NOTE: Cannot use pnp_set_XXX() here because they assume chip + * support for logical devices, which the LPC47N227 doesn't have. + */ + pnp_enter_conf_state(dev); + lpc47n227_pnp_set_enable(dev, 0); + lpc47n227_pnp_set_iobase(dev, iobase); + lpc47n227_pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/smsc/lpc47n227/lpc47n227_early_serial.c b/src/superio/smsc/lpc47n227/lpc47n227_early_serial.c deleted file mode 100644 index 32bd3e3680..0000000000 --- a/src/superio/smsc/lpc47n227/lpc47n227_early_serial.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Digital Design Corporation - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for SMSC LPC47N227 Super I/O chip. */ - -#include -#include "lpc47n227.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x55, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -/** - * Program the base I/O port for the specified logical device. - * - * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. - * @param iobase Base I/O port for the logical device. - */ -void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase) -{ - /* LPC47N227 requires base ports to be a multiple of 4. */ - ASSERT(!(iobase & 0x3)); - - switch (dev & 0xFF) { - case LPC47N227_PP: - pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff); - break; - case LPC47N227_SP1: - pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff); - break; - case LPC47N227_SP2: - pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff); - break; - default: - break; - } -} - -/** - * Enable or disable the specified logical device. - * - * Technically, a full disable requires setting the device's base I/O port - * below 0x100. We don't do that here, because we don't have access to a data - * structure that specifies what the 'real' base port is (when asked to enable - * the device). Also the function is used only to disable the device while its - * true base port is programmed (see lpc47n227_enable_serial() below). - * - * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. - * @param enable 0 to disable, anythig else to enable. - */ -void lpc47n227_pnp_set_enable(device_t dev, int enable) -{ - u8 power_register = 0, power_mask = 0, current_power, new_power; - - switch (dev & 0xFF) { - case LPC47N227_PP: - power_register = 0x01; - power_mask = 0x04; - break; - case LPC47N227_SP1: - power_register = 0x02; - power_mask = 0x08; - break; - case LPC47N227_SP2: - power_register = 0x02; - power_mask = 0x80; - break; - default: - return; - } - - current_power = pnp_read_config(dev, power_register); - new_power = current_power & ~power_mask; /* Disable by default. */ - if (enable) - new_power |= power_mask; /* Enable. */ - pnp_write_config(dev, power_register, new_power); -} - -/** - * Configure the base I/O port of the specified serial device and enable the - * serial device. - * - * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. - * @param iobase Processor I/O port address to assign to this serial device. - */ -static void lpc47n227_enable_serial(device_t dev, u16 iobase) -{ - /* - * NOTE: Cannot use pnp_set_XXX() here because they assume chip - * support for logical devices, which the LPC47N227 doesn't have. - */ - pnp_enter_conf_state(dev); - lpc47n227_pnp_set_enable(dev, 0); - lpc47n227_pnp_set_iobase(dev, iobase); - lpc47n227_pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/smsc/smscsuperio/early_serial.c b/src/superio/smsc/smscsuperio/early_serial.c new file mode 100644 index 0000000000..281a35c861 --- /dev/null +++ b/src/superio/smsc/smscsuperio/early_serial.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include + +/* All known/supported SMSC Super I/Os have the same logical device IDs + * for the serial ports (COM1, COM2). + */ +#define SMSCSUPERIO_SP1 4 /* Com1 */ +#define SMSCSUPERIO_SP2 5 /* Com2 */ + +/** + * Enable the specified serial port. + * + * @param dev The device to use. + * @param iobase The I/O base of the serial port (usually 0x3f8/0x2f8). + */ +static inline void smscsuperio_enable_serial(device_t dev, u16 iobase) +{ + u16 port = dev >> 8; + + outb(0x55, port); /* Enter the configuration state. */ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + outb(0xaa, port); /* Exit the configuration state. */ +} diff --git a/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c b/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c deleted file mode 100644 index 281a35c861..0000000000 --- a/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include - -/* All known/supported SMSC Super I/Os have the same logical device IDs - * for the serial ports (COM1, COM2). - */ -#define SMSCSUPERIO_SP1 4 /* Com1 */ -#define SMSCSUPERIO_SP2 5 /* Com2 */ - -/** - * Enable the specified serial port. - * - * @param dev The device to use. - * @param iobase The I/O base of the serial port (usually 0x3f8/0x2f8). - */ -static inline void smscsuperio_enable_serial(device_t dev, u16 iobase) -{ - u16 port = dev >> 8; - - outb(0x55, port); /* Enter the configuration state. */ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - outb(0xaa, port); /* Exit the configuration state. */ -} diff --git a/src/superio/winbond/w83627dhg/early_serial.c b/src/superio/winbond/w83627dhg/early_serial.c new file mode 100644 index 0000000000..f530dc6797 --- /dev/null +++ b/src/superio/winbond/w83627dhg/early_serial.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include "w83627dhg.h" + +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +static void w83627dhg_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); +} diff --git a/src/superio/winbond/w83627dhg/w83627dhg_early_serial.c b/src/superio/winbond/w83627dhg/w83627dhg_early_serial.c deleted file mode 100644 index f530dc6797..0000000000 --- a/src/superio/winbond/w83627dhg/w83627dhg_early_serial.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include "w83627dhg.h" - -static void pnp_enter_ext_func_mode(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_ext_func_mode(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -static void w83627dhg_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} diff --git a/src/superio/winbond/w83627ehg/early_init.c b/src/superio/winbond/w83627ehg/early_init.c new file mode 100644 index 0000000000..5e66fafadb --- /dev/null +++ b/src/superio/winbond/w83627ehg/early_init.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include "w83627ehg.h" + +void w83627ehg_disable_dev(device_t dev) +{ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); +} + +void w83627ehg_enable_dev(device_t dev, u16 iobase) +{ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); +} diff --git a/src/superio/winbond/w83627ehg/early_serial.c b/src/superio/winbond/w83627ehg/early_serial.c new file mode 100644 index 0000000000..deb8bf6566 --- /dev/null +++ b/src/superio/winbond/w83627ehg/early_serial.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "w83627ehg.h" + +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +void w83627ehg_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); +} diff --git a/src/superio/winbond/w83627ehg/w83627ehg_early_init.c b/src/superio/winbond/w83627ehg/w83627ehg_early_init.c deleted file mode 100644 index 5e66fafadb..0000000000 --- a/src/superio/winbond/w83627ehg/w83627ehg_early_init.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include "w83627ehg.h" - -void w83627ehg_disable_dev(device_t dev) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); -} - -void w83627ehg_enable_dev(device_t dev, u16 iobase) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); -} diff --git a/src/superio/winbond/w83627ehg/w83627ehg_early_serial.c b/src/superio/winbond/w83627ehg/w83627ehg_early_serial.c deleted file mode 100644 index deb8bf6566..0000000000 --- a/src/superio/winbond/w83627ehg/w83627ehg_early_serial.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "w83627ehg.h" - -static void pnp_enter_ext_func_mode(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_ext_func_mode(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -void w83627ehg_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} diff --git a/src/superio/winbond/w83627hf/early_init.c b/src/superio/winbond/w83627hf/early_init.c new file mode 100644 index 0000000000..55ab2fa109 --- /dev/null +++ b/src/superio/winbond/w83627hf/early_init.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright 2003-2004 Linux Networx + * Copyright 2004 Tyan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "w83627hf.h" + +void w83627hf_disable_dev(device_t dev) +{ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); +} + +void w83627hf_enable_dev(device_t dev, u16 iobase) +{ + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); +} diff --git a/src/superio/winbond/w83627hf/early_serial.c b/src/superio/winbond/w83627hf/early_serial.c new file mode 100644 index 0000000000..14cad5dd66 --- /dev/null +++ b/src/superio/winbond/w83627hf/early_serial.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan + * Copyright (C) 2010 Win Enterprises (anishp@win-ent.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "w83627hf.h" + +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +void w83627hf_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); +} + +void w83627hf_set_clksel_48(device_t dev) +{ + u8 reg8; + + pnp_enter_ext_func_mode(dev); + reg8 = pnp_read_config(dev, 0x24); + reg8 |= (1 << 6); /* Set CLKSEL (clock input on pin 1) to 48MHz. */ + pnp_write_config(dev, 0x24, reg8); + pnp_exit_ext_func_mode(dev); +} diff --git a/src/superio/winbond/w83627hf/w83627hf_early_init.c b/src/superio/winbond/w83627hf/w83627hf_early_init.c deleted file mode 100644 index 55ab2fa109..0000000000 --- a/src/superio/winbond/w83627hf/w83627hf_early_init.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright 2003-2004 Linux Networx - * Copyright 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "w83627hf.h" - -void w83627hf_disable_dev(device_t dev) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); -} - -void w83627hf_enable_dev(device_t dev, u16 iobase) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); -} diff --git a/src/superio/winbond/w83627hf/w83627hf_early_serial.c b/src/superio/winbond/w83627hf/w83627hf_early_serial.c deleted file mode 100644 index 14cad5dd66..0000000000 --- a/src/superio/winbond/w83627hf/w83627hf_early_serial.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * Copyright (C) 2010 Win Enterprises (anishp@win-ent.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "w83627hf.h" - -static void pnp_enter_ext_func_mode(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_ext_func_mode(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -void w83627hf_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} - -void w83627hf_set_clksel_48(device_t dev) -{ - u8 reg8; - - pnp_enter_ext_func_mode(dev); - reg8 = pnp_read_config(dev, 0x24); - reg8 |= (1 << 6); /* Set CLKSEL (clock input on pin 1) to 48MHz. */ - pnp_write_config(dev, 0x24, reg8); - pnp_exit_ext_func_mode(dev); -} diff --git a/src/superio/winbond/w83627thg/early_serial.c b/src/superio/winbond/w83627thg/early_serial.c new file mode 100644 index 0000000000..559e9827fc --- /dev/null +++ b/src/superio/winbond/w83627thg/early_serial.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "w83627thg.h" + +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +static void inline w83627thg_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); +} diff --git a/src/superio/winbond/w83627thg/w83627thg_early_serial.c b/src/superio/winbond/w83627thg/w83627thg_early_serial.c deleted file mode 100644 index 559e9827fc..0000000000 --- a/src/superio/winbond/w83627thg/w83627thg_early_serial.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "w83627thg.h" - -static void pnp_enter_ext_func_mode(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_ext_func_mode(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -static void inline w83627thg_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} diff --git a/src/superio/winbond/w83627uhg/early_serial.c b/src/superio/winbond/w83627uhg/early_serial.c new file mode 100644 index 0000000000..3636641f60 --- /dev/null +++ b/src/superio/winbond/w83627uhg/early_serial.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Dynon Avionics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include "w83627uhg.h" + +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +/** Set the input clock to 24 or 48 MHz. */ +static void w83627uhg_set_input_clk_sel(device_t dev, u8 speed_24mhz) +{ + u8 value; + + value = pnp_read_config(dev, 0x24); + value &= ~(1 << 6); + if (!speed_24mhz) + value |= (1 << 6); + pnp_write_config(dev, 0x24, value); +} + +static void w83627uhg_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); +} diff --git a/src/superio/winbond/w83627uhg/w83627uhg_early_serial.c b/src/superio/winbond/w83627uhg/w83627uhg_early_serial.c deleted file mode 100644 index 3636641f60..0000000000 --- a/src/superio/winbond/w83627uhg/w83627uhg_early_serial.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Dynon Avionics - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include "w83627uhg.h" - -static void pnp_enter_ext_func_mode(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_ext_func_mode(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -/** Set the input clock to 24 or 48 MHz. */ -static void w83627uhg_set_input_clk_sel(device_t dev, u8 speed_24mhz) -{ - u8 value; - - value = pnp_read_config(dev, 0x24); - value &= ~(1 << 6); - if (!speed_24mhz) - value |= (1 << 6); - pnp_write_config(dev, 0x24, value); -} - -static void w83627uhg_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} diff --git a/src/superio/winbond/w83697hf/early_serial.c b/src/superio/winbond/w83697hf/early_serial.c new file mode 100644 index 0000000000..7731804699 --- /dev/null +++ b/src/superio/winbond/w83697hf/early_serial.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Sean Nelson + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include "w83697hf.h" + +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +static void w83697hf_set_clksel_48(device_t dev) +{ + u8 reg8; + + pnp_enter_ext_func_mode(dev); + reg8 = pnp_read_config(dev, 0x24); + reg8 |= (1 << 6); /* Set the clock input to 48MHz. */ + pnp_write_config(dev, 0x24, reg8); + pnp_exit_ext_func_mode(dev); +} + +static void w83697hf_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); +} diff --git a/src/superio/winbond/w83697hf/w83697hf_early_serial.c b/src/superio/winbond/w83697hf/w83697hf_early_serial.c deleted file mode 100644 index 7731804699..0000000000 --- a/src/superio/winbond/w83697hf/w83697hf_early_serial.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Sean Nelson - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include "w83697hf.h" - -static void pnp_enter_ext_func_mode(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_ext_func_mode(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -static void w83697hf_set_clksel_48(device_t dev) -{ - u8 reg8; - - pnp_enter_ext_func_mode(dev); - reg8 = pnp_read_config(dev, 0x24); - reg8 |= (1 << 6); /* Set the clock input to 48MHz. */ - pnp_write_config(dev, 0x24, reg8); - pnp_exit_ext_func_mode(dev); -} - -static void w83697hf_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} diff --git a/src/superio/winbond/w83977f/early_serial.c b/src/superio/winbond/w83977f/early_serial.c new file mode 100644 index 0000000000..f0fb1da6d5 --- /dev/null +++ b/src/superio/winbond/w83977f/early_serial.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Nikolay Petukhov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "w83977f.h" + +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +static void w83977f_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); +} diff --git a/src/superio/winbond/w83977f/w83977f_early_serial.c b/src/superio/winbond/w83977f/w83977f_early_serial.c deleted file mode 100644 index f0fb1da6d5..0000000000 --- a/src/superio/winbond/w83977f/w83977f_early_serial.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Nikolay Petukhov - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "w83977f.h" - -static void pnp_enter_ext_func_mode(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_ext_func_mode(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -static void w83977f_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} diff --git a/src/superio/winbond/w83977tf/early_serial.c b/src/superio/winbond/w83977tf/early_serial.c new file mode 100644 index 0000000000..fb4590b50a --- /dev/null +++ b/src/superio/winbond/w83977tf/early_serial.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include "w83977tf.h" + +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +static void w83977tf_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); +} diff --git a/src/superio/winbond/w83977tf/w83977tf_early_serial.c b/src/superio/winbond/w83977tf/w83977tf_early_serial.c deleted file mode 100644 index fb4590b50a..0000000000 --- a/src/superio/winbond/w83977tf/w83977tf_early_serial.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include "w83977tf.h" - -static void pnp_enter_ext_func_mode(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_ext_func_mode(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -static void w83977tf_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} -- cgit v1.2.3