From 657d9cd5482835b49d79c7eabeb7baf2dce70dfe Mon Sep 17 00:00:00 2001 From: "Jonathan A. Kollasch" Date: Mon, 6 Jul 2015 08:07:50 -0500 Subject: smscsuperio: map interrupt in smscsuperio_enable_serial() This is a stopgap for when you use SUPERIO_SMSC_SMSCSUPERIO and the interrupt is unmapped at reset, but for whatever reason the chip is inaccessible in smscsuperio/superio.c::enable_dev() and thus the devicetree.cb IRQ information is not applied in ramstage and then serial console output fails to work for more than the UART FIFO depth in the OS. Change-Id: I00998088975569516f7caeb7f4098b48fe437889 Signed-off-by: Jonathan A. Kollasch Reviewed-on: https://review.coreboot.org/10807 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Zheng Bao Reviewed-by: Stefan Reinauer --- src/superio/smsc/smscsuperio/early_serial.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/superio/smsc/smscsuperio') diff --git a/src/superio/smsc/smscsuperio/early_serial.c b/src/superio/smsc/smscsuperio/early_serial.c index 7845ab83be..27e3ef266c 100644 --- a/src/superio/smsc/smscsuperio/early_serial.c +++ b/src/superio/smsc/smscsuperio/early_serial.c @@ -51,6 +51,14 @@ void smscsuperio_enable_serial(pnp_devfn_t dev, u16 iobase) pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + switch (iobase) { + case 0x03f8: + pnp_set_irq(dev, PNP_IDX_IRQ0, 4); + break; + case 0x02f8: + pnp_set_irq(dev, PNP_IDX_IRQ0, 3); + break; + } pnp_set_enable(dev, 1); pnp_exit_conf_state(dev); } -- cgit v1.2.3