From 6b2475dd8198f3f6b43b96d48b2f4e3de75042a4 Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Fri, 1 Dec 2006 13:14:55 +0000 Subject: Explicitly set the CLKIN to 24 MHz on all ITE Super I/Os, otherwise serial output might not always work correctly (trivial). Thanks Philipp Degler for testing and reporting this issue. Signed-off-by: Uwe Hermann Acked-by: Uwe Hermann git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/superio/ite/it8712f/it8712f_early_serial.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/superio/ite/it8712f') diff --git a/src/superio/ite/it8712f/it8712f_early_serial.c b/src/superio/ite/it8712f/it8712f_early_serial.c index 3d6c2e8f6a..932fcb2fe3 100644 --- a/src/superio/ite/it8712f/it8712f_early_serial.c +++ b/src/superio/ite/it8712f/it8712f_early_serial.c @@ -78,8 +78,8 @@ static void it8712f_enable_serial(device_t dev, unsigned iobase) it8712f_sio_write(IT8712F_GAME, 0x30, 0x1); /* GAME port */ it8712f_sio_write(IT8712F_IR, 0x30, 0x1); /* Consumer IR */ - /* Select 24MHz/48MHz CLKIN (set/clear bit 0). TODO: Needed? */ - /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x01); */ + /* Select 24MHz CLKIN (set bit 0). */ + it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x01); /* Clear software suspend mode (clear bit 0). TODO: Needed? */ /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_SWSUSP, 0x00); */ -- cgit v1.2.3