From 5c6bae213ea55e1436e010706560d86120b0b286 Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Mon, 8 Nov 2010 15:16:30 +0000 Subject: Random ITE Super I/O fixes. - Drop some of the less useful / outdated / duplicated comments. - Simplify and streamline some code to look like the other Super I/Os. - Use u8/16/etc. everywhere. - ITE IT8718F: Add missing GPIO LDN. - Add missing braces around SIO_DATA #defines, potential bug even. Signed-off-by: Uwe Hermann Acked-by: Uwe Hermann git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6047 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/superio/ite/it8712f/Makefile.inc | 2 +- src/superio/ite/it8712f/chip.h | 6 +-- src/superio/ite/it8712f/it8712f.h | 3 +- src/superio/ite/it8712f/it8712f_early_serial.c | 70 +++++++++++--------------- src/superio/ite/it8712f/superio.c | 22 +++----- 5 files changed, 42 insertions(+), 61 deletions(-) (limited to 'src/superio/ite/it8712f') diff --git a/src/superio/ite/it8712f/Makefile.inc b/src/superio/ite/it8712f/Makefile.inc index 08b2223192..8c8ace6fd8 100644 --- a/src/superio/ite/it8712f/Makefile.inc +++ b/src/superio/ite/it8712f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_ITE_IT8712F) += superio.c + diff --git a/src/superio/ite/it8712f/chip.h b/src/superio/ite/it8712f/chip.h index 22dfa8dcc8..844d4df7a0 100644 --- a/src/superio/ite/it8712f/chip.h +++ b/src/superio/ite/it8712f/chip.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SUPERIO_ITE_IT8712F -#define _SUPERIO_ITE_IT8712F +#ifndef SUPERIO_ITE_IT8712F_CHIP_H +#define SUPERIO_ITE_IT8712F_CHIP_H #include #include @@ -32,4 +32,4 @@ struct superio_ite_it8712f_config { struct pc_keyboard keyboard; }; -#endif /* _SUPERIO_ITE_IT8712F */ +#endif diff --git a/src/superio/ite/it8712f/it8712f.h b/src/superio/ite/it8712f/it8712f.h index 60c7413b3e..609f361a66 100644 --- a/src/superio/ite/it8712f/it8712f.h +++ b/src/superio/ite/it8712f/it8712f.h @@ -19,7 +19,6 @@ */ /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8712_2.asp */ -/* Status: Com1 is tested and works. */ #define IT8712F_FDC 0x00 /* Floppy */ #define IT8712F_SP1 0x01 /* Com1 */ @@ -35,7 +34,7 @@ #ifndef __ROMCC__ void it8712f_kill_watchdog(void); -void it8712f_enable_serial(device_t dev, unsigned iobase); +void it8712f_enable_serial(device_t dev, u16 iobase); void it8712f_24mhz_clkin(void); void it8712f_enable_3vsbsw(void); #endif diff --git a/src/superio/ite/it8712f/it8712f_early_serial.c b/src/superio/ite/it8712f/it8712f_early_serial.c index 76f9bc0d07..ebc8e0a7f1 100644 --- a/src/superio/ite/it8712f/it8712f_early_serial.c +++ b/src/superio/ite/it8712f/it8712f_early_serial.c @@ -24,7 +24,7 @@ /* The base address is 0x2e or 0x4e, depending on config bytes. */ #define SIO_BASE 0x2e #define SIO_INDEX SIO_BASE -#define SIO_DATA SIO_BASE+1 +#define SIO_DATA (SIO_BASE + 1) /* Global configuration registers. */ #define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ @@ -35,11 +35,7 @@ #define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */ #define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */ -#define IT8712F_CONFIGURATION_PORT 0x2e /* Write-only. */ - -/* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the - LDN the register belongs to, before you can access the register. */ -static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) +static void it8712f_sio_write(u8 ldn, u8 index, u8 value) { outb(IT8712F_CONFIG_REG_LDN, SIO_BASE); outb(ldn, SIO_DATA); @@ -49,75 +45,69 @@ static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) static void it8712f_enter_conf(void) { - /* Enter the configuration state (MB PnP mode). */ - - /* Perform MB PnP setup to put the SIO chip at 0x2e. */ - /* Base address 0x2e: 0x87 0x01 0x55 0x55. */ - /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ - outb(0x87, IT8712F_CONFIGURATION_PORT); - outb(0x01, IT8712F_CONFIGURATION_PORT); - outb(0x55, IT8712F_CONFIGURATION_PORT); - outb(0x55, IT8712F_CONFIGURATION_PORT); + u16 port = 0x2e; /* TODO: Don't hardcode! */ + + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); } static void it8712f_exit_conf(void) { - /* Exit the configuration state (MB PnP mode). */ it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); } +/* Select 24MHz CLKIN (48MHz is the default). */ void it8712f_24mhz_clkin(void) { it8712f_enter_conf(); - - /* Select 24MHz CLKIN (48MHZ default)*/ it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x1); - it8712f_exit_conf(); } +/* + * We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2! + * + * LDN 7, reg 0x2a - needed for S3, or memory power will be cut off. + * + * Enable 3VSBSW#. (For System Suspend-to-RAM) + * 0: 3VSBSW# will be always inactive. + * 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#. + */ void it8712f_enable_3vsbsw(void) { - - /* We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2! - LDN 7, reg 0x2a - needed for S3, or memory power will be cut off. - Enable 3VSBSW#. (For System Suspend-to-RAM) - 0: 3VSBSW# will be always inactive. - 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#. - */ - it8712f_enter_conf(); - it8712f_sio_write(0x07, IT8712F_CONFIG_REG_MFC, 0x80); + it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_MFC, 0x80); it8712f_exit_conf(); } void it8712f_kill_watchdog(void) { it8712f_enter_conf(); - - /* Kill the Watchdog */ - it8712f_sio_write(0x07, IT8712F_CONFIG_REG_WATCHDOG, 0x00); - + it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_WATCHDOG, 0x00); it8712f_exit_conf(); } -/* Enable the peripheral devices on the IT8712F Super I/O chip. */ -void it8712f_enable_serial(device_t dev, unsigned iobase) +/* Enable the serial port(s). */ +void it8712f_enable_serial(device_t dev, u16 iobase) { - /* (1) Enter the configuration state (MB PnP mode). */ it8712f_enter_conf(); /* (2) Modify the data of configuration registers. */ - /* Select the chip to configure (if there's more than one). - Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. - If this register is not written, both chips are configured. */ + /* + * Select the chip to configure (if there's more than one). + * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. + * If this register is not written, both chips are configured. + */ + /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CONFIGSEL, 0x00); */ /* Enable serial port(s). */ - it8712f_sio_write(IT8712F_SP1, 0x30, 0x1); /* Serial port 1 */ - it8712f_sio_write(IT8712F_SP2, 0x30, 0x1); /* Serial port 2 */ + it8712f_sio_write(IT8712F_SP1, 0x30, 0x1); /* Serial port 1 */ + it8712f_sio_write(IT8712F_SP2, 0x30, 0x1); /* Serial port 2 */ /* Clear software suspend mode (clear bit 0). TODO: Needed? */ /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_SWSUSP, 0x00); */ diff --git a/src/superio/ite/it8712f/superio.c b/src/superio/ite/it8712f/superio.c index 2d2a83a943..4d41ac3412 100644 --- a/src/superio/ite/it8712f/superio.c +++ b/src/superio/ite/it8712f/superio.c @@ -28,19 +28,14 @@ #include "chip.h" #include "it8712f.h" -/* Base address 0x2e: 0x87 0x01 0x55 0x55. */ -/* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ static void pnp_enter_ext_func_mode(device_t dev) { - outb(0x87, dev->path.pnp.port); - outb(0x01, dev->path.pnp.port); - outb(0x55, dev->path.pnp.port); + u16 port = dev->path.pnp.port; - if (dev->path.pnp.port == 0x4e) { - outb(0xaa, dev->path.pnp.port); - } else { - outb(0x55, dev->path.pnp.port); - } + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); } static void pnp_exit_ext_func_mode(device_t dev) @@ -50,14 +45,11 @@ static void pnp_exit_ext_func_mode(device_t dev) static void it8712f_init(device_t dev) { - struct superio_ite_it8712f_config *conf; + struct superio_ite_it8712f_config *conf = dev->chip_info; struct resource *res0, *res1; - if (!dev->enabled) { + if (!dev->enabled) return; - } - - conf = dev->chip_info; switch (dev->path.pnp.device) { case IT8712F_FDC: /* TODO. */ -- cgit v1.2.3