From cf7b4989083cb3fd1adf34dc5e07d4ac253e8f85 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Wed, 23 Apr 2014 21:52:25 +1000 Subject: superio/fintek/*: Factor out generic romstage component The romstage of Fintek Super I/O's is identical, leading to replication of essentially the same code prone to bitrot. Herein we consolidate the early pre-ram UART initialisation code into fintek/common, rather we leave the exceptions to be implemented under model/. More precisely we provide a well documented version of early_serial.c under fintek/common and select by way of Kconfig as a generic romstage component to Super I/O support. We leave future Super I/O's the option to implement `non-standard` initialisation code should such a (unlikely) need araise. A primary advantage is that new support for romstage serial is now trival to add. We also provide some Kconfig documentation while here. Change-Id: I3c62561558a62ece944a167ba302fb7076bba001 Signed-off-by: Edward O'Callaghan Reviewed-on: http://review.coreboot.org/5575 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/superio/fintek/f71872/f71872.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/superio/fintek/f71872/f71872.h') diff --git a/src/superio/fintek/f71872/f71872.h b/src/superio/fintek/f71872/f71872.h index fb8076248a..629d42deb8 100644 --- a/src/superio/fintek/f71872/f71872.h +++ b/src/superio/fintek/f71872/f71872.h @@ -32,6 +32,4 @@ #define F71872_VID 0x07 /* VID */ #define F71872_PM 0x0a /* ACPI/PME */ -void f71872_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_FINTEK_F71872_H */ -- cgit v1.2.3