From dd2e8c35fb368316b51d969d046696a017f09d25 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Thu, 24 Apr 2014 02:58:11 +1000 Subject: superio/fintek/f71869ad: Configure multi-func reg in devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Facilitate for the configuration of so called "Multi-function Select Registers" with devicetree.cb in ramstage. Make use of this new functionality in, mainboard/jetway/nf81-t56n-lf to correctly configure the Fintek's multiplexed GPIO pins to be in AMD TSI mode. This allows the Fintek to correctly talk to the Southbridge over the SMBus for CPU temperature data as to control fans and so on. Change-Id: I80abcd8b767fc4b22d00d1384ce4ef89fe837e3d Signed-off-by: Edward O'Callaghan Reviewed-on: http://review.coreboot.org/5576 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/superio/fintek/f71869ad/chip.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/superio/fintek/f71869ad/chip.h') diff --git a/src/superio/fintek/f71869ad/chip.h b/src/superio/fintek/f71869ad/chip.h index ea2ee6ed50..5011383d99 100644 --- a/src/superio/fintek/f71869ad/chip.h +++ b/src/superio/fintek/f71869ad/chip.h @@ -22,9 +22,17 @@ #define SUPERIO_FINTEK_F71869AD_CHIP_H #include +#include struct superio_fintek_f71869ad_config { struct pc_keyboard keyboard; + + /* Member variables are defined in devicetree.cb. */ + uint8_t multi_function_register_1; + uint8_t multi_function_register_2; + uint8_t multi_function_register_3; + uint8_t multi_function_register_4; + uint8_t multi_function_register_5; }; #endif /* SUPERIO_FINTEK_F71869AD_CHIP_H */ -- cgit v1.2.3