From 27770c93d49cfd5f5cdec7094259ae600ca4bcca Mon Sep 17 00:00:00 2001 From: Zheng Bao Date: Fri, 5 Nov 2010 07:59:06 +0000 Subject: According to the description in datasheet of f71889, "To enable configuration, the entry key 0x87 must be written to the index port" " -o 4e 87 -o 4e 87 (enable configuration) -o 4e aa (disable configuration) " This piece of text appears in most of the datasheet of fintek superio. It doesnt say it quite clear, but it seems that the 0x87 should be written twice. I tried on f81865, which is not in the coreboot tree yet. If the 0x87 is only written once, you can only R/W the index/data port once. All the subsequent RW will fail. Writing twice will be ok. Plus, in the superiotool, the function enter_conf_mode_winbond_fintek_ite_8787 also write 8787. The fintek superio chips seem to enable the UART automatically when the power is on. So I didnt find it failed to access. Signed-off-by: Zheng Bao Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6025 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/superio/fintek/f71863fg/f71863fg_early_serial.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/superio/fintek/f71863fg') diff --git a/src/superio/fintek/f71863fg/f71863fg_early_serial.c b/src/superio/fintek/f71863fg/f71863fg_early_serial.c index 7eeb06aef0..d410ef6031 100644 --- a/src/superio/fintek/f71863fg/f71863fg_early_serial.c +++ b/src/superio/fintek/f71863fg/f71863fg_early_serial.c @@ -27,6 +27,7 @@ static void pnp_enter_conf_state(device_t dev) { u16 port = dev >> 8; outb(0x87, port); + outb(0x87, port); } static void pnp_exit_conf_state(device_t dev) -- cgit v1.2.3