From 4311d9f8528360f0c161d511a016b643b68562f1 Mon Sep 17 00:00:00 2001 From: Michael Niewöhner Date: Sun, 23 Feb 2020 22:55:03 +0100 Subject: superio/aspeed/ast2400: drop non-onetime-config registers for iLPC2AHB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The specified PNP registers PNP_MSC0-E (F0-FE) are part of the iLPC2AHB bridge's index/value interface. They are no one-time config registers so we can't specify a sane value in the devicetree. Thus, drop them to stop coreboot from complaining about the missing entries. Change-Id: I7d7f16845c755592317f140cca66cca12032f7a6 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39093 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Felix Held --- src/superio/aspeed/ast2400/superio.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'src/superio/aspeed/ast2400') diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c index a3d92c22ce..4867f6ed88 100644 --- a/src/superio/aspeed/ast2400/superio.c +++ b/src/superio/aspeed/ast2400/superio.c @@ -82,10 +82,7 @@ static struct pnp_info pnp_dev_info[] = { { NULL, AST2400_GPIO, PNP_IRQ0, }, // GPIO LDN has no IO Region { NULL, AST2400_SUART3, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, }, { NULL, AST2400_SUART4, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, }, - { NULL, AST2400_ILPC2AHB, PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2 - | PNP_MSC3 | PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSC7 - | PNP_MSC8 | PNP_MSC9 | PNP_MSCA | PNP_MSCB | PNP_MSCC - | PNP_MSCD | PNP_MSCE, }, + { NULL, AST2400_ILPC2AHB, PNP_IRQ0 }, { NULL, AST2400_MAILBOX, PNP_IO0 | PNP_IRQ0, 0xfffe, }, }; -- cgit v1.2.3