From e7dd3ca40504272ede602fe868275c70f3a61ee8 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 5 Jan 2019 09:58:39 +0100 Subject: sb/intel/fsp_rangeley: Fix typo in GPIO Level Change-Id: I83886820b8c1acceb2007b694361fe8c30c34f7f Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/30675 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: David Guckian --- src/southbridge/intel/fsp_rangeley/acpi/soc.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/southbridge') diff --git a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl index b55bd92dd1..dde6796ed0 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl +++ b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl @@ -93,7 +93,7 @@ Scope(\) GIO2, 8, GIO3, 8, Offset(0x0c), // GPIO Level - GL00, 1, + GP00, 1, GP01, 1, GP02, 1, GP0e, 1, -- cgit v1.2.3