From e7a5b76a748a27b033122b55356661b79839874c Mon Sep 17 00:00:00 2001 From: Arne Georg Gleditsch Date: Mon, 13 Sep 2010 15:11:35 +0000 Subject: Move initialization of MMCONF BAR to cache_as_ram setup phase, in order to make sure MMCONF is set up before use. Otherwise, PCI config accesses run before init_cpus() will be lost if MMCONF is enabled (unless explicitly done as port-based accesses). This obsoletes removal of RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78) in mcp55_early_setup, so reinsert. Signed-off-by: Arne Georg Gleditsch Acked-by: Myles Watson git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5810 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'src/southbridge') diff --git a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c index e01630dc05..6a453cbfea 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c @@ -267,13 +267,7 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x74), 0xFFFFFFC0, 0x00000000, RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC0), 0x00000000, 0xCB8410DE, RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007, - /* The following operation hangs when performed via MMCFG: - pci_read_config32(romcc): 00010000:0078: 20040000 - setup_resource_map_x_offset: 10000, 78: 20040000 - pci_write_config32(romcc): 00010000:0078: 19040000 - (hang) - Response missing? */ - /* RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000, */ + RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000, #if MCP55_USE_AZA == 1 RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE, -- cgit v1.2.3