From e27c013f39f0433dac57a754b3484553a536f30d Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 12 Nov 2019 23:34:13 +0100 Subject: nb/intel/i945: Move to C_ENVIRONMENT_BOOTBLOCK Console init in bootblock will be done in a separate CL. Change-Id: Ia2405013f262d904aa82be323e928223dbb4296c Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36795 Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82801gx/Kconfig | 4 --- src/southbridge/intel/i82801gx/Makefile.inc | 2 +- src/southbridge/intel/i82801gx/bootblock.c | 15 +++++---- src/southbridge/intel/i82801gx/bootblock_gcc.c | 44 -------------------------- 4 files changed, 10 insertions(+), 55 deletions(-) delete mode 100644 src/southbridge/intel/i82801gx/bootblock_gcc.c (limited to 'src/southbridge') diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index b0cdfd416c..17ee4fcab3 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -40,10 +40,6 @@ config EHCI_BAR hex default 0xfef00000 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/i82801gx/bootblock.c" - config HPET_MIN_TICKS hex default 0x80 diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 31264295ad..c9ed899578 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -16,7 +16,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y) bootblock-y += early_init.c -bootblock-y += bootblock_gcc.c +bootblock-y += bootblock.c ramstage-y += i82801gx.c ramstage-y += ac97.c diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 9d94d0cd25..4c464ff920 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -14,14 +14,13 @@ */ #include +#include #include "i82801gx.h" static void enable_spi_prefetch(void) { u8 reg8; - pci_devfn_t dev; - - dev = PCI_DEV(0, 0x1f, 0); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); reg8 = pci_read_config8(dev, BIOS_CNTL); reg8 &= ~(3 << 2); @@ -29,13 +28,17 @@ static void enable_spi_prefetch(void) pci_write_config8(dev, BIOS_CNTL, reg8); } -static void bootblock_southbridge_init(void) +void bootblock_early_southbridge_init(void) { enable_spi_prefetch(); - /* Enable RCBA */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); + i82801gx_setup_bars(); /* Enable upper 128bytes of CMOS */ RCBA32(0x3400) = (1 << 2); + + /* Disable watchdog timer */ + RCBA32(GCS) = RCBA32(GCS) | 0x20; + + i82801gx_lpc_setup(); } diff --git a/src/southbridge/intel/i82801gx/bootblock_gcc.c b/src/southbridge/intel/i82801gx/bootblock_gcc.c deleted file mode 100644 index 4c464ff920..0000000000 --- a/src/southbridge/intel/i82801gx/bootblock_gcc.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include "i82801gx.h" - -static void enable_spi_prefetch(void) -{ - u8 reg8; - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - - reg8 = pci_read_config8(dev, BIOS_CNTL); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, BIOS_CNTL, reg8); -} - -void bootblock_early_southbridge_init(void) -{ - enable_spi_prefetch(); - - i82801gx_setup_bars(); - - /* Enable upper 128bytes of CMOS */ - RCBA32(0x3400) = (1 << 2); - - /* Disable watchdog timer */ - RCBA32(GCS) = RCBA32(GCS) | 0x20; - - i82801gx_lpc_setup(); -} -- cgit v1.2.3