From db4f3bacce835222e53dea91976b15abc2113779 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 22 Apr 2020 16:10:14 +0200 Subject: sb/amd/cimx/sb800: Const'ify pci_devfn_t devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I25a6c3ac2426881c6b3f6390ffdc76f08944b7fa Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40602 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski Reviewed-by: Paul Menzel --- src/southbridge/amd/cimx/sb800/bootblock.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'src/southbridge') diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 7a1d05bf17..7181243c94 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -9,9 +9,7 @@ static void enable_rom(void) { u16 word; u32 dword; - pci_devfn_t dev; - - dev = PCI_DEV(0, 0x14, 0x03); + const pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); /* SB800 LPC Bridge 0:20:3:44h. * BIT6: Port Enable for serial port 0x3f8-0x3ff * BIT29: Port Enable for KBC port 0x60 and 0x64 @@ -43,7 +41,7 @@ static void enable_rom(void) static void enable_prefetch(void) { u32 dword; - pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); + const pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); /* Enable PrefetchEnSPIFromHost */ dword = pci_s_read_config32(dev, 0xb8); @@ -53,7 +51,7 @@ static void enable_prefetch(void) static void enable_spi_fast_mode(void) { u32 dword; - pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); + const pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); // set temp MMIO base volatile u32 *spi_base = (void *)0xa0000000; -- cgit v1.2.3