From d7acdfb44acfcebe6107b7286c5e4b79f25a33e0 Mon Sep 17 00:00:00 2001 From: Scott Duplichan Date: Mon, 18 Oct 2010 04:01:12 +0000 Subject: This patch enables SB700 option PrefetchEnSPIFromHost in early setup. It affects only systems booting from SPI flash, not those booting from LPC flash. By default, the SB700 reads dwords from the SPI flash chip. Setting PrefetchEnSPIFromHost causes the SB700 to read entire cache lines from the flash chip. Signed-off-by: Scott Duplichan Acked-by: Carl-Daniel Hailfinger git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/amd/sb700/sb700_early_setup.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/southbridge') diff --git a/src/southbridge/amd/sb700/sb700_early_setup.c b/src/southbridge/amd/sb700/sb700_early_setup.c index 8c268d60af..9f8d44f6c7 100644 --- a/src/southbridge/amd/sb700/sb700_early_setup.c +++ b/src/southbridge/amd/sb700/sb700_early_setup.c @@ -129,6 +129,11 @@ static void sb700_lpc_init(void) reg8 |= (1 << 5) | (1 << 6); pci_write_config8(dev, 0x47, reg8); + /* Enable PrefetchEnSPIFromHost to speed up SPI flash read (does not affect LPC) */ + reg8 = pci_read_config8(dev, 0xbb); + reg8 |= 1 << 0; + pci_write_config8(dev, 0xbb, reg8); + /* SuperIO, LPC ROM */ reg8 = pci_read_config8(dev, 0x48); /* Decode ports 0x2e-0x2f, 0x4e-0x4f (SuperI/O configuration) */ -- cgit v1.2.3