From d48982acacbe87bfe78bf9b748d5a2f3fd3225c0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 12 Apr 2023 20:01:46 +0300 Subject: cpu/intel/speedstep: Separate single SSDT CPU entry MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ibe5d84c8fbff79cc73b01eee0980cbed71ceb506 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/74400 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/southbridge/intel/i82371eb/acpi_tables.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) (limited to 'src/southbridge') diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c index cd002e8135..a4cd1b3102 100644 --- a/src/southbridge/intel/i82371eb/acpi_tables.c +++ b/src/southbridge/intel/i82371eb/acpi_tables.c @@ -6,18 +6,27 @@ #include #include "i82371eb.h" +static void generate_cpu_entry(int cpu) +{ + int pcontrol_blk = DEFAULT_PMBASE + PCNTRL, plen = 6; + + acpigen_write_processor(cpu, pcontrol_blk, plen); + acpigen_pop_len(); +} + void generate_cpu_entries(const struct device *device) { - int cpu, pcontrol_blk=DEFAULT_PMBASE+PCNTRL, plen=6; + int cpu; int numcpus = dev_count_cpu(); + printk(BIOS_DEBUG, "Found %d CPU(s).\n", numcpus); /* without the outer scope, further ssdt addition will end up * within the processor statement */ acpigen_write_scope("\\_SB"); - for (cpu=0; cpu < numcpus; cpu++) { - acpigen_write_processor(cpu, pcontrol_blk, plen); - acpigen_pop_len(); - } + + for (cpu = 0; cpu < numcpus; cpu++) + generate_cpu_entry(cpu); + acpigen_pop_len(); } -- cgit v1.2.3