From d24d6993b6d7bcf7977d74d081e718e1b076d1b0 Mon Sep 17 00:00:00 2001 From: "arch import user (historical)" Date: Wed, 6 Jul 2005 17:06:46 +0000 Subject: Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-26 Creator: Hamish Guthrie Added AMD GX1 northbridge and cs5530 Southbridge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1942 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/amd/cs5530/Config.lb | 4 ++ src/southbridge/amd/cs5530/chip.h | 12 +++++ src/southbridge/amd/cs5530/cs5530.c | 92 +++++++++++++++++++++++++++++++++ src/southbridge/amd/cs5530/cs5530.h | 4 ++ src/southbridge/amd/cs5530/cs5530_ide.c | 30 +++++++++++ 5 files changed, 142 insertions(+) create mode 100644 src/southbridge/amd/cs5530/Config.lb create mode 100644 src/southbridge/amd/cs5530/chip.h create mode 100644 src/southbridge/amd/cs5530/cs5530.c create mode 100644 src/southbridge/amd/cs5530/cs5530.h create mode 100644 src/southbridge/amd/cs5530/cs5530_ide.c (limited to 'src/southbridge') diff --git a/src/southbridge/amd/cs5530/Config.lb b/src/southbridge/amd/cs5530/Config.lb new file mode 100644 index 0000000000..68c0556905 --- /dev/null +++ b/src/southbridge/amd/cs5530/Config.lb @@ -0,0 +1,4 @@ +#config chip.h +driver cs5530.o +#driver cs5530_pci.o +driver cs5530_ide.o diff --git a/src/southbridge/amd/cs5530/chip.h b/src/southbridge/amd/cs5530/chip.h new file mode 100644 index 0000000000..ed891b2acc --- /dev/null +++ b/src/southbridge/amd/cs5530/chip.h @@ -0,0 +1,12 @@ +#ifndef _SOUTHBRIDGE_AMD_CS5530 +#define _SOUTHBRIDGE_AMD_CS5530 + +extern struct chip_operations southbridge_amd_cs5530_ops; + +struct southbridge_amd_cs5530_config { + /* PCI function enables so the pci scan bus finds the devices */ + int enable_ide; + int enable_nvram; +}; + +#endif /* _SOUTHBRIDGE_AMD_CS5530 */ diff --git a/src/southbridge/amd/cs5530/cs5530.c b/src/southbridge/amd/cs5530/cs5530.c new file mode 100644 index 0000000000..f70918e566 --- /dev/null +++ b/src/southbridge/amd/cs5530/cs5530.c @@ -0,0 +1,92 @@ + +#include +#include +#include +#include +#include +#include +#include "cs5530.h" + +static void nvram_on(struct device *dev) +{ +#if 0 + volatile char *flash = (volatile unsigned char *)0xFFFc0000; + unsigned char id1, id2; +#endif + unsigned char reg; + + /* Enable writes to flash at top of memory */ + pci_write_config8(dev, 0x52, 0xee); + + /* Set positive decode on ROM */ + /* Also, there is no apparent reason to turn off the devoce on the */ + /* IDE devices */ + + reg = pci_read_config8(dev, 0x5b); + reg |= 1 << 5; /* ROM Decode */ + reg |= 1 << 3; /* Primary IDE decode */ + reg |= 1 << 4; /* Secondary IDE decode */ + + pci_write_config8(dev, 0x5b, reg); + +#if 0 // just to test if the flash is accessible! + *(flash + 0x555) = 0xaa; + *(flash + 0x2aa) = 0x55; + *(flash + 0x555) = 0x90; + + id1 = *(volatile unsigned char *) flash; + id2 = *(volatile unsigned char *) (flash + 1); + + *flash = 0xf0; + + printk_debug("Flash device: MFGID %02x, DEVID %02x\n", id1, id2); +#endif +} + + +static void southbridge_init(struct device *dev) +{ + printk_spew("cs5530: %s\n", __FUNCTION__); + nvram_on(dev); +} + +/* +static void dump_south(struct device *dev) +{ + int i, j; + + for(i=0; i<256; i+=16) { + printk_debug("0x%02x: ", i); + for(j=0; j<16; j++) + printk_debug("%02x ", pci_read_config8(dev, i+j)); + printk_debug("\n"); + } +} +*/ + +static void southbridge_enable(struct device *dev) +{ + printk_spew("%s: dev is %p\n", __FUNCTION__, dev); +} + +static void cs5530_pci_dev_enable_resources(device_t dev) +{ + printk_spew("cs5530.c: %s()\n", __FUNCTION__); + pci_dev_enable_resources(dev); + enable_childrens_resources(dev); +} + +static struct device_operations southbridge_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = cs5530_pci_dev_enable_resources, + .init = southbridge_init, + .enable = southbridge_enable, + .scan_bus = scan_static_bus, +}; + +static struct pci_driver cs5530_pci_driver __pci_driver = { + .ops = &southbridge_ops, + .vendor = PCI_VENDOR_ID_CYRIX, + .device = PCI_DEVICE_ID_CYRIX_5530_LEGACY, +}; diff --git a/src/southbridge/amd/cs5530/cs5530.h b/src/southbridge/amd/cs5530/cs5530.h new file mode 100644 index 0000000000..127718d47a --- /dev/null +++ b/src/southbridge/amd/cs5530/cs5530.h @@ -0,0 +1,4 @@ +#ifndef _CS5530_H +#define _CS5530_H + +#endif diff --git a/src/southbridge/amd/cs5530/cs5530_ide.c b/src/southbridge/amd/cs5530/cs5530_ide.c new file mode 100644 index 0000000000..e1b932d942 --- /dev/null +++ b/src/southbridge/amd/cs5530/cs5530_ide.c @@ -0,0 +1,30 @@ +#include +#include +#include +#include +#include +#include "cs5530.h" + +static void ide_init(struct device *dev) +{ + printk_spew("cs5530_ide: %s\n", __FUNCTION__); +} + +static void ide_enable(struct device *dev) +{ + printk_spew("cs5530_ide: %s\n", __FUNCTION__); +} + +static struct device_operations ide_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init, + .enable = ide_enable, +}; + +static struct pci_driver ide_driver __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_CYRIX, + .device = PCI_DEVICE_ID_CYRIX_5530_IDE, +}; -- cgit v1.2.3