From d1b6ff80c017e671c1e2229ee0d659e491ab53f5 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sun, 10 Apr 2016 15:52:47 -0500 Subject: sb/amd/sp5100: Enable CPU reset timing option per RPR v3.02 Change-Id: Ifb568ca126283e533232f52175d6147ee500220c Signed-off-by: Timothy Pearson Reviewed-on: https://review.coreboot.org/14307 Tested-by: Raptor Engineering Automated Test Stand Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/southbridge/amd/sb700/early_setup.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/southbridge') diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 26ee8366ce..aae845fbf2 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -677,6 +677,11 @@ static void sb700_pmio_por_init(void) pmio_write(0xbb, byte); #if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 + /* RPR 2.26 Alter CPU reset timing */ + byte = pmio_read(0xb2); + byte |= 0x1 << 2; /* Enable CPU reset timing option */ + pmio_write(0xb2, byte); + /* Work around system clock drift issues */ byte = pmio_read(0xd4); byte |= 0x1 << 6; /* Enable alternate 14MHz clock source */ -- cgit v1.2.3