From cea4fd9bb059dab2a0c10b48b1c645807665eec2 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 3 Oct 2019 08:54:35 +0200 Subject: nb/intel/nehalem: Move romstage boilerplate to a common location MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move the mainboard_romstage_entry to a common location and provide mainboard specific callbacks. Change-Id: Ia827053617cead5d2cf8e9f06cb68c2cbb668ca9 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/35771 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/southbridge/intel/ibexpeak/pch.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/southbridge') diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 556b9e0a0b..fbe88a5d7c 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -65,6 +65,7 @@ int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf); void early_thermal_init(void); void southbridge_configure_default_intmap(void); void pch_setup_cir(int chipset_type); +void mainboard_lpc_init(void); enum current_lookup_idx { IF1_F57 = 0, @@ -84,9 +85,11 @@ struct southbridge_usb_port { enum current_lookup_idx current; int oc_pin; }; + void early_usb_init(const struct southbridge_usb_port *portmap); #ifndef __ROMCC__ +extern const struct southbridge_usb_port mainboard_usb_ports[14]; #include void pch_enable(struct device *dev); #endif -- cgit v1.2.3