From c70eed1e6202c928803f3e7f79161cd247a62b23 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Tue, 22 May 2018 02:18:00 +0300 Subject: device: Use pcidev_on_root() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc Signed-off-by: Kyösti Mälkki Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/26484 Tested-by: build bot (Jenkins) Reviewed-by: Piotr Król Reviewed-by: Arthur Heymans --- src/southbridge/amd/cimx/sb800/spi.c | 2 +- src/southbridge/amd/rs780/cmn.c | 4 ++-- src/southbridge/amd/rs780/gfx.c | 14 +++++++------- src/southbridge/amd/rs780/ht.c | 2 +- src/southbridge/amd/rs780/rs780.c | 4 ++-- src/southbridge/amd/sb700/ide.c | 2 +- src/southbridge/amd/sb700/lpc.c | 2 +- src/southbridge/amd/sb700/sata.c | 4 ++-- src/southbridge/amd/sb700/spi.c | 2 +- src/southbridge/amd/sb700/usb.c | 4 ++-- src/southbridge/amd/sb800/lpc.c | 2 +- src/southbridge/amd/sb800/sata.c | 2 +- src/southbridge/amd/sb800/usb.c | 2 +- src/southbridge/amd/sr5650/ht.c | 4 ++-- src/southbridge/amd/sr5650/pcie.c | 2 +- src/southbridge/amd/sr5650/sr5650.c | 14 +++++++------- src/southbridge/intel/bd82x6x/elog.c | 2 +- src/southbridge/intel/bd82x6x/lpc.c | 4 ++-- src/southbridge/intel/bd82x6x/pch.c | 12 ++++-------- src/southbridge/intel/bd82x6x/watchdog.c | 2 +- src/southbridge/intel/common/acpi_pirq_gen.c | 2 +- src/southbridge/intel/common/gpio.c | 2 +- src/southbridge/intel/common/pmbase.c | 2 +- src/southbridge/intel/common/rtc.c | 2 +- src/southbridge/intel/common/spi.c | 2 +- src/southbridge/intel/fsp_rangeley/soc.c | 4 ++-- src/southbridge/intel/fsp_rangeley/spi.c | 5 ++--- src/southbridge/intel/fsp_rangeley/watchdog.c | 2 +- src/southbridge/intel/i82801dx/smi.c | 8 ++++---- src/southbridge/intel/i82801gx/lpc.c | 2 +- src/southbridge/intel/i82801gx/sata.c | 2 +- src/southbridge/intel/i82801gx/watchdog.c | 2 +- src/southbridge/intel/i82801ix/i82801ix.c | 8 ++++---- src/southbridge/intel/i82801ix/lpc.c | 2 +- src/southbridge/intel/i82801ix/sata.c | 3 +-- src/southbridge/intel/i82801ix/smi.c | 9 +++++---- src/southbridge/intel/i82801ix/thermal.c | 2 +- src/southbridge/intel/i82801jx/i82801jx.c | 8 ++++---- src/southbridge/intel/i82801jx/lpc.c | 4 ++-- src/southbridge/intel/i82801jx/sata.c | 3 +-- src/southbridge/intel/i82801jx/thermal.c | 2 +- src/southbridge/intel/ibexpeak/lpc.c | 4 ++-- src/southbridge/intel/lynxpoint/early_pch.c | 2 +- src/southbridge/intel/lynxpoint/elog.c | 2 +- src/southbridge/intel/lynxpoint/lp_gpio.c | 2 +- src/southbridge/intel/lynxpoint/lpc.c | 4 ++-- src/southbridge/intel/lynxpoint/pch.c | 2 +- src/southbridge/intel/lynxpoint/watchdog.c | 2 +- src/southbridge/nvidia/ck804/ht.c | 2 +- 49 files changed, 88 insertions(+), 94 deletions(-) (limited to 'src/southbridge') diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index 574c0621db..8cfa24bbc5 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -50,7 +50,7 @@ void spi_init() { struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + dev = pcidev_on_root(0x14, 3); spibar = pci_read_config32(dev, 0xA0) & ~0x1F; } diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c index 16270d6d89..2ef9cd6bf2 100644 --- a/src/southbridge/amd/rs780/cmn.c +++ b/src/southbridge/amd/rs780/cmn.c @@ -192,8 +192,8 @@ void set_pcie_enable_bits(struct device *dev, u32 reg_pos, u32 mask, u32 val) void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add) { /* K8 Function1 is address map */ - struct device *k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1)); - struct device *k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + struct device *k8_f1 = pcidev_on_root(0x18, 1); + struct device *k8_f0 = pcidev_on_root(0x18, 0); if (in_out) { u32 dword, sblk; diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index 575a340894..8431223690 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -175,7 +175,7 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO) CIM_STATUS Status = CIM_UNSUPPORTED; u8 Bus, Dev, Reg, BusStart, BusEnd; u32 Value; - struct device *dev0x14 = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device *dev0x14 = pcidev_on_root(0x14, 4); struct device *tempdev; Value = pci_read_config32(dev0x14, 0x18); BusStart = (Value >> 8) & 0xFF; @@ -235,7 +235,7 @@ static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute) int i, j, n = 7; struct device *k8_f1; - k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + k8_f1 = pcidev_on_root(0x18, 1); for (i = 0; i < 8; i++) { int k = 0, MmioReg; @@ -787,7 +787,7 @@ static void rs780_internal_gfx_enable(struct device *dev) /* LPC DMA Deadlock workaround? */ /* GFX_InitCommon*/ - struct device *k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + struct device *k8_f0 = pcidev_on_root(0x18, 0); l_dword = pci_read_config32(k8_f0, 0x68); l_dword &= ~(3 << 21); l_dword |= (1 << 21); @@ -802,9 +802,9 @@ static void rs780_internal_gfx_enable(struct device *dev) #if IS_ENABLED(CONFIG_GFXUMA) /* GFX_InitUMA. */ /* Copy CPU DDR Controller to NB MC. */ - struct device *k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1)); - struct device *k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2)); - struct device *k8_f4 = dev_find_slot(0, PCI_DEVFN(0x18, 4)); + struct device *k8_f1 = pcidev_on_root(0x18, 1); + struct device *k8_f2 = pcidev_on_root(0x18, 2); + struct device *k8_f4 = pcidev_on_root(0x18, 4); for (i = 0; i < 12; i++) { l_dword = pci_read_config32(k8_f2, 0x40 + i * 4); nbmc_write_index(nb_dev, 0x30 + i, l_dword); @@ -1145,7 +1145,7 @@ static void dynamic_link_width_control(struct device *nb_dev, struct device *dev while (reg32 & 0x100); /* step 5.9.1.6 */ - sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0)); + sb_dev = pcidev_on_root(8, 0); do { reg32 = pci_ext_read_config32(nb_dev, sb_dev, PCIE_VC0_RESOURCE_STATUS); diff --git a/src/southbridge/amd/rs780/ht.c b/src/southbridge/amd/rs780/ht.c index 43fb899803..94df2337c1 100644 --- a/src/southbridge/amd/rs780/ht.c +++ b/src/southbridge/amd/rs780/ht.c @@ -26,7 +26,7 @@ void avoid_lpc_dma_deadlock(struct device *nb_dev, struct device *sb_dev) struct device *cpu_f0; u8 reg; - cpu_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + cpu_f0 = pcidev_on_root(0x18, 0); set_nbcfg_enable_bits(cpu_f0, 0x68, 3 << 21, 1 << 21); reg = nbpcie_p_read_index(sb_dev, 0x10); diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index a753da77be..c5e38c130c 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -271,14 +271,14 @@ void rs780_enable(struct device *dev) printk(BIOS_INFO, "rs780_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); - nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + nb_dev = pcidev_on_root(0, 0); if (!nb_dev) { die("rs780_enable: CAN NOT FIND RS780 DEVICE, HALT!\n"); /* NOT REACHED */ } /* sb_dev (dev 8) is a bridge that links to southbridge. */ - sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0)); + sb_dev = pcidev_on_root(8, 0); if (!sb_dev) { die("rs780_enable: CAN NOT FIND SB bridge, HALT!\n"); /* NOT REACHED */ diff --git a/src/southbridge/amd/sb700/ide.c b/src/southbridge/amd/sb700/ide.c index d08f2f1cb2..673464318c 100644 --- a/src/southbridge/amd/sb700/ide.c +++ b/src/southbridge/amd/sb700/ide.c @@ -56,7 +56,7 @@ static void ide_init(struct device *dev) /* set ide as primary, if you want to boot from IDE, you'd better set it * in $vendor/$mainboard/devicetree.cb */ if (conf->boot_switch_sata_ide == 1) { - struct device *sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + struct device *sm_dev = pcidev_on_root(0x14, 0); byte = pci_read_config8(sm_dev, 0xad); byte |= 1 << 4; pci_write_config8(sm_dev, 0xad, byte); diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 857503a7ed..eb0af0de1c 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -40,7 +40,7 @@ static void lpc_init(struct device *dev) printk(BIOS_SPEW, "%s\n", __func__); /* Enable the LPC Controller */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); dword = pci_read_config32(sm_dev, 0x64); dword |= 1 << 20; pci_write_config32(sm_dev, 0x64, dword); diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index 975e5ac132..f1c05f62f6 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -134,7 +134,7 @@ static void sata_init(struct device *dev) struct device *sm_dev; /* SATA SMBus Disable */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); /* WARNING * Enabling the SATA link latency enhancement (SMBUS 0xAD bit 5) @@ -171,7 +171,7 @@ static void sata_init(struct device *dev) struct device *ide_dev; /* IDE Device */ - ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); + ide_dev = pcidev_on_root(0x14, 1); /* Disable legacy IDE mode (enable PATA_BAR0/2) */ byte = pci_read_config8(ide_dev, 0x09); diff --git a/src/southbridge/amd/sb700/spi.c b/src/southbridge/amd/sb700/spi.c index 1fa29aa817..8dc142db45 100644 --- a/src/southbridge/amd/sb700/spi.c +++ b/src/southbridge/amd/sb700/spi.c @@ -31,7 +31,7 @@ static uint32_t get_spi_bar(void) { struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + dev = pcidev_on_root(0x14, 3); return pci_read_config32(dev, 0xa0) & ~0x1f; } diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c index bf790565ee..3ca12f6866 100644 --- a/src/southbridge/amd/sb700/usb.c +++ b/src/southbridge/amd/sb700/usb.c @@ -35,7 +35,7 @@ static void usb_init(struct device *dev) /* 6.1 Enable OHCI0-4 and EHCI Controllers */ struct device *sm_dev; - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); byte = pci_read_config8(sm_dev, 0x68); byte |= 0xFF; pci_write_config8(sm_dev, 0x68, byte); @@ -88,7 +88,7 @@ static void usb_init2(struct device *dev) if (get_option(&nvram, "ehci_async_data_cache") == CB_SUCCESS) ehci_async_data_cache = !!nvram; - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); rev = get_sb700_revision(sm_dev); /* dword = pci_read_config32(dev, 0xf8); */ diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 3bbf823ddb..e67dcd7464 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -35,7 +35,7 @@ static void lpc_init(struct device *dev) struct device *sm_dev; /* Enable the LPC Controller */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); dword = pci_read_config32(sm_dev, 0x64); dword |= 1 << 20; pci_write_config32(sm_dev, 0x64, dword); diff --git a/src/southbridge/amd/sb800/sata.c b/src/southbridge/amd/sb800/sata.c index 2186d37a41..acb899f6c2 100644 --- a/src/southbridge/amd/sb800/sata.c +++ b/src/southbridge/amd/sb800/sata.c @@ -88,7 +88,7 @@ static void sata_init(struct device *dev) struct device *sm_dev; /* SATA SMBus Disable */ /* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); /* get rev_id */ rev_id = pci_read_config8(sm_dev, 0x08) - 0x2F; diff --git a/src/southbridge/amd/sb800/usb.c b/src/southbridge/amd/sb800/usb.c index 715095f443..9850014de1 100644 --- a/src/southbridge/amd/sb800/usb.c +++ b/src/southbridge/amd/sb800/usb.c @@ -57,7 +57,7 @@ static void usb_init2(struct device *dev) void *usb2_bar0; struct device *sm_dev; - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); //rev = get_sb800_revision(sm_dev); /* dword = pci_read_config32(dev, 0xf8); */ diff --git a/src/southbridge/amd/sr5650/ht.c b/src/southbridge/amd/sr5650/ht.c index 1b4c99bc6f..f8db2b8c6d 100644 --- a/src/southbridge/amd/sr5650/ht.c +++ b/src/southbridge/amd/sr5650/ht.c @@ -187,8 +187,8 @@ static void sr5690_set_resources(struct device *dev) printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__); /* Find requisite AMD CPU devices */ - amd_ht_cfg_dev = dev_find_slot(0, PCI_DEVFN(0x18, 0)); - amd_addr_map_dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + amd_ht_cfg_dev = pcidev_on_root(0x18, 0); + amd_addr_map_dev = pcidev_on_root(0x18, 1); if (!amd_ht_cfg_dev || !amd_addr_map_dev) { printk(BIOS_WARNING, "%s: %s Unable to locate CPU control devices\n", __func__, dev_path(dev)); diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index 5084a122ce..9d4c689759 100644 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -843,7 +843,7 @@ static void lock_hwinitreg(struct device *nb_dev) */ void sr56x0_lock_hwinitreg(void) { - struct device *nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *nb_dev = pcidev_on_root(0, 0); /* Lock HWInit Register */ lock_hwinitreg(nb_dev); diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index 0f8b265781..119e4f3141 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -129,8 +129,8 @@ void l1cfg_ind_write_index(struct device *nb_dev, uint32_t index, uint32_t data) void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add) { /* K8 Function1 is address map */ - struct device *k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1)); - struct device *k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + struct device *k8_f1 = pcidev_on_root(0x18, 1); + struct device *k8_f0 = pcidev_on_root(0x18, 0); if (in_out) { u32 dword, sblk; @@ -331,7 +331,7 @@ void detect_and_enable_iommu(struct device *iommu_dev) { if (iommu) { printk(BIOS_DEBUG, "Initializing IOMMU\n"); - struct device *nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *nb_dev = pcidev_on_root(0, 0); if (!nb_dev) { printk(BIOS_WARNING, "Unable to find SR5690 device! IOMMU NOT initialized\n"); @@ -616,7 +616,7 @@ void sr5650_enable(struct device *dev) struct southbridge_amd_sr5650_config *cfg; printk(BIOS_INFO, "sr5650_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); - nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + nb_dev = pcidev_on_root(0, 0); if (!nb_dev) { die("sr5650_enable: CAN NOT FIND SR5650 DEVICE, HALT!\n"); /* NOT REACHED */ @@ -624,7 +624,7 @@ void sr5650_enable(struct device *dev) cfg = (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; /* sb_dev (dev 8) is a bridge that links to southbridge. */ - sb_dev = dev_find_slot(0, PCI_DEVFN(8, 0)); + sb_dev = pcidev_on_root(8, 0); if (!sb_dev) { die("sr5650_enable: CAN NOT FIND SB bridge, HALT!\n"); /* NOT REACHED */ @@ -823,14 +823,14 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) { uint8_t *p; - struct device *nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *nb_dev = pcidev_on_root(0, 0); if (!nb_dev) { printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate SR5650 " "device! IVRS table not generated...\n"); return (unsigned long)ivrs; } - struct device *iommu_dev = dev_find_slot(0, PCI_DEVFN(0, 2)); + struct device *iommu_dev = pcidev_on_root(0, 2); if (!iommu_dev) { printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate SR5650 " "IOMMU device! IVRS table not generated...\n"); diff --git a/src/southbridge/intel/bd82x6x/elog.c b/src/southbridge/intel/bd82x6x/elog.c index 2ccdf83c4d..ef345efb75 100644 --- a/src/southbridge/intel/bd82x6x/elog.c +++ b/src/southbridge/intel/bd82x6x/elog.c @@ -30,7 +30,7 @@ void pch_log_state(void) u32 gpe0_sts, gpe0_en; u8 gen_pmcon_2; int i; - struct device *lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *lpc = pcidev_on_root(0x1f, 0); if (!lpc) return; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 7ae538ebd2..d3da239321 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -738,7 +738,7 @@ static void southbridge_inject_dsdt(struct device *dev) void acpi_fill_fadt(acpi_fadt_t *fadt) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = pcidev_on_root(0x1f, 0); config_t *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; int c2_latency; @@ -875,7 +875,7 @@ static const char *lpc_acpi_name(const struct device *dev) static void southbridge_fill_ssdt(struct device *device) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = pcidev_on_root(0x1f, 0); config_t *chip = dev->chip_info; intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8); diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 00265d0219..1a646b17b9 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -32,11 +32,9 @@ int pch_silicon_revision(void) static int pch_revision_id = -1; #ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev; - dev = PCI_DEV(0, 0x1f, 0); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); #else - struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = pcidev_on_root(0x1f, 0); #endif if (pch_revision_id < 0) @@ -49,11 +47,9 @@ int pch_silicon_type(void) static int pch_type = -1; #ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev; - dev = PCI_DEV(0, 0x1f, 0); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); #else - struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = pcidev_on_root(0x1f, 0); #endif if (pch_type < 0) diff --git a/src/southbridge/intel/bd82x6x/watchdog.c b/src/southbridge/intel/bd82x6x/watchdog.c index eb4d38cd2c..c186f353ba 100644 --- a/src/southbridge/intel/bd82x6x/watchdog.c +++ b/src/southbridge/intel/bd82x6x/watchdog.c @@ -34,7 +34,7 @@ void watchdog_off(void) struct device *dev; /* Get LPC device. */ - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + dev = pcidev_on_root(0x1f, 0); /* Disable interrupt. */ value = pci_read_config16(dev, PCI_COMMAND); diff --git a/src/southbridge/intel/common/acpi_pirq_gen.c b/src/southbridge/intel/common/acpi_pirq_gen.c index 1f1a2ab258..6f28bc693f 100644 --- a/src/southbridge/intel/common/acpi_pirq_gen.c +++ b/src/southbridge/intel/common/acpi_pirq_gen.c @@ -32,7 +32,7 @@ static int create_pirq_matrix(char matrix[32][4]) struct device *dev; int num_devs = 0; - for (dev = dev_find_slot(0, PCI_DEVFN(0, 0)); dev; dev = dev->sibling) { + for (dev = pcidev_on_root(0, 0); dev; dev = dev->sibling) { u8 pci_dev; u8 int_pin; diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c index 7c8cfe8144..30c50283f6 100644 --- a/src/southbridge/intel/common/gpio.c +++ b/src/southbridge/intel/common/gpio.c @@ -31,7 +31,7 @@ #if defined(__SIMPLE_DEVICE__) #define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) #else -#define PCH_LPC_DEV dev_find_slot(0, PCI_DEVFN(0x1f, 0)) +#define PCH_LPC_DEV pcidev_on_root(0x1f, 0) #endif static u16 get_gpio_base(void) diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index 2de57d6da4..8b3274f524 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -33,7 +33,7 @@ #if defined(__SIMPLE_DEVICE__) #define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) #else -#define PCH_LPC_DEV dev_find_slot(0, PCI_DEVFN(0x1f, 0)) +#define PCH_LPC_DEV pcidev_on_root(0x1f, 0) #endif u16 lpc_get_pmbase(void) diff --git a/src/southbridge/intel/common/rtc.c b/src/southbridge/intel/common/rtc.c index e9ac2c2deb..1f0abeb450 100644 --- a/src/southbridge/intel/common/rtc.c +++ b/src/southbridge/intel/common/rtc.c @@ -27,7 +27,7 @@ #if defined(__SIMPLE_DEVICE__) #define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) #else -#define PCH_LPC_DEV dev_find_slot(0, PCI_DEVFN(0x1f, 0)) +#define PCH_LPC_DEV pcidev_on_root(0x1f, 0) #endif int rtc_failure(void) diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 3ca0d6c8d6..9bc34140a9 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -306,7 +306,7 @@ void spi_init(void) #ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 31, 0); #else - struct device *dev = dev_find_slot(0, PCI_DEVFN(31, 0)); + struct device *dev = pcidev_on_root(31, 0); #endif pci_read_config_dword(dev, 0xf0, &rcba); diff --git a/src/southbridge/intel/fsp_rangeley/soc.c b/src/southbridge/intel/fsp_rangeley/soc.c index 13b64c4e7f..fd83342ac7 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.c +++ b/src/southbridge/intel/fsp_rangeley/soc.c @@ -29,7 +29,7 @@ int soc_silicon_revision(void) { if (soc_revision_id < 0) soc_revision_id = pci_read_config8( - dev_find_slot(0, PCI_DEVFN(0x1f, 0)), + pcidev_on_root(0x1f, 0), PCI_REVISION_ID); return soc_revision_id; } @@ -38,7 +38,7 @@ int soc_silicon_type(void) { if (soc_type < 0) soc_type = pci_read_config8( - dev_find_slot(0, PCI_DEVFN(0x1f, 0)), + pcidev_on_root(0x1f, 0), PCI_DEVICE_ID + 1); return soc_type; } diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index 97548069ad..1571925027 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -341,14 +341,13 @@ void spi_init(void) { int ich_version = 0; uint8_t bios_cntl; - struct device *dev; uint32_t ids; uint16_t vendor_id, device_id; #ifdef __SMM__ - dev = PCI_DEV(0, 31, 0); + pci_devfn_t dev = PCI_DEV(0, 31, 0); #else - dev = dev_find_slot(0, PCI_DEVFN(31, 0)); + struct device *dev = pcidev_on_root(31, 0); #endif pci_read_config_dword(dev, 0, &ids); vendor_id = ids; diff --git a/src/southbridge/intel/fsp_rangeley/watchdog.c b/src/southbridge/intel/fsp_rangeley/watchdog.c index ff1c571505..d7d3141e59 100644 --- a/src/southbridge/intel/fsp_rangeley/watchdog.c +++ b/src/southbridge/intel/fsp_rangeley/watchdog.c @@ -29,7 +29,7 @@ void watchdog_off(void) u32 value, abase; /* Turn off the watchdog. */ - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + dev = pcidev_on_root(0x1f, 0); /* Enable I/O space. */ value = pci_read_config16(dev, 0x04); diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c index 0ff813e1ae..bdea66f9b3 100644 --- a/src/southbridge/intel/i82801dx/smi.c +++ b/src/southbridge/intel/i82801dx/smi.c @@ -238,7 +238,7 @@ static void smm_relocate(void) printk(BIOS_DEBUG, "Initializing SMM handler..."); - pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), 0x40) & 0xfffc; + pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffc; printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); smi_en = inl(pmbase + SMI_EN); @@ -317,7 +317,7 @@ static void smm_relocate(void) static void smm_install(void) { /* enable the SMM memory window */ - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, + pci_write_config8(pcidev_on_root(0, 0), SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG); /* copy the real SMM handler */ @@ -326,7 +326,7 @@ static void smm_install(void) wbinvd(); /* close the SMM memory window and enable normal SMM */ - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, + pci_write_config8(pcidev_on_root(0, 0), SMRAM, G_SMRAME | C_BASE_SEG); } @@ -354,7 +354,7 @@ void smm_lock(void) * make the SMM registers writable again. */ printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, + pci_write_config8(pcidev_on_root(0, 0), SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); } diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 7dcec507a8..c16b8a6649 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -487,7 +487,7 @@ unsigned long acpi_fill_madt(unsigned long current) void acpi_fill_fadt(acpi_fadt_t *fadt) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = pcidev_on_root(0x1f, 0); config_t *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 588d68701c..567c1e5047 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -28,7 +28,7 @@ static u8 get_ich7_sata_ports(void) { struct device *lpc; - lpc = dev_find_slot(0, PCI_DEVFN(31, 0)); + lpc = pcidev_on_root(31, 0); switch (pci_read_config16(lpc, PCI_DEVICE_ID)) { case 0x27b0: diff --git a/src/southbridge/intel/i82801gx/watchdog.c b/src/southbridge/intel/i82801gx/watchdog.c index ac2de3a66c..ff4da6412c 100644 --- a/src/southbridge/intel/i82801gx/watchdog.c +++ b/src/southbridge/intel/i82801gx/watchdog.c @@ -26,7 +26,7 @@ void watchdog_off(void) unsigned long value, base; /* Turn off the ICH7 watchdog. */ - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + dev = pcidev_on_root(0x1f, 0); /* Enable I/O space. */ value = pci_read_config16(dev, 0x04); diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index 797856ea78..46838fcbf4 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -58,7 +58,7 @@ static void i82801ix_pcie_init(const config_t *const info) /* PCIe - BIOS must program... */ for (i = 0; i < 6; ++i) { - pciePort[i] = dev_find_slot(0, PCI_DEVFN(0x1c, i)); + pciePort[i] = pcidev_on_root(0x1c, i); if (!pciePort[i]) { printk(BIOS_EMERG, "PCIe port 00:1c.%x", i); die(" is not listed in devicetree.\n"); @@ -68,7 +68,7 @@ static void i82801ix_pcie_init(const config_t *const info) pci_write_config8(pciePort[i], 0x324, 0x40); } - if (LPC_IS_MOBILE(dev_find_slot(0, PCI_DEVFN(0x1f, 0)))) { + if (LPC_IS_MOBILE(pcidev_on_root(0x1f, 0))) { for (i = 0; i < 6; ++i) { if (pciePort[i]->enabled) { reg32 = pci_read_config32(pciePort[i], 0xe8); @@ -116,10 +116,10 @@ static void i82801ix_pcie_init(const config_t *const info) static void i82801ix_ehci_init(void) { - struct device *const pciEHCI1 = dev_find_slot(0, PCI_DEVFN(0x1d, 7)); + struct device *const pciEHCI1 = pcidev_on_root(0x1d, 7); if (!pciEHCI1) die("EHCI controller (00:1d.7) not listed in devicetree.\n"); - struct device *const pciEHCI2 = dev_find_slot(0, PCI_DEVFN(0x1a, 7)); + struct device *const pciEHCI2 = pcidev_on_root(0x1a, 7); if (!pciEHCI2) die("EHCI controller (00:1a.7) not listed in devicetree.\n"); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 474c484ad6..b809a4e3b7 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -566,7 +566,7 @@ static const char *lpc_acpi_name(const struct device *dev) static void southbridge_fill_ssdt(struct device *device) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + struct device *dev = pcidev_on_root(0x1f, 0); config_t *chip = dev->chip_info; intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8); diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index e35babce28..e3b7e14b8c 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -213,8 +213,7 @@ static void sata_init(struct device *const dev) pci_write_config32(dev, 0x94, sclkcg); if (is_mobile && config->sata_traffic_monitor) { - struct device *const lpc_dev = dev_find_slot(0, - PCI_DEVFN(0x1f, 0)); + struct device *const lpc_dev = pcidev_on_root(0x1f, 0); if (((pci_read_config8(lpc_dev, D31F0_CxSTATE_CNF) >> 3) & 3) == 3) { u8 reg8 = pci_read_config8(dev, 0x9c); diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index 9dc9a3b989..74fa495695 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -50,7 +50,8 @@ static void smm_relocate(void) printk(BIOS_DEBUG, "Initializing SMM handler..."); - pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), D31F0_PMBASE) & 0xfffc; + pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), D31F0_PMBASE) & + 0xfffc; printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); smi_en = inl(pmbase + SMI_EN); @@ -138,7 +139,7 @@ static void smm_install(void) if (!acpi_is_wakeup_s3()) { /* enable the SMM memory window */ - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, + pci_write_config8(pcidev_on_root(0, 0), SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG); /* copy the real SMM handler */ @@ -148,7 +149,7 @@ static void smm_install(void) } /* close the SMM memory window and enable normal SMM */ - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, + pci_write_config8(pcidev_on_root(0, 0), SMRAM, G_SMRAME | C_BASE_SEG); } @@ -176,6 +177,6 @@ void smm_lock(void) * make the SMM registers writable again. */ printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, + pci_write_config8(pcidev_on_root(0, 0), SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); } diff --git a/src/southbridge/intel/i82801ix/thermal.c b/src/southbridge/intel/i82801ix/thermal.c index 5f40d2ec7c..931198254d 100644 --- a/src/southbridge/intel/i82801ix/thermal.c +++ b/src/southbridge/intel/i82801ix/thermal.c @@ -24,7 +24,7 @@ static void thermal_init(struct device *dev) { - if (LPC_IS_MOBILE(dev_find_slot(0, PCI_DEVFN(0x1f, 0)))) + if (LPC_IS_MOBILE(pcidev_on_root(0x1f, 0))) return; u8 reg8; diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c index 31df5c4d14..2f3ed4b195 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.c +++ b/src/southbridge/intel/i82801jx/i82801jx.c @@ -57,7 +57,7 @@ static void i82801jx_pcie_init(const config_t *const info) /* PCIe - BIOS must program... */ for (i = 0; i < 6; ++i) { - pciePort[i] = dev_find_slot(0, PCI_DEVFN(0x1c, i)); + pciePort[i] = pcidev_on_root(0x1c, i); if (!pciePort[i]) { printk(BIOS_EMERG, "PCIe port 00:1c.%x", i); die(" is not listed in devicetree.\n"); @@ -67,7 +67,7 @@ static void i82801jx_pcie_init(const config_t *const info) pci_write_config8(pciePort[i], 0x324, 0x40); } - if (LPC_IS_MOBILE(dev_find_slot(0, PCI_DEVFN(0x1f, 0)))) { + if (LPC_IS_MOBILE(pcidev_on_root(0x1f, 0))) { for (i = 0; i < 6; ++i) { if (pciePort[i]->enabled) { reg32 = pci_read_config32(pciePort[i], 0xe8); @@ -115,10 +115,10 @@ static void i82801jx_pcie_init(const config_t *const info) static void i82801jx_ehci_init(void) { - struct device *const pciEHCI1 = dev_find_slot(0, PCI_DEVFN(0x1d, 7)); + struct device *const pciEHCI1 = pcidev_on_root(0x1d, 7); if (!pciEHCI1) die("EHCI controller (00:1d.7) not listed in devicetree.\n"); - struct device *const pciEHCI2 = dev_find_slot(0, PCI_DEVFN(0x1a, 7)); + struct device *const pciEHCI2 = pcidev_on_root(0x1a, 7); if (!pciEHCI2) die("EHCI controller (00:1a.7) not listed in devicetree.\n"); diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index b9f2e4bffc..2ff2acd095 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -501,7 +501,7 @@ unsigned long acpi_fill_madt(unsigned long current) void acpi_fill_fadt(acpi_fadt_t *fadt) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = pcidev_on_root(0x1f, 0); config_t *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; @@ -727,7 +727,7 @@ static const char *lpc_acpi_name(const struct device *dev) static void southbridge_fill_ssdt(struct device *device) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + struct device *dev = pcidev_on_root(0x1f, 0); config_t *chip = dev->chip_info; intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8); diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index b511c54d57..5978294616 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -208,8 +208,7 @@ static void sata_init(struct device *const dev) pci_write_config32(dev, 0x94, sclkcg); if (is_mobile && config->sata_traffic_monitor) { - struct device *const lpc_dev = dev_find_slot(0, - PCI_DEVFN(0x1f, 0)); + struct device *const lpc_dev = pcidev_on_root(0x1f, 0); if (((pci_read_config8(lpc_dev, D31F0_CxSTATE_CNF) >> 3) & 3) == 3) { u8 reg8 = pci_read_config8(dev, 0x9c); diff --git a/src/southbridge/intel/i82801jx/thermal.c b/src/southbridge/intel/i82801jx/thermal.c index ae111a6e07..4a8ba290f3 100644 --- a/src/southbridge/intel/i82801jx/thermal.c +++ b/src/southbridge/intel/i82801jx/thermal.c @@ -24,7 +24,7 @@ static void thermal_init(struct device *dev) { - if (LPC_IS_MOBILE(dev_find_slot(0, PCI_DEVFN(0x1f, 0)))) + if (LPC_IS_MOBILE(pcidev_on_root(0x1f, 0))) return; u8 reg8; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index e5cbc594ae..24a217d284 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -647,7 +647,7 @@ static void southbridge_inject_dsdt(struct device *dev) void acpi_fill_fadt(acpi_fadt_t *fadt) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + struct device *dev = pcidev_on_root(0x1f, 0); config_t *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; int c2_latency; @@ -783,7 +783,7 @@ static const char *lpc_acpi_name(const struct device *dev) static void southbridge_fill_ssdt(struct device *device) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + struct device *dev = pcidev_on_root(0x1f, 0); config_t *chip = dev->chip_info; intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8); diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 27a3b2954c..46e803d82f 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -99,7 +99,7 @@ static int sleep_type_s3(void) void pch_enable_lpc(void) { - const struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + const struct device *dev = pcidev_on_root(0x1f, 0); const struct southbridge_intel_lynxpoint_config *config = NULL; /* Set COM1/COM2 decode range */ diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c index c575db0693..e16e1be18a 100644 --- a/src/southbridge/intel/lynxpoint/elog.c +++ b/src/southbridge/intel/lynxpoint/elog.c @@ -112,7 +112,7 @@ void pch_log_state(void) { u16 pm1_sts, gen_pmcon_3, tco2_sts; u8 gen_pmcon_2; - struct device *lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *lpc = pcidev_on_root(0x1f, 0); if (!lpc) return; diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c index 2b07de2735..b6edc8da1f 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.c +++ b/src/southbridge/intel/lynxpoint/lp_gpio.c @@ -27,7 +27,7 @@ static u16 get_gpio_base(void) #if defined(__PRE_RAM__) || defined(__SMM__) return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; #else - return pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), + return pci_read_config16(pcidev_on_root(0x1f, 0), GPIO_BASE) & 0xfffc; #endif } diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index f0fc22deaf..5b48da0848 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -456,7 +456,7 @@ static void enable_lp_clock_gating(struct device *dev) RCBA32_AND_OR(0x2614, 0x8bffffff, 0x0a206500); /* Check for LPT-LP B2 stepping and 0:31.0@0xFA > 4 */ - if (pci_read_config8(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x8) >= 0x0b) + if (pci_read_config8(pcidev_on_root(2, 0), 0x8) >= 0x0b) RCBA32_OR(0x2614, (1 << 26)); RCBA32_OR(0x900, 0x0000031f); @@ -775,7 +775,7 @@ static void southbridge_inject_dsdt(struct device *dev) void acpi_fill_fadt(acpi_fadt_t *fadt) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = pcidev_on_root(0x1f, 0); struct southbridge_intel_lynxpoint_config *cfg = dev->chip_info; u16 pmbase = get_pmbase(); diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 1fb6d7ad54..b197bbcfc4 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -31,7 +31,7 @@ static pci_devfn_t pch_get_lpc_device(void) #else static struct device *pch_get_lpc_device(void) { - return dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + return pcidev_on_root(0x1f, 0); } #endif diff --git a/src/southbridge/intel/lynxpoint/watchdog.c b/src/southbridge/intel/lynxpoint/watchdog.c index 9a867e413a..ec7cb5d0b5 100644 --- a/src/southbridge/intel/lynxpoint/watchdog.c +++ b/src/southbridge/intel/lynxpoint/watchdog.c @@ -32,7 +32,7 @@ void watchdog_off(void) unsigned long value, base; /* Turn off the ICH7 watchdog. */ - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + dev = pcidev_on_root(0x1f, 0); /* Enable I/O space. */ value = pci_read_config16(dev, 0x04); diff --git a/src/southbridge/nvidia/ck804/ht.c b/src/southbridge/nvidia/ck804/ht.c index 48b18cb636..6028cd663f 100644 --- a/src/southbridge/nvidia/ck804/ht.c +++ b/src/southbridge/nvidia/ck804/ht.c @@ -29,7 +29,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) struct device *dev; unsigned long mcfg_base; - dev = dev_find_slot(0x0, PCI_DEVFN(0x0,0)); + dev = pcidev_on_root(0x0, 0); if (!dev) return current; -- cgit v1.2.3