From c46242f904b64daee36e6d478e1d88c623fb3c44 Mon Sep 17 00:00:00 2001 From: Elyes Haouas Date: Sun, 19 Mar 2023 07:43:32 +0100 Subject: sb/intel/i82801gx/chip.h: Use 'bool' instead of 'int' This to fix following error using Clang-16.0.0: /cb-build/coreboot-toolchain.0/clang/APPLE_IMAC52/mainboard/apple/macbook21/static.c:66:19: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .c4onc3_enable = 1, ^ /cb-build/coreboot-toolchain.0/clang/APPLE_IMAC52/mainboard/apple/macbook21/static.c:75:32: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .p_cnt_throttling_supported = 1, ^ Change-Id: I691b51a97b359655c406bff28ee6562636d11015 Signed-off-by: Elyes Haouas Reviewed-on: https://review.coreboot.org/c/coreboot/+/73796 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- src/southbridge/intel/i82801gx/chip.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/southbridge') diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index ba8dd6f438..04b82d321b 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -63,9 +63,9 @@ struct southbridge_intel_i82801gx_config { /* Enable linear PCIe Root Port function numbers starting at zero */ bool pcie_port_coalesce; - int c4onc3_enable:1; - int docking_supported:1; - int p_cnt_throttling_supported:1; + bool c4onc3_enable; + bool docking_supported; + bool p_cnt_throttling_supported; int c3_latency; /* Additional LPC IO decode ranges */ -- cgit v1.2.3