From b486f29a4452227c3dd9ee676eda41775afd8b96 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Thu, 18 Jun 2020 14:05:35 +0300
Subject: cpu/x86/smm: Define APM_CNT_ROUTE_ALL_XHCI
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Change-Id: I0bc321f499278e0cdbfb40be9a2b2ae21828d2f4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/southbridge/intel/lynxpoint/smihandler.c | 2 +-
 src/southbridge/intel/lynxpoint/usb_xhci.c   | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'src/southbridge')

diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index 8bbe3feaa4..be842c5720 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -330,7 +330,7 @@ static void southbridge_smi_apmc(void)
 			printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
 		}
 		break;
-	case 0xca:
+	case APM_CNT_ROUTE_ALL_XHCI:
 		usb_xhci_route_all();
 		break;
 	case APM_CNT_ELOG_GSMI:
diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c
index 8684aa9b32..1cfec1b476 100644
--- a/src/southbridge/intel/lynxpoint/usb_xhci.c
+++ b/src/southbridge/intel/lynxpoint/usb_xhci.c
@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <cpu/x86/smm.h>
 #include <delay.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <arch/io.h>
 #include <device/mmio.h>
 #include <device/pci_ops.h>
 #include "chip.h"
@@ -356,7 +356,7 @@ static void usb_xhci_init(struct device *dev)
 		usb_xhci_reset_usb3(dev, 0);
 	} else if (config->xhci_default) {
 		/* Route all ports to XHCI */
-		outb(0xca, 0xb2);
+		apm_control(APM_CNT_ROUTE_ALL_XHCI);
 	}
 }
 
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