From b196834b620008651b6dcf1dbf2d39aff7514b33 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 17 Jan 2022 13:57:55 +0200 Subject: sb/intel/i82801dx: Add call i8259_setup() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Observed with aopen/dxplplusu that without SeaBIOS (using GRUB2 payload) Linux kernel panics. < [ 0.000000] Using NULL legacy PIC < [ 0.000000] NR_IRQS: 2304, nr_irqs: 1024, preallocated irqs: 0 ... < [ 0.000000] unexpected #NM exception: ffff [#1] SMP PTI versus > [ 0.000000] NR_IRQS: 2304, nr_irqs: 1024, preallocated irqs: 16 ... > [ 0.004000] Enabling APIC mode: Flat. Using 3 I/O APICs > [ 0.008000] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=0 pin2=0 > [ 0.028000] tsc: Fast TSC calibration using PIT > [ 0.032000] tsc: Detected 3198.436 MHz processor Change-Id: I1beb93a8fd04697f259aefddfd369aa79e3359b7 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/61465 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- src/southbridge/intel/i82801dx/lpc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'src/southbridge') diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 34d93c4800..bb38e1ab56 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include #include #include @@ -8,8 +10,7 @@ #include #include #include -#include -#include +#include #include "chip.h" #include "i82801dx.h" @@ -273,6 +274,8 @@ static void lpc_init(struct device *dev) /* Initialize the High Precision Event Timers */ enable_hpet(dev); + setup_i8259(); + /* Don't allow evil boot loaders, kernels, or * userspace applications to deceive us: */ -- cgit v1.2.3