From adc4753a8d8c5dc7462547ab148c2d63eabbe4fa Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 28 Dec 2018 15:48:58 +0100 Subject: usbdebug: Make the EHCI debug console work in the bootblock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently this needlessly initializes the hardware in the both the romstage and the bootblock, but it works. Build option is renamed to USBDEBUG_IN_PRE_RAM to reflect the use better, related support files can be built to pre-ram stages regardless of usbdebug being enabled or not. Tested on Google/peppy (adapted to C_ENVIRONMENT_BOOTBLOCK). Change-Id: Ib77f2fc7f3d8fa524405601bae15cce9f76ffc6f Signed-off-by: Arthur Heymans Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/30480 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/amd/agesa/hudson/Makefile.inc | 4 +++- src/southbridge/amd/cimx/sb800/Makefile.inc | 3 ++- src/southbridge/amd/pi/hudson/Makefile.inc | 4 +++- src/southbridge/amd/sb700/Makefile.inc | 4 +++- src/southbridge/amd/sb800/Makefile.inc | 4 +++- src/southbridge/intel/common/Makefile.inc | 3 ++- src/southbridge/intel/fsp_rangeley/Makefile.inc | 1 + src/southbridge/intel/fsp_rangeley/romstage.c | 2 +- src/southbridge/nvidia/ck804/Makefile.inc | 3 ++- src/southbridge/nvidia/mcp55/Makefile.inc | 3 ++- 10 files changed, 22 insertions(+), 9 deletions(-) (limited to 'src/southbridge') diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 2bf6f02539..5d3d5b4ad4 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -16,7 +16,9 @@ ramstage-y += sd.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c -romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c + +bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c +romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_setup.c diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index a5287fa231..418110b5e0 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -34,7 +34,8 @@ postcar-y += ramtop.c romstage-y += ramtop.c ramstage-y += ramtop.c -romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ../../sb800/enable_usbdebug.c +bootblock-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c +romstage-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c ramstage-y += smbus.c diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 251cb6cbc5..c7cd757da2 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -28,8 +28,10 @@ # #***************************************************************************** +bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c + romstage-y += early_setup.c -romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c +romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-$(CONFIG_HUDSON_IMC_FWM) += imc.c romstage-y += smbus.c romstage-y += smbus_spd.c diff --git a/src/southbridge/amd/sb700/Makefile.inc b/src/southbridge/amd/sb700/Makefile.inc index d93c9a6d5e..17d0a3abc0 100644 --- a/src/southbridge/amd/sb700/Makefile.inc +++ b/src/southbridge/amd/sb700/Makefile.inc @@ -13,7 +13,9 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c romstage-y += reset.c ramstage-y += reset.c ramstage-y += spi.c -romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c + +bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c +romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_setup.c diff --git a/src/southbridge/amd/sb800/Makefile.inc b/src/southbridge/amd/sb800/Makefile.inc index e5cdb56c8d..fd2577ce39 100644 --- a/src/southbridge/amd/sb800/Makefile.inc +++ b/src/southbridge/amd/sb800/Makefile.inc @@ -11,7 +11,9 @@ ramstage-y += pci.c ramstage-y += pcie.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c -romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c + +bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c +romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += ramtop.c diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 1a509b16a4..3224e1fcf1 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -29,7 +29,8 @@ ramstage-y += pmbase.c postcar-y += pmbase.c smm-y += pmbase.c -romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c +bootblock-$(CONFIG_USBDEBUG) += usb_debug.c +romstage-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c diff --git a/src/southbridge/intel/fsp_rangeley/Makefile.inc b/src/southbridge/intel/fsp_rangeley/Makefile.inc index ace227c92e..ac5888ca38 100644 --- a/src/southbridge/intel/fsp_rangeley/Makefile.inc +++ b/src/southbridge/intel/fsp_rangeley/Makefile.inc @@ -27,6 +27,7 @@ ramstage-y += acpi.c romstage-y += early_usb.c early_smbus.c gpio.c early_spi.c early_init.c romstage-y += romstage.c +bootblock-$(CONFIG_USBDEBUG) += usb_debug.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index bf92049479..0032fd6715 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -101,7 +101,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { __func__, (u32) status, (u32) hob_list_ptr); /* FSP reconfigures USB, so reinit it to have debug */ - if (IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)) + if (IS_ENABLED(CONFIG_USBDEBUG_IN_PRE_RAM)) usbdebug_hw_init(true); printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc index 554a4407f0..68495c5f1b 100644 --- a/src/southbridge/nvidia/ck804/Makefile.inc +++ b/src/southbridge/nvidia/ck804/Makefile.inc @@ -17,7 +17,8 @@ ramstage-y += reset.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c -romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c +bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c +romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_smbus.c diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc index 7073b6974e..db0b3100ec 100644 --- a/src/southbridge/nvidia/mcp55/Makefile.inc +++ b/src/southbridge/nvidia/mcp55/Makefile.inc @@ -17,7 +17,8 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c -romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c +bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c +romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_smbus.c romstage-y += early_ctrl.c -- cgit v1.2.3