From 9646cfe989a096372a717d8ef16ce5096d1b2708 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 9 May 2019 13:24:14 +0200 Subject: sb/bd82x6x: Don't rewrite over BCTRL PCI_MIN_GNT is defined at offset 0x3e in which does not apply to this PCI bridge because it is only defined for "Header type 0 (normal devices)" (line 82). Some lines obove that code line, the "write" on BCTRL is already done. Change-Id: I8f1b98ba627947ab6652a4ba31d2acb159dd3e32 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/32700 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/southbridge/intel/bd82x6x/pci.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'src/southbridge') diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index c3b82577e1..2186287df2 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -47,9 +47,6 @@ static void pci_init(struct device *dev) reg8 |= (0x04 << 3); pci_write_config8(dev, SMLT, reg8); - /* Will this improve throughput of bus masters? */ - pci_write_config8(dev, PCI_MIN_GNT, 0x06); - /* Clear errors in status registers */ reg16 = pci_read_config16(dev, PSTS); //reg16 |= 0xf900; -- cgit v1.2.3