From 8c2cc68b1ac9e1fb2011bcb669df04b4c8cad351 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 29 Jun 2020 05:57:12 +0300 Subject: arch/x86: Pass GNVS as parameter to SMM module MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I9d7417462830443f9c96273d2cc326cbcc3b17dd Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/48698 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/southbridge/intel/bd82x6x/lpc.c | 2 -- src/southbridge/intel/bd82x6x/smihandler.c | 17 ----------------- src/southbridge/intel/common/pmutil.h | 3 --- src/southbridge/intel/common/smihandler.c | 12 +----------- src/southbridge/intel/i82801gx/lpc.c | 2 -- src/southbridge/intel/i82801gx/smihandler.c | 5 ----- src/southbridge/intel/i82801ix/lpc.c | 2 -- src/southbridge/intel/i82801ix/smihandler.c | 4 ---- src/southbridge/intel/i82801jx/lpc.c | 2 -- src/southbridge/intel/i82801jx/smihandler.c | 5 ----- src/southbridge/intel/ibexpeak/lpc.c | 2 -- src/southbridge/intel/ibexpeak/smihandler.c | 16 ---------------- src/southbridge/intel/lynxpoint/lpc.c | 2 -- src/southbridge/intel/lynxpoint/smihandler.c | 21 --------------------- 14 files changed, 1 insertion(+), 94 deletions(-) (limited to 'src/southbridge') diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 8af80654e9..4515261ad2 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -659,8 +659,6 @@ void southbridge_inject_dsdt(const struct device *dev) chromeos_init_chromeos_acpi(&(gnvs->chromeos)); #endif - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ acpigen_write_scope("\\"); diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 40672f87cd..1a9e5b4252 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -185,23 +185,6 @@ void southbridge_smm_xhci_sleep(u8 slp_type) xhci_sleep(slp_type); } -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - em64t101_smm_state_save_area_t *state = - smi_apmc_find_state_save(apm_cnt); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); - struct region r = {(uintptr_t)gnvs, sizeof(struct global_nvs)}; - if (smm_region_overlaps_handler(&r)) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - *smm_done = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } -} - void southbridge_finalize_all(void) { intel_me_finalize_smm(); diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index c1756474ae..c9cf544f4e 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -4,7 +4,6 @@ #define INTEL_COMMON_PMUTIL_H #include -#include #define D31F0_PMBASE 0x40 #define D31F0_GEN_PMCON_1 0xa0 @@ -129,10 +128,8 @@ void dump_all_status(void); void southbridge_smm_xhci_sleep(u8 slp_type); void gpi_route_interrupt(u8 gpi, u8 mode); void southbridge_gate_memory_reset(void); -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done); void southbridge_finalize_all(void); void southbridge_smi_monitor(void); -em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd); void pch_log_state(void); #endif /*INTEL_COMMON_PMUTIL_H */ diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 7610aa1102..d59e29cdd9 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -17,8 +17,6 @@ #include "pmutil.h" -static int smm_initialized = 0; - u16 get_pmbase(void) { return lpc_get_pmbase(); @@ -198,7 +196,7 @@ static void southbridge_smi_sleep(void) * core in case we are not running on the same core that * initiated the IO transaction. */ -em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) +static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) { em64t101_smm_state_save_area_t *state; int node; @@ -302,14 +300,6 @@ static void southbridge_smi_apmc(void) write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); - return; - } - southbridge_update_gnvs(reg8, &smm_initialized); - break; case APM_CNT_FINALIZE: if (mainboard_finalized) { printk(BIOS_DEBUG, "SMI#: Already finalized\n"); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 9ac894254c..4db93511fc 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -491,8 +491,6 @@ void southbridge_inject_dsdt(const struct device *dev) acpi_create_gnvs(gnvs); - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); /* Add it to SSDT. */ acpigen_write_scope("\\"); diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index f1be5c200b..03480a7903 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -19,11 +19,6 @@ /* While we read PMBASE dynamically in case it changed, let's initialize it with a sane value */ u16 pmbase = DEFAULT_PMBASE; -u8 smm_initialized = 0; - -/* This implementation was removed since it was invalid. There will be one shared - approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */ -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { } int southbridge_io_trap_handler(int smif) { diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 652da54103..821a0b7386 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -461,8 +461,6 @@ void southbridge_inject_dsdt(const struct device *dev) memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); /* Add it to SSDT. */ acpigen_write_scope("\\"); diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 537e544f94..046cc2b5d5 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -14,10 +14,6 @@ struct global_nvs *gnvs; #endif -/* This implementation was removed since it was invalid. There will be one shared - approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */ -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { } - int southbridge_io_trap_handler(int smif) { switch (smif) { diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 1f4cf29187..ad9bac1da6 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -485,8 +485,6 @@ void southbridge_inject_dsdt(const struct device *dev) memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); /* Add it to SSDT. */ acpigen_write_scope("\\"); diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 7d79620114..6a6c5b4c7f 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -13,11 +13,6 @@ * initialize it with a sane value */ u16 pmbase = DEFAULT_PMBASE; -u8 smm_initialized = 0; - -/* This implementation was removed since it was invalid. There will be one shared - approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */ -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { } int southbridge_io_trap_handler(int smif) { diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index d2a3404880..0895dddec5 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -555,8 +555,6 @@ void southbridge_inject_dsdt(const struct device *dev) gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu(); - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); /* Add it to SSDT. */ acpigen_write_scope("\\"); diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 0c5e954c72..e83a9de2fb 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -147,22 +147,6 @@ void southbridge_smi_monitor(void) #undef IOTRAP } -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - em64t101_smm_state_save_area_t *state = - smi_apmc_find_state_save(apm_cnt); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)(uintptr_t)((u32)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - *smm_done = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } -} - void southbridge_finalize_all(void) { intel_me_finalize_smm(); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 915c181c2f..586e626bba 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -712,8 +712,6 @@ void southbridge_inject_dsdt(const struct device *dev) /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); - /* And tell SMI about it */ - apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ acpigen_write_scope("\\"); diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 9c68a54f06..bd445008d3 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -19,8 +19,6 @@ #include "pch.h" #include "nvs.h" -static u8 smm_initialized = 0; - int southbridge_io_trap_handler(int smif) { switch (smif) { @@ -262,7 +260,6 @@ static void southbridge_smi_store(void) static void southbridge_smi_apmc(void) { u8 reg8; - em64t101_smm_state_save_area_t *state; static int chipset_finalized = 0; /* Emulate B2 register as the FADT / Linux expects it */ @@ -304,24 +301,6 @@ static void southbridge_smi_apmc(void) enable_pm1_control(SCI_EN); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_GNVS_UPDATE: - if (smm_initialized) { - printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); - return; - } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); - if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { - printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); - return; - } - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } - break; case APM_CNT_ROUTE_ALL_XHCI: usb_xhci_route_all(); break; -- cgit v1.2.3