From 8a41f4b71e883ec66be511cb592ee19dfa6708c5 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Fri, 8 Feb 2019 18:14:34 +0200 Subject: device/pci_ops: Move questionable pci_locate() variants MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are defined for __SIMPLE_DEVICE__ when PCI enumeration has not happened yet. These should not really try to probe devices other than those on bus 0. It's hard to track but there maybe cases of southbridge being located on bus 2 and available for configuration, so I rather leave the code unchanged. Just move these out of arch/io.h because they cause build failures if one attempts to include before . There are two direct copies for ROMCC bootblocks to avoid inlining them elsewhere. Change-Id: Ida2919a5d83fe5ea89284ffbd8ead382e4312524 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/31304 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/southbridge/amd/amd8111/bootblock.c | 15 +++++++++++++++ src/southbridge/amd/amd8111/reset.c | 1 + src/southbridge/amd/sb700/early_setup.c | 1 + src/southbridge/broadcom/bcm5785/bootblock.c | 15 +++++++++++++++ src/southbridge/intel/i82371eb/bootblock.c | 15 +++++++++++++++ src/southbridge/intel/i82371eb/early_pm.c | 1 + src/southbridge/intel/i82371eb/early_smbus.c | 1 + src/southbridge/nvidia/ck804/early_smbus.c | 1 + src/southbridge/nvidia/mcp55/early_smbus.c | 1 + 9 files changed, 51 insertions(+) (limited to 'src/southbridge') diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c index 2c722c82b8..0abd999efe 100644 --- a/src/southbridge/amd/amd8111/bootblock.c +++ b/src/southbridge/amd/amd8111/bootblock.c @@ -17,6 +17,21 @@ #include #include #include +#include + +#define PCI_ID(VENDOR_ID, DEVICE_ID) \ + ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) + +static pci_devfn_t pci_io_locate_device(unsigned int pci_id, pci_devfn_t dev) +{ + for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) { + unsigned int id; + id = pci_io_read_config32(dev, 0); + if (id == pci_id) + return dev; + } + return PCI_DEV_INVALID; +} /* Enable 5MB ROM access at 0xFFB00000 - 0xFFFFFFFF. */ static void amd8111_enable_rom(void) diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c index 41d9880f59..62ae99e414 100644 --- a/src/southbridge/amd/amd8111/reset.c +++ b/src/southbridge/amd/amd8111/reset.c @@ -16,6 +16,7 @@ #include #include +#include #include diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 70cf340c8e..167986fa67 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include "sb700.h" diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c index 2861ff0cc1..62b20a3f7b 100644 --- a/src/southbridge/broadcom/bcm5785/bootblock.c +++ b/src/southbridge/broadcom/bcm5785/bootblock.c @@ -17,6 +17,21 @@ #include #include #include +#include + +#define PCI_ID(VENDOR_ID, DEVICE_ID) \ + ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) + +static pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev) +{ + for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) { + unsigned int id; + id = pci_read_config32(dev, 0); + if (id == pci_id) + return dev; + } + return PCI_DEV_INVALID; +} /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ static void bcm5785_enable_rom(void) diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index c59343df91..38b797d5a6 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -17,8 +17,23 @@ #include #include #include +#include #include "i82371eb.h" +#define PCI_ID(VENDOR_ID, DEVICE_ID) \ + ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) + +static pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev) +{ + for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) { + unsigned int id; + id = pci_read_config32(dev, 0); + if (id == pci_id) + return dev; + } + return PCI_DEV_INVALID; +} + static void bootblock_southbridge_init(void) { u16 reg16; diff --git a/src/southbridge/intel/i82371eb/early_pm.c b/src/southbridge/intel/i82371eb/early_pm.c index 8ae7669f33..720cb0d013 100644 --- a/src/southbridge/intel/i82371eb/early_pm.c +++ b/src/southbridge/intel/i82371eb/early_pm.c @@ -16,6 +16,7 @@ #include #include +#include #include #include #include "i82371eb.h" diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index de16717416..4e91c0aabf 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -16,6 +16,7 @@ #include #include +#include #include #include #include diff --git a/src/southbridge/nvidia/ck804/early_smbus.c b/src/southbridge/nvidia/ck804/early_smbus.c index 51e200b598..f7bddbf674 100644 --- a/src/southbridge/nvidia/ck804/early_smbus.c +++ b/src/southbridge/nvidia/ck804/early_smbus.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include diff --git a/src/southbridge/nvidia/mcp55/early_smbus.c b/src/southbridge/nvidia/mcp55/early_smbus.c index a849ebab92..f52d079a12 100644 --- a/src/southbridge/nvidia/mcp55/early_smbus.c +++ b/src/southbridge/nvidia/mcp55/early_smbus.c @@ -19,6 +19,7 @@ #include #include +#include #include "smbus.h" #include "mcp55.h" -- cgit v1.2.3