From 851fe8334e75d1b3f372f7878745d65c236a12a4 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 10 Aug 2020 13:52:21 +0200 Subject: sb/intel/i82801jx: Drop is-mobile checks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There's no mobile ICH10 variant. This was copied from i82801ix. Change-Id: I141da407e336f6fbbf84d0e2cee55b0c12931c7b Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/44335 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Michael Niewöhner --- src/southbridge/intel/i82801jx/i82801jx.c | 8 -------- src/southbridge/intel/i82801jx/i82801jx.h | 6 ------ src/southbridge/intel/i82801jx/lpc.c | 17 ----------------- src/southbridge/intel/i82801jx/thermal.c | 3 --- 4 files changed, 34 deletions(-) (limited to 'src/southbridge') diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c index a332ec079b..6f90301419 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.c +++ b/src/southbridge/intel/i82801jx/i82801jx.c @@ -46,14 +46,6 @@ static void i82801jx_pcie_init(const config_t *const info) pci_write_config8(pciePort[i], 0x324, 0x40); } - if (LPC_IS_MOBILE(pcidev_on_root(0x1f, 0))) { - for (i = 0; i < 6; ++i) { - if (pciePort[i]->enabled) { - pci_or_config32(pciePort[i], 0xe8, 1); - } - } - } - for (i = 5; (i >= 0) && !pciePort[i]->enabled; --i) { /* Only for the top disabled ports. */ pci_or_config32(pciePort[i], 0x300, 0x3 << 16); diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 0a353de6ff..b3cab9154a 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -169,12 +169,6 @@ #include -static inline int lpc_is_mobile(const u16 devid) -{ - return (devid == 0x2917) || (devid == 0x2919); -} -#define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID)) - void i82801jx_lpc_setup(void); void i82801jx_setup_bars(void); void i82801jx_early_init(void); diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index a8b53706c1..3bed5ddcc2 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -276,19 +276,6 @@ static void i82801jx_power_options(struct device *dev) outl(reg32, pmbase + 0x10); } -static void i82801jx_configure_cstates(struct device *dev) -{ - // Enable Popup & Popdown - pci_or_config8(dev, D31F0_CxSTATE_CNF, (1 << 4) | (1 << 3) | (1 << 2)); - - // Set Deeper Sleep configuration to recommended values - // Deeper Sleep to Stop CPU: 34-40us - // Deeper Sleep to Sleep: 15us - pci_update_config8(dev, D31F0_C4TIMING_CNT, ~0x0f, (2 << 2) | (2 << 0)); - - /* We could enable slow-C4 exit here, if someone needs it? */ -} - static void i82801jx_rtc_init(struct device *dev) { u8 reg8; @@ -376,10 +363,6 @@ static void lpc_init(struct device *dev) /* Setup power options. */ i82801jx_power_options(dev); - /* Configure Cx state registers */ - if (LPC_IS_MOBILE(dev)) - i82801jx_configure_cstates(dev); - /* Initialize the real time clock. */ i82801jx_rtc_init(dev); diff --git a/src/southbridge/intel/i82801jx/thermal.c b/src/southbridge/intel/i82801jx/thermal.c index 41013a3596..5fc9548e55 100644 --- a/src/southbridge/intel/i82801jx/thermal.c +++ b/src/southbridge/intel/i82801jx/thermal.c @@ -10,9 +10,6 @@ static void thermal_init(struct device *dev) { - if (LPC_IS_MOBILE(pcidev_on_root(0x1f, 0))) - return; - u8 reg8; pci_write_config32(dev, 0x10, (uintptr_t)DEFAULT_TBAR); -- cgit v1.2.3