From 81e9b8ee67fe4f395e999200333a5214d1bf3789 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 3 Dec 2018 11:51:17 +0100 Subject: sb/intel/common/smi.c: Remove unused functions Since all targets using sb/intel/common and cpu/intel/smm/gen1 are now using PARALLEL_MP, some code is not used anymore. Change-Id: Ibdc2bb0f1412366b945813efbc1b6451d27f376f Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/30019 Reviewed-by: Paul Menzel Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/southbridge/intel/common/smi.c | 32 -------------------------------- 1 file changed, 32 deletions(-) (limited to 'src/southbridge') diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index 036ac22adc..398c6804e0 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -104,38 +104,6 @@ void southbridge_smm_init(void) write_pmbase32(SMI_EN, smi_en); } -void southbridge_trigger_smi(void) -{ - /** - * There are several methods of raising a controlled SMI# via - * software, among them: - * - Writes to io 0xb2 (APMC) - * - Writes to the Local Apic ICR with Delivery mode SMI. - * - * Using the local apic is a bit more tricky. According to - * AMD Family 11 Processor BKDG no destination shorthand must be - * used. - * The whole SMM initialization is quite a bit hardware specific, so - * I'm not too worried about the better of the methods at the moment - */ - - /* raise an SMI interrupt */ - printk(BIOS_SPEW, " ... raise SMI#\n"); - outb(0x00, 0xb2); -} - -void southbridge_clear_smi_status(void) -{ - /* Clear SMI status */ - reset_smi_status(); - - /* Clear PM1 status */ - reset_pm1_status(); - - /* Set EOS bit so other SMIs can occur. */ - smi_set_eos(); -} - void smm_setup_structures(void *gnvs, void *tcg, void *smi1) { /* -- cgit v1.2.3