From 7f6335324bb80d9a06bc9832a4fcc3726d74976f Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 7 Oct 2020 13:11:58 -0500 Subject: sb/intel/lynxpoint: Enable/disable AER via Kconfig Several changes[1][2] to the Linux kernel now enable ASPM/AER for the rt8169 network driver, for which it was previously disabled. This, coupled with the southbridge enabling AER for all PCIe devices, has resulted in a large amount of AER timeout errors in the kernel log for boards which utilize the rt8169 for on-board Ethernet (e.g., google/beltino). While performance is not impacted, the errors do accumulate. To mitigate this, guard AER enablement via Kconfig, select it by default (as to maintain current default behavior), and allow boards which need to disable it to do so (implemented in subsequent commits). This implementation is derived from that in soc/intel/broadwell. Test: build/boot google/beltino variants with AER disabled (CB:46136), verify dmesg log free of AER timeout errors. [1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=671646c151d492c3846e6e6797e72ff757b5d65e [2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=a99790bf5c7f3d68d8b01e015d3212a98ee7bd57 Change-Id: Ia03ef0d111335892c65122954c1248191ded7cb8 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/46133 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/southbridge/intel/lynxpoint/Kconfig | 4 ++++ src/southbridge/intel/lynxpoint/pcie.c | 7 +++++-- 2 files changed, 9 insertions(+), 2 deletions(-) (limited to 'src/southbridge') diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index c104cbb3b8..43f8bceb91 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -58,4 +58,8 @@ config FINALIZE_USB_ROUTE_XHCI If you set this option to y, the USB ports will be routed to the XHCI controller during the finalize SMM callback. +config PCIEXP_AER + bool + default y + endif diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 35ce5c4702..077dcd6573 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -670,8 +670,11 @@ static void pch_pcie_early(struct device *dev) /* Set EOI forwarding disable. */ pci_or_config32(dev, 0xd4, 1 << 1); - /* Set something involving advanced error reporting. */ - pci_update_config32(dev, 0x100, ~((1 << 20) - 1), 0x10001); + /* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */ + if (CONFIG(PCIEXP_AER)) + pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29) | 0x10001); + else + pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29)); if (is_lp) pci_or_config32(dev, 0x100, 1 << 29); -- cgit v1.2.3