From 7d14e89c54e89901e7196e7a5da9583515576128 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 30 Jul 2013 15:45:25 -0700 Subject: lynxpoint: Don't write to non-existent EHCI The LynxPoint-LP chipset only has one EHCI controller so we should not attempt to write into the second one that only exists on LynxPoint-H. Change-Id: I1eae060c7f0a5873c9684e5abfeea5cb5895ab62 Signed-off-by: Duncan Laurie Reviewed-on: https://gerrit.chromium.org/gerrit/63799 Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/4405 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/southbridge/intel/lynxpoint/early_pch.c | 6 ++++++ src/southbridge/intel/lynxpoint/early_usb.c | 5 ++--- 2 files changed, 8 insertions(+), 3 deletions(-) (limited to 'src/southbridge') diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 38506c9438..9909bb6d44 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -42,6 +42,12 @@ const struct rcba_config_instruction pch_early_config[] = { RCBA_END_CONFIG, }; +int pch_is_lp(void) +{ + u8 id = pci_read_config8(PCH_LPC_DEV, PCI_DEVICE_ID + 1); + return id == PCH_TYPE_LPT_LP; +} + static void pch_enable_bars(void) { /* Setting up Southbridge. In the northbridge code. */ diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c index 9a1a4cb35e..d328ef6818 100644 --- a/src/southbridge/intel/lynxpoint/early_usb.c +++ b/src/southbridge/intel/lynxpoint/early_usb.c @@ -54,7 +54,6 @@ static void enable_usb_bar_on_device(device_t dev, u32 bar) void enable_usb_bar(void) { enable_usb_bar_on_device(PCH_EHCI1_DEV, PCH_EHCI1_TEMP_BAR0); -#if !CONFIG_INTEL_LYNXPOINT_LP - enable_usb_bar_on_device(PCH_EHCI2_DEV, PCH_EHCI2_TEMP_BAR0); -#endif + if (!pch_is_lp()) + enable_usb_bar_on_device(PCH_EHCI2_DEV, PCH_EHCI2_TEMP_BAR0); } -- cgit v1.2.3