From 7cdb047ce714378a644b7aa2c1f40a2e1a8d5750 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Thu, 8 Aug 2019 11:16:06 +0300 Subject: cpu/x86/smm: Promote smm_memory_map() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I909e9b5fead317928d3513a677cfab25e3c42f64 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34792 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/southbridge/intel/fsp_rangeley/romstage.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/southbridge') diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 2c2427eed1..f52a75205a 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -31,6 +31,7 @@ #include "southbridge/intel/fsp_rangeley/gpio.h" #include "southbridge/intel/fsp_rangeley/romstage.h" #include +#include #include "gpio.h" void main(FSP_INFO_HEADER *fsp_info_header) @@ -121,9 +122,11 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { *(u32*)cbmem_hob_ptr = (u32)hob_list_ptr; post_code(0x4e); - post_code(0x4f); + if (CONFIG(SMM_TSEG)) + smm_list_regions(); /* Load the ramstage. */ + post_code(0x4f); run_ramstage(); while (1); } -- cgit v1.2.3