From 6f55154cd75f67f8d7a737d36125353ce664fe30 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sun, 10 Sep 2017 07:27:08 +0300 Subject: AGESA CIMX: Remove empty set_pcie_(de)reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For boards with cimx/sb800, mainboards defined only empty stubs. Reset functionality is handled as BiosCallout. For amd/inagua, the defined function was actually initial GPIO programming. For cimx/sb700, function had prototypes but no callers. For cimx/sb900, everything was commented out already. Change-Id: I936feb4fc41d903078620c919a733bb9f39c3efb Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/21477 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin --- src/southbridge/amd/cimx/sb700/late.c | 6 ------ src/southbridge/amd/cimx/sb800/late.c | 8 -------- src/southbridge/amd/cimx/sb900/late.c | 12 ------------ 3 files changed, 26 deletions(-) (limited to 'src/southbridge') diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c index 368584ad75..051b563a24 100644 --- a/src/southbridge/amd/cimx/sb700/late.c +++ b/src/southbridge/amd/cimx/sb700/late.c @@ -31,15 +31,9 @@ #include "sb700_cfg.h" /* sb700 Cimx configuration */ #include "chip.h" /* struct southbridge_amd_cimx_sb700_config */ - -/*implement in mainboard.c*/ -void set_pcie_reset(void); -void set_pcie_dereset(void); - static AMDSBCFG sb_late_cfg; //global, init in sb700_cimx_config static AMDSBCFG *sb_config = &sb_late_cfg; - /** * @brief Entry point of Southbridge CIMx callout * diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index e764ba09fe..58d3a3432a 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -37,15 +37,9 @@ #include "pci_devs.h" #include -/*implement in mainboard.c*/ -void set_pcie_reset(void); -void set_pcie_dereset(void); - - static AMDSBCFG sb_late_cfg; //global, init in sb800_cimx_config static AMDSBCFG *sb_config = &sb_late_cfg; - /** * @brief Entry point of Southbridge CIMx callout * @@ -62,11 +56,9 @@ static u32 sb800_callout_entry(u32 func, u32 data, void* config) printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__); switch (func) { case CB_SBGPP_RESET_ASSERT: - set_pcie_reset(); break; case CB_SBGPP_RESET_DEASSERT: - set_pcie_dereset(); break; case IMC_FIRMWARE_FAIL: diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index 90df8e6983..7c001d9b6a 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -28,14 +28,6 @@ #include "SbPlatform.h" /* Platform Specific Definitions */ #include "chip.h" /* struct southbridge_amd_cimx_sb900_config */ - -/*implement in mainboard.c*/ -//void set_pcie_assert(void); -//void set_pcie_deassert(void); -void set_pcie_reset(void); -void set_pcie_dereset(void); - - #ifndef _RAMSTAGE_ #define _RAMSTAGE_ #endif @@ -60,13 +52,9 @@ u32 sb900_callout_entry(u32 func, u32 data, void* config) printk(BIOS_DEBUG, "SB900 - Late.c - sb900_callout_entry - Start.\n"); switch (func) { case CB_SBGPP_RESET_ASSERT: - //set_pcie_assert(); -//- set_pcie_reset(); break; case CB_SBGPP_RESET_DEASSERT: - //set_pcie_deassert(); -//- set_pcie_dereset(); break; //- case IMC_FIRMWARE_FAIL: -- cgit v1.2.3