From 6683e409d3688217e70f1f19deab152790b0f495 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 30 Jul 2017 13:23:32 +0300 Subject: usbdebug: Refactor early enable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Always sanity check for EHCI class device and move PCI function power enablement up. Change-Id: I1eebe813fbb420738af2d572178213fc660f392a Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/20826 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Arthur Heymans --- src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 12 ++++------ src/southbridge/amd/pi/hudson/enable_usbdebug.c | 12 ++++------ src/southbridge/amd/sb600/enable_usbdebug.c | 4 ---- src/southbridge/amd/sb700/enable_usbdebug.c | 4 ---- src/southbridge/amd/sb800/enable_usbdebug.c | 12 ++++------ src/southbridge/intel/common/usb_debug.c | 28 ++++++---------------- src/southbridge/nvidia/ck804/enable_usbdebug.c | 4 ---- src/southbridge/nvidia/mcp55/enable_usbdebug.c | 4 ---- src/southbridge/sis/sis966/enable_usbdebug.c | 4 ---- 9 files changed, 19 insertions(+), 65 deletions(-) (limited to 'src/southbridge') diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c index 4a37e557b6..88b28f4d32 100644 --- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c @@ -26,6 +26,10 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) { + /* Enable all of the USB controllers */ + outb(0xEF, PM_INDEX); + outb(0x7F, PM_DATA); + if (hcd_idx == 3) return PCI_DEV(0, 0x16, 2); else if (hcd_idx == 2) @@ -46,11 +50,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */ write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32); } - - -void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) -{ - /* Enable all of the USB controllers */ - outb(0xEF, PM_INDEX); - outb(0x7F, PM_DATA); -} diff --git a/src/southbridge/amd/pi/hudson/enable_usbdebug.c b/src/southbridge/amd/pi/hudson/enable_usbdebug.c index cb6961ae40..7bea799d0a 100644 --- a/src/southbridge/amd/pi/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/pi/hudson/enable_usbdebug.c @@ -26,6 +26,10 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) { + /* Enable all of the USB controllers */ + outb(0xEF, PM_INDEX); + outb(0x7F, PM_DATA); + if (hcd_idx == 3) return PCI_DEV(0, 0x16, 0); else if (hcd_idx == 2) @@ -46,11 +50,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */ write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32); } - - -void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) -{ - /* Enable all of the USB controllers */ - outb(0xEF, PM_INDEX); - outb(0x7F, PM_DATA); -} diff --git a/src/southbridge/amd/sb600/enable_usbdebug.c b/src/southbridge/amd/sb600/enable_usbdebug.c index 8b19cc41de..5988add889 100644 --- a/src/southbridge/amd/sb600/enable_usbdebug.c +++ b/src/southbridge/amd/sb600/enable_usbdebug.c @@ -32,7 +32,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) { /* TODO: Allow changing the physical USB port used as Debug Port. */ } - -void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) -{ -} diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c index 6d95b8ee4f..654c1acbcf 100644 --- a/src/southbridge/amd/sb700/enable_usbdebug.c +++ b/src/southbridge/amd/sb700/enable_usbdebug.c @@ -45,7 +45,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */ write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32); } - -void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) -{ -} diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c index 8ef3151f13..938a4a6617 100644 --- a/src/southbridge/amd/sb800/enable_usbdebug.c +++ b/src/southbridge/amd/sb800/enable_usbdebug.c @@ -26,6 +26,10 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) { + /* Enable all of the USB controllers */ + outb(0xEF, PM_INDEX); + outb(0x7F, PM_DATA); + if (hcd_idx == 3) return PCI_DEV(0, 0x16, 2); else if (hcd_idx == 2) @@ -46,11 +50,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */ write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32); } - - -void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) -{ - /* Enable all of the USB controllers */ - outb(0xEF, PM_INDEX); - outb(0x7F, PM_DATA); -} diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c index e1cd6575d0..f74da657fd 100644 --- a/src/southbridge/intel/common/usb_debug.c +++ b/src/southbridge/intel/common/usb_debug.c @@ -27,27 +27,20 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) u32 class; pci_devfn_t dev; -#if IS_ENABLED(CONFIG_HAVE_USBDEBUG_OPTIONS) + if (!IS_ENABLED(CONFIG_HAVE_USBDEBUG_OPTIONS)) + return PCI_DEV(0, 0x1d, 7); + if (hcd_idx==2) dev = PCI_DEV(0, 0x1a, 0); else dev = PCI_DEV(0, 0x1d, 0); -#else - dev = PCI_DEV(0, 0x1d, 7); -#endif + /* If we enter here before RCBA programming, EHCI function may + * appear with the highest function number instead. + */ class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8; -#if IS_ENABLED(CONFIG_HAVE_USBDEBUG_OPTIONS) - if (class != PCI_EHCI_CLASSCODE) { - /* If we enter here before RCBA programming, EHCI function may - * appear with the highest function number instead. - */ - dev |= PCI_DEV(0, 0, 7); - class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8; - } -#endif if (class != PCI_EHCI_CLASSCODE) - return 0; + dev |= PCI_DEV(0, 0, 7); return dev; } @@ -57,10 +50,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) { /* Not needed, the ICH* southbridges hardcode physical USB port 1. */ } - -void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) -{ - /* Bail out. No console to complain in. */ - if (!dev) - return; -} diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c index 4ae4aa0052..7296e0526d 100644 --- a/src/southbridge/nvidia/ck804/enable_usbdebug.c +++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c @@ -41,7 +41,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) dword |= (port << 12); pci_write_config32(dev, 0x74, dword); } - -void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) -{ -} diff --git a/src/southbridge/nvidia/mcp55/enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c index 679a71d7b3..69e085984d 100644 --- a/src/southbridge/nvidia/mcp55/enable_usbdebug.c +++ b/src/southbridge/nvidia/mcp55/enable_usbdebug.c @@ -41,7 +41,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) dword |= (port << 12); pci_write_config32(dev, 0x74, dword); } - -void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) -{ -} diff --git a/src/southbridge/sis/sis966/enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c index 428af9429a..6be115e3e5 100644 --- a/src/southbridge/sis/sis966/enable_usbdebug.c +++ b/src/southbridge/sis/sis966/enable_usbdebug.c @@ -43,7 +43,3 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) dword |= (port << 12); pci_write_config32(dev, 0x74, dword); } - -void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) -{ -} -- cgit v1.2.3