From 54e1f59215f3adb6ab1f2e8f2413a71ae7a545c2 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 7 Oct 2020 13:17:09 -0500 Subject: sb/intel/lynxpoint: Set PCIe L1 substates capabilities register Copied from soc/intel/broadwell. Test: build/boot google/beltino variants, verify L1 PM substates listed under PCIe device capabilities Change-Id: Ib2ae3d9539de9f7e22975f00450d9d60d1fd938a Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/46134 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/southbridge/intel/lynxpoint/pcie.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/southbridge') diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 077dcd6573..2da14ed5f0 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -676,6 +676,12 @@ static void pch_pcie_early(struct device *dev) else pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29)); + /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */ + if (CONFIG(PCIEXP_L1_SUB_STATE)) + pci_update_config32(dev, 0x200, ~0xfffff, 0x001e); + else + pci_update_config32(dev, 0x200, ~0xfffff, 0); + if (is_lp) pci_or_config32(dev, 0x100, 1 << 29); -- cgit v1.2.3