From 52f0871b23233ec7314cf778e5534d99dd85ff3d Mon Sep 17 00:00:00 2001 From: Nathaniel Roach Date: Sat, 9 Sep 2017 19:58:08 +0800 Subject: sb/intel/bd82x6x: Add time-stamp around ME DRAM update Add a timestamp before and after waiting for the ME to acknowledge the DRAM being ready. This allows easier debugging during use of me_cleaner and/or alternate ME images. Change-Id: Ie228e12a75d373b4f406b3595e1fb1aab41aa5df Signed-off-by: Nathaniel Roach Reviewed-on: https://review.coreboot.org/21465 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel --- src/southbridge/intel/bd82x6x/early_me.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/southbridge') diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index 607cd14911..b2e920056d 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -20,6 +20,7 @@ #include #include #include +#include #include "me.h" #include "pch.h" @@ -190,6 +191,7 @@ int intel_early_me_init_done(u8 status) meDID = did.uma_base | (1 << 28);// | (1 << 23); pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_ME_H_GS, meDID); + timestamp_add_now(TS_ME_INFORM_DRAM_WAIT); udelay(1100); /* Must wait for ME acknowledgement */ @@ -200,6 +202,7 @@ int intel_early_me_init_done(u8 status) hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24; millisec++; } + timestamp_add_now(TS_ME_INFORM_DRAM_DONE); me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48); printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2); -- cgit v1.2.3