From 4c65bfc3e88fe6f4d6441fb7e51f78ed22dea709 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 10 Apr 2018 13:34:24 +0200 Subject: nb/intel/x4x: Use common code for SMM in TSEG This also caches the TSEG region and therefore increases MTRR usage a little in some cases. Currently SMRR msr's are not set on model_1067x and model_6fx since this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL. This will be handled properly in the subsequent parallel mp init patchset. Tested on Intel DG41WV, resume from S3 still works fine. Change-Id: I317c5ca34bd38c3d42bf0d4e929b2a225a8a82dc Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/25597 Reviewed-by: Angel Pons Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82801jx/Makefile.inc | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/southbridge') diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index 1053659d68..c21a61a757 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -31,8 +31,6 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c ramstage-y += ../i82801gx/watchdog.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += early_smbus.c -- cgit v1.2.3