From 38f1d13a755548ee8afaf9b5e19d8b6709b9e55d Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 17 Sep 2018 08:44:18 +0200 Subject: src/{sb/intel,mb/google/auron}: Don't use device_t Use of device_t is deprecated. Change-Id: I564319506870f75eab58cce535d4e3535a64a993 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/28642 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/southbridge/intel/i82801gx/lpc.c | 2 +- src/southbridge/intel/lynxpoint/azalia.c | 3 ++- src/southbridge/intel/lynxpoint/early_smbus.c | 2 +- src/southbridge/intel/lynxpoint/early_usb.c | 2 +- src/southbridge/intel/lynxpoint/pch.c | 6 +++--- src/southbridge/intel/lynxpoint/pch.h | 10 +++++----- src/southbridge/intel/lynxpoint/serialio.c | 4 ++-- src/southbridge/intel/lynxpoint/smbus.c | 12 ++++++------ 8 files changed, 21 insertions(+), 20 deletions(-) (limited to 'src/southbridge') diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index ac83ec9500..6c8331f940 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -724,7 +724,7 @@ static const char *lpc_acpi_name(const struct device *dev) return "LPCB"; } -static void southbridge_fill_ssdt(device_t device) +static void southbridge_fill_ssdt(struct device *device) { intel_acpi_gen_def_acpi_pirq(device); } diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index 0b1acdd409..38db1a47fc 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -154,7 +154,8 @@ static void azalia_init(struct device *dev) } } -static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void azalia_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c index cf3a34c9e5..4c67aea29c 100644 --- a/src/southbridge/intel/lynxpoint/early_smbus.c +++ b/src/southbridge/intel/lynxpoint/early_smbus.c @@ -23,7 +23,7 @@ void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; /* Set the SMBus device statically. */ dev = PCI_DEV(0x0, 0x1f, 0x3); diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c index a64530eae0..fbc7b37c0c 100644 --- a/src/southbridge/intel/lynxpoint/early_usb.c +++ b/src/southbridge/intel/lynxpoint/early_usb.c @@ -38,7 +38,7 @@ * The BAR will be re-assigned during device * enumeration so these are only temporary. */ -static void enable_usb_bar_on_device(device_t dev, u32 bar) +static void enable_usb_bar_on_device(pci_devfn_t dev, u32 bar) { u32 cmd; pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar); diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 1a390cca42..cb01de7496 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -80,7 +80,7 @@ u16 get_gpiobase(void) #ifndef __SMM__ /* Put device in D3Hot Power State */ -static void pch_enable_d3hot(device_t dev) +static void pch_enable_d3hot(struct device *dev) { u32 reg32 = pci_read_config32(dev, PCH_PCS); reg32 |= PCH_PCS_PS_D3HOT; @@ -88,7 +88,7 @@ static void pch_enable_d3hot(device_t dev) } /* Set bit in Function Disble register to hide this device */ -void pch_disable_devfn(device_t dev) +void pch_disable_devfn(struct device *dev) { switch (dev->path.pci.devfn) { case PCI_DEVFN(19, 0): /* Audio DSP */ @@ -285,7 +285,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) pch_iobp_write(address, data); } -void pch_enable(device_t dev) +void pch_enable(struct device *dev) { u32 reg32; diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index ae996e866e..489b565aef 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -93,9 +93,9 @@ #if defined(__SMM__) && !defined(__ASSEMBLER__) void intel_pch_finalize_smm(void); -void usb_ehci_sleep_prepare(device_t dev, u8 slp_typ); -void usb_ehci_disable(device_t dev); -void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ); +void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); +void usb_ehci_disable(pci_devfn_t dev); +void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); void usb_xhci_route_all(void); #endif @@ -179,8 +179,8 @@ int rtc_failure(void); #include #include #include "chip.h" -void pch_enable(device_t dev); -void pch_disable_devfn(device_t dev); +void pch_enable(struct device *dev); +void pch_disable_devfn(struct device *dev); u32 pch_iobp_read(u32 address); void pch_iobp_write(u32 address, u32 data); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 7d6608f46a..92fa9503aa 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -237,8 +237,8 @@ static void serialio_init(struct device *dev) } } -static void serialio_set_subsystem(device_t dev, unsigned vendor, - unsigned device) +static void serialio_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index ccb5ea08f6..f9deb7d57f 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -25,7 +24,7 @@ #include #include "pch.h" -static void pch_smbus_init(device_t dev) +static void pch_smbus_init(struct device *dev) { struct resource *res; u16 reg16; @@ -41,7 +40,7 @@ static void pch_smbus_init(device_t dev) outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA); } -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device *dev, u8 address) { u16 device; struct resource *res; @@ -54,7 +53,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, u8 address, u8 data) +static int lsmbus_write_byte(struct device *dev, u8 address, u8 data) { u16 device; struct resource *res; @@ -71,7 +70,8 @@ static struct smbus_bus_operations lops_smbus_bus = { .write_byte = lsmbus_write_byte, }; -static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void smbus_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -86,7 +86,7 @@ static struct pci_operations smbus_pci_ops = { .set_subsystem = smbus_set_subsystem, }; -static void smbus_read_resources(device_t dev) +static void smbus_read_resources(struct device *dev) { struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); res->base = SMBUS_IO_BASE; -- cgit v1.2.3