From 35546deba642d3bb341d329fc1b9711727a5c50e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 17 Apr 2014 15:07:32 +0300 Subject: AMD AGESA cimx/sb800: Drop APIC_ID_OFFSET and MAX_PHYSICAL_CPUS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All boards had APIC_ID_OFFSET=0 and MAX_PHYSICAL_CPUS=1. Change-Id: I6f08ea6de92a2af79fb3a99c5edd942b3a321c43 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/5538 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc Reviewed-by: Edward O'Callaghan --- src/southbridge/amd/cimx/sb800/late.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/southbridge') diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 3a534cdb48..219118aa25 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -370,6 +370,10 @@ static void sb800_enable(device_t dev) case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ printk(BIOS_INFO, "sm_init().\n"); clear_ioapic(IO_APIC_ADDR); +#if CONFIG_CPU_AMD_AGESA + /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ + setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS); +#else /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16) /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ @@ -379,6 +383,7 @@ static void sb800_enable(device_t dev) setup_ioapic(IO_APIC_ADDR, 0); #else #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID" +#endif #endif break; -- cgit v1.2.3