From 09fc6342d27bef78aa10e03a5e27bb6322732c66 Mon Sep 17 00:00:00 2001 From: Tristan Corrick Date: Fri, 30 Nov 2018 22:53:01 +1300 Subject: sb/intel/lynxpoint: Make the finalise handler common The ASRock H81M-HDS doesn't implement a finalise handler. To fix this, and reduce code duplication in the process, make a common implementation. There should be no functional change to boards with existing finalise handlers, since the code is identical among them and the new, common implementation. Tested on an ASRock H81M-HDS. The finalise handler works. Change-Id: I13b581a2219288019a4e0c9e618db3ac7c3c15ab Signed-off-by: Tristan Corrick Reviewed-on: https://review.coreboot.org/c/29975 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/lynxpoint/smihandler.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src/southbridge') diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 87848c23c7..12e5ea2eb6 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -25,6 +25,8 @@ #include #include #include +#include +#include #include "pch.h" #include "nvs.h" @@ -270,11 +272,24 @@ static void southbridge_smi_apmc(void) { u8 reg8; em64t101_smm_state_save_area_t *state; + static int chipset_finalized = 0; /* Emulate B2 register as the FADT / Linux expects it */ reg8 = inb(APM_CNT); switch (reg8) { + case APM_CNT_FINALIZE: + if (chipset_finalized) { + printk(BIOS_DEBUG, "SMI#: Already finalized\n"); + return; + } + + intel_pch_finalize_smm(); + intel_northbridge_haswell_finalize_smm(); + intel_cpu_haswell_finalize_smm(); + + chipset_finalized = 1; + break; case APM_CNT_CST_CONTROL: /* Calling this function seems to cause * some kind of race condition in Linux -- cgit v1.2.3