From 836ae29ee325b1e3d28ff59468cc50913b1e24ce Mon Sep 17 00:00:00 2001 From: stepan Date: Wed, 8 Dec 2010 05:42:47 +0000 Subject: first round name simplification. drop the _ prefix. the prefix was introduced in the early v2 tree many years ago because our old build system "newconfig" could not handle two files with the same name in different paths like /path/to/usb.c and /another/path/to/usb.c correctly. Only one of the files would end up being compiled into the final image. Since Kconfig (actually since shortly before we switched to Kconfig) we don't suffer from that problem anymore. So we could drop the sb700_ prefix from all those filenames (or, the _ prefix in general) - makes it easier to fork off a new chipset - makes it easier to diff against other chipsets - storing redundant information in filenames seems wrong Signed-off-by: Acked-by: Patrick Georgi Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/via/k8t890/Makefile.inc | 18 +- src/southbridge/via/k8t890/bridge.c | 70 +++ src/southbridge/via/k8t890/chrome.c | 174 ++++++ src/southbridge/via/k8t890/ctrl.c | 192 +++++++ src/southbridge/via/k8t890/dram.c | 183 ++++++ src/southbridge/via/k8t890/early_car.c | 161 ++++++ src/southbridge/via/k8t890/error.c | 61 ++ src/southbridge/via/k8t890/host.c | 89 +++ src/southbridge/via/k8t890/host_ctrl.c | 151 +++++ src/southbridge/via/k8t890/k8m890_chrome.c | 174 ------ src/southbridge/via/k8t890/k8t890_bridge.c | 70 --- src/southbridge/via/k8t890/k8t890_ctrl.c | 192 ------- src/southbridge/via/k8t890/k8t890_dram.c | 183 ------ src/southbridge/via/k8t890/k8t890_early_car.c | 161 ------ src/southbridge/via/k8t890/k8t890_error.c | 61 -- src/southbridge/via/k8t890/k8t890_host.c | 89 --- src/southbridge/via/k8t890/k8t890_host_ctrl.c | 151 ----- src/southbridge/via/k8t890/k8t890_pcie.c | 176 ------ src/southbridge/via/k8t890/k8t890_traf_ctrl.c | 157 ------ src/southbridge/via/k8t890/pcie.c | 176 ++++++ src/southbridge/via/k8t890/traf_ctrl.c | 157 ++++++ src/southbridge/via/vt8231/Makefile.inc | 10 +- src/southbridge/via/vt8231/acpi.c | 43 ++ src/southbridge/via/vt8231/early_serial.c | 74 +++ src/southbridge/via/vt8231/early_smbus.c | 295 ++++++++++ src/southbridge/via/vt8231/enable_rom.c | 47 ++ src/southbridge/via/vt8231/ide.c | 113 ++++ src/southbridge/via/vt8231/lpc.c | 165 ++++++ src/southbridge/via/vt8231/nic.c | 36 ++ src/southbridge/via/vt8231/usb.c | 52 ++ src/southbridge/via/vt8231/vt8231_acpi.c | 43 -- src/southbridge/via/vt8231/vt8231_early_serial.c | 74 --- src/southbridge/via/vt8231/vt8231_early_smbus.c | 295 ---------- src/southbridge/via/vt8231/vt8231_enable_rom.c | 47 -- src/southbridge/via/vt8231/vt8231_ide.c | 113 ---- src/southbridge/via/vt8231/vt8231_lpc.c | 165 ------ src/southbridge/via/vt8231/vt8231_nic.c | 36 -- src/southbridge/via/vt8231/vt8231_usb.c | 52 -- src/southbridge/via/vt8235/Makefile.inc | 8 +- src/southbridge/via/vt8235/early_serial.c | 77 +++ src/southbridge/via/vt8235/early_smbus.c | 249 ++++++++ src/southbridge/via/vt8235/ide.c | 113 ++++ src/southbridge/via/vt8235/lpc.c | 261 +++++++++ src/southbridge/via/vt8235/nic.c | 36 ++ src/southbridge/via/vt8235/usb.c | 44 ++ src/southbridge/via/vt8235/vt8235_early_serial.c | 77 --- src/southbridge/via/vt8235/vt8235_early_smbus.c | 249 -------- src/southbridge/via/vt8235/vt8235_ide.c | 113 ---- src/southbridge/via/vt8235/vt8235_lpc.c | 261 --------- src/southbridge/via/vt8235/vt8235_nic.c | 36 -- src/southbridge/via/vt8235/vt8235_usb.c | 44 -- src/southbridge/via/vt8237r/Makefile.inc | 14 +- src/southbridge/via/vt8237r/ctrl.c | 289 ++++++++++ src/southbridge/via/vt8237r/early_smbus.c | 498 ++++++++++++++++ src/southbridge/via/vt8237r/fadt.c | 173 ++++++ src/southbridge/via/vt8237r/ide.c | 132 +++++ src/southbridge/via/vt8237r/lpc.c | 624 +++++++++++++++++++++ src/southbridge/via/vt8237r/nic.c | 62 ++ src/southbridge/via/vt8237r/pirq.c | 51 ++ src/southbridge/via/vt8237r/sata.c | 132 +++++ src/southbridge/via/vt8237r/usb.c | 165 ++++++ src/southbridge/via/vt8237r/vt8237_ctrl.c | 289 ---------- src/southbridge/via/vt8237r/vt8237_fadt.c | 173 ------ src/southbridge/via/vt8237r/vt8237r_early_smbus.c | 498 ---------------- src/southbridge/via/vt8237r/vt8237r_ide.c | 132 ----- src/southbridge/via/vt8237r/vt8237r_lpc.c | 624 --------------------- src/southbridge/via/vt8237r/vt8237r_nic.c | 62 -- src/southbridge/via/vt8237r/vt8237r_pirq.c | 51 -- src/southbridge/via/vt8237r/vt8237r_sata.c | 132 ----- src/southbridge/via/vt8237r/vt8237r_usb.c | 165 ------ src/southbridge/via/vt82c686/early_serial.c | 92 +++ .../via/vt82c686/vt82c686_early_serial.c | 92 --- 72 files changed, 5262 insertions(+), 5262 deletions(-) create mode 100644 src/southbridge/via/k8t890/bridge.c create mode 100644 src/southbridge/via/k8t890/chrome.c create mode 100644 src/southbridge/via/k8t890/ctrl.c create mode 100644 src/southbridge/via/k8t890/dram.c create mode 100644 src/southbridge/via/k8t890/early_car.c create mode 100644 src/southbridge/via/k8t890/error.c create mode 100644 src/southbridge/via/k8t890/host.c create mode 100644 src/southbridge/via/k8t890/host_ctrl.c delete mode 100644 src/southbridge/via/k8t890/k8m890_chrome.c delete mode 100644 src/southbridge/via/k8t890/k8t890_bridge.c delete mode 100644 src/southbridge/via/k8t890/k8t890_ctrl.c delete mode 100644 src/southbridge/via/k8t890/k8t890_dram.c delete mode 100644 src/southbridge/via/k8t890/k8t890_early_car.c delete mode 100644 src/southbridge/via/k8t890/k8t890_error.c delete mode 100644 src/southbridge/via/k8t890/k8t890_host.c delete mode 100644 src/southbridge/via/k8t890/k8t890_host_ctrl.c delete mode 100644 src/southbridge/via/k8t890/k8t890_pcie.c delete mode 100644 src/southbridge/via/k8t890/k8t890_traf_ctrl.c create mode 100644 src/southbridge/via/k8t890/pcie.c create mode 100644 src/southbridge/via/k8t890/traf_ctrl.c create mode 100644 src/southbridge/via/vt8231/acpi.c create mode 100644 src/southbridge/via/vt8231/early_serial.c create mode 100644 src/southbridge/via/vt8231/early_smbus.c create mode 100644 src/southbridge/via/vt8231/enable_rom.c create mode 100644 src/southbridge/via/vt8231/ide.c create mode 100644 src/southbridge/via/vt8231/lpc.c create mode 100644 src/southbridge/via/vt8231/nic.c create mode 100644 src/southbridge/via/vt8231/usb.c delete mode 100644 src/southbridge/via/vt8231/vt8231_acpi.c delete mode 100644 src/southbridge/via/vt8231/vt8231_early_serial.c delete mode 100644 src/southbridge/via/vt8231/vt8231_early_smbus.c delete mode 100644 src/southbridge/via/vt8231/vt8231_enable_rom.c delete mode 100644 src/southbridge/via/vt8231/vt8231_ide.c delete mode 100644 src/southbridge/via/vt8231/vt8231_lpc.c delete mode 100644 src/southbridge/via/vt8231/vt8231_nic.c delete mode 100644 src/southbridge/via/vt8231/vt8231_usb.c create mode 100644 src/southbridge/via/vt8235/early_serial.c create mode 100644 src/southbridge/via/vt8235/early_smbus.c create mode 100644 src/southbridge/via/vt8235/ide.c create mode 100644 src/southbridge/via/vt8235/lpc.c create mode 100644 src/southbridge/via/vt8235/nic.c create mode 100644 src/southbridge/via/vt8235/usb.c delete mode 100644 src/southbridge/via/vt8235/vt8235_early_serial.c delete mode 100644 src/southbridge/via/vt8235/vt8235_early_smbus.c delete mode 100644 src/southbridge/via/vt8235/vt8235_ide.c delete mode 100644 src/southbridge/via/vt8235/vt8235_lpc.c delete mode 100644 src/southbridge/via/vt8235/vt8235_nic.c delete mode 100644 src/southbridge/via/vt8235/vt8235_usb.c create mode 100644 src/southbridge/via/vt8237r/ctrl.c create mode 100644 src/southbridge/via/vt8237r/early_smbus.c create mode 100644 src/southbridge/via/vt8237r/fadt.c create mode 100644 src/southbridge/via/vt8237r/ide.c create mode 100644 src/southbridge/via/vt8237r/lpc.c create mode 100644 src/southbridge/via/vt8237r/nic.c create mode 100644 src/southbridge/via/vt8237r/pirq.c create mode 100644 src/southbridge/via/vt8237r/sata.c create mode 100644 src/southbridge/via/vt8237r/usb.c delete mode 100644 src/southbridge/via/vt8237r/vt8237_ctrl.c delete mode 100644 src/southbridge/via/vt8237r/vt8237_fadt.c delete mode 100644 src/southbridge/via/vt8237r/vt8237r_early_smbus.c delete mode 100644 src/southbridge/via/vt8237r/vt8237r_ide.c delete mode 100644 src/southbridge/via/vt8237r/vt8237r_lpc.c delete mode 100644 src/southbridge/via/vt8237r/vt8237r_nic.c delete mode 100644 src/southbridge/via/vt8237r/vt8237r_pirq.c delete mode 100644 src/southbridge/via/vt8237r/vt8237r_sata.c delete mode 100644 src/southbridge/via/vt8237r/vt8237r_usb.c create mode 100644 src/southbridge/via/vt82c686/early_serial.c delete mode 100644 src/southbridge/via/vt82c686/vt82c686_early_serial.c (limited to 'src/southbridge/via') diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc index b549d4af33..972ff70074 100644 --- a/src/southbridge/via/k8t890/Makefile.inc +++ b/src/southbridge/via/k8t890/Makefile.inc @@ -1,12 +1,12 @@ -driver-y += k8t890_ctrl.c -driver-y += k8t890_dram.c -driver-y += k8t890_bridge.c -driver-y += k8t890_host.c -driver-y += k8t890_host_ctrl.c -driver-y += k8t890_pcie.c -driver-y += k8t890_traf_ctrl.c -driver-y += k8t890_error.c -driver-y += k8m890_chrome.c +driver-y += ctrl.c +driver-y += dram.c +driver-y += bridge.c +driver-y += host.c +driver-y += host_ctrl.c +driver-y += pcie.c +driver-y += traf_ctrl.c +driver-y += error.c +driver-y += chrome.c chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc chipset_bootblock_lds += $(src)/southbridge/via/k8t890/romstrap.lds diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c new file mode 100644 index 0000000000..3e1e81730d --- /dev/null +++ b/src/southbridge/via/k8t890/bridge.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "k8t890.h" + +static void bridge_enable(struct device *dev) +{ + u8 tmp; + print_debug("B188 device dump\n"); + /* VIA recommends this, sorry no known info. */ + + writeback(dev, 0x40, 0x91); + writeback(dev, 0x41, 0x40); + writeback(dev, 0x43, 0x44); + writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet + * says it is reserved + */ + writeback(dev, 0x45, 0x3a); + writeback(dev, 0x46, 0x88); /* PCI ID lo */ + writeback(dev, 0x47, 0xb1); /* PCI ID hi */ + + /* Bridge control, K8M890 bit 3 should be set to enable VGA on AGP + * (Forward VGA compatible memory and I/O cycles ) + */ + + writeback(dev, 0x3e, 0x16); + dump_south(dev); + + /* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */ + tmp = pci_read_config8(dev, PCI_COMMAND); + tmp &= ~0x3; + pci_write_config8(dev, PCI_COMMAND, tmp); + +} + +static const struct device_operations bridge_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .enable = bridge_enable, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, +}; + +static const struct pci_driver northbridge_driver __pci_driver = { + .ops = &bridge_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_BR, +}; diff --git a/src/southbridge/via/k8t890/chrome.c b/src/southbridge/via/k8t890/chrome.c new file mode 100644 index 0000000000..5880026552 --- /dev/null +++ b/src/southbridge/via/k8t890/chrome.c @@ -0,0 +1,174 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 Luc Verhaegen + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include /* for memset */ +#include "k8t890.h" + +#if CONFIG_VGA +#include +#include +#include + +/* + * + */ +static void +chrome_vga_init(struct device *dev) +{ + vga_sr_write(0x10, 0x01); /* unlock extended regs */ + + vga_sr_mask(0x1A, 0x02, 0x02); /* enable mmio */ + + vga_sr_mask(0x1A, 0x40, 0x40); /* Software Reset */ + + vga_cr_mask(0x6A, 0x00, 0xC8); /* Disable CRTC2 & Simultaneous */ + + /* Make sure that non of the primary VGA overflow registers are set */ + vga_cr_write(0x33, 0x00); + vga_cr_write(0x35, 0x00); + vga_cr_mask(0x11, 0x00, 0x30); + + vga_sr_mask(0x16, 0x00, 0x40); /* Wire CRT to CRTC1 */ + vga_cr_mask(0x36, 0x00, 0x30); /* Power on CRT */ + + /* Disable Extended Display Mode */ + vga_sr_mask(0x15, 0x00, 0x02); + + /* Disable Wrap-around */ + vga_sr_mask(0x15, 0x00, 0x20); + + /* Disable Extended Mode memory access */ + vga_sr_mask(0x1A, 0x00, 0x08); + + /* Make sure that we only touch CRTC1s DAC */ + vga_sr_mask(0x1A, 0x00, 0x01); + + /* Set up power to the clocks/crtcs */ + vga_sr_mask(0x19, 0x7F, 0x7F); /* enable clock gating for all. */ + vga_sr_mask(0x1B, 0xC0, 0xC0); /* secondary clock according to pm */ + vga_sr_mask(0x1B, 0x20, 0x30); /* primary clock is always on */ + + /* set everything according to PM/Engine idle state except pci dma */ + vga_sr_write(0x2D, 0xFF); /* Power management control 1 */ + vga_sr_write(0x2E, 0xFB); /* Power management control 2 */ + vga_sr_write(0x3F, 0xFF); /* Power management control 3 */ + + /* now set up the engine clock. */ + vga_sr_write(0x47, 0xB8); + vga_sr_write(0x48, 0x08); + vga_sr_write(0x49, 0x03); + + /* trigger engine clock setting */ + vga_sr_mask(0x40, 0x01, 0x01); + vga_sr_mask(0x40, 0, 0x01); + + vga_cr_mask(0x30, 0x04, 0x04); /* Enable PowerNow in primary path */ + vga_cr_mask(0x36, 0x01, 0x01); /* Enable PCI Power Management */ + + /* Power now indicators... */ + vga_cr_write(0x41, 0xB9); + vga_cr_write(0x42, 0xB4); + /* could these be the CRTC2 power now indicators? */ + vga_cr_write(0x9D, 0x80); /* Power Now Ending position enable */ + vga_cr_write(0x9E, 0xB4); /* Power Now Control 3 */ + + /* primary fifo setting */ + vga_sr_mask(0x16, 0x28, 0xBF); /* pthreshold: 160 */ + vga_sr_write(0x17, 0x60); /* max depth: 194 */ + vga_sr_mask(0x18, 0x0E, 0xBF); /* high priority threshold: 56 */ + vga_sr_write(0x1C, 0x54); /* Fetch count */ + + vga_sr_write(0x20, 0x40); /* display queue typical arbiter control 0 */ + vga_sr_write(0x21, 0x40); /* display queue typical arbiter control 1 */ + vga_sr_mask(0x22, 0x14, 0x1F); /* display queue expire number */ + + /* Typical Arbiter Control */ + vga_sr_mask(0x41, 0x40, 0xF0); /* Request threshold */ + vga_sr_mask(0x42, 0x20, 0x20); /* Support Fetch Cycle with Length 2 */ + + vga_sr_write(0x50, 0x1F); /* AGP Control Register */ + vga_sr_write(0x51, 0xF5); /* AGP FIFO Control 1 */ + + vga_cr_mask(0x33, 0x08, 0x08); /* Enable Prefetch Mode */ +} + +#endif /* CONFIG_VGA */ + +/* + * + */ +static void +chrome_init(struct device *dev) +{ + uint32_t fb_size, fb_address; + + fb_size = k8m890_host_fb_size_get(); + if (!fb_size) { + printk(BIOS_WARNING, "Chrome: Device has not been initialised in the" + " ramcontroller!\n"); + return; + } + + fb_address = pci_read_config32(dev, 0x10); + fb_address &= ~0x0F; + if (!fb_address) { + printk(BIOS_WARNING, "Chrome: No FB BAR assigned!\n"); + return; + } + + printk(BIOS_INFO, "Chrome: Using %dMB Framebuffer at 0x%08X.\n", + fb_size, fb_address); + + //k8m890_host_fb_direct_set(fb_address); + +#if CONFIG_VGA + /* Now set up the VGA console */ + vga_io_init(); /* Enable full IO access */ + + chrome_vga_init(dev); + + vga_textmode_init(); + + printk(BIOS_INFO, "Chrome VGA Textmode initialized.\n"); + + /* if we don't have console, at least print something... */ + vga_line_write(0, "Chrome VGA Textmode initialized."); +#endif /* CONFIG_VGA */ +} + +static struct device_operations +chrome_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = chrome_init, + .scan_bus = 0, + .enable = 0, +}; + +static const struct pci_driver unichrome_driver __pci_driver = { + .ops = &chrome_ops, + .vendor = 0x1106, + .device = 0x3230, +}; diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c new file mode 100644 index 0000000000..bb3cc02217 --- /dev/null +++ b/src/southbridge/via/k8t890/ctrl.c @@ -0,0 +1,192 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include + +/* We support here K8M890/K8T890 and VT8237R PCI1/Vlink which setup is not in separate + * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1) + */ + +static void vt8237r_cfg(struct device *dev, struct device *devsb) +{ + u8 regm, regm3; + + device_t devfun3; + + devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CE_3, 0); + + if (!devfun3) + devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CF_3, 0); + + if (!devfun3) + devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8M890CE_3, 0); + + pci_write_config8(dev, 0x70, 0xc2); + + /* PCI Control */ + pci_write_config8(dev, 0x72, 0xee); + pci_write_config8(dev, 0x73, 0x01); + pci_write_config8(dev, 0x74, 0x24); + pci_write_config8(dev, 0x75, 0x0f); + pci_write_config8(dev, 0x76, 0x50); + pci_write_config8(dev, 0x77, 0x08); + pci_write_config8(dev, 0x78, 0x01); + /* APIC on HT */ + pci_write_config8(dev, 0x7c, 0x7f); + pci_write_config8(dev, 0x7f, 0x02); + + /* WARNING: Need to copy some registers from NB (D0F3) to SB (D0F7). */ + + regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */ + pci_write_config8(dev, 0x57, regm); + + regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */ + pci_write_config8(dev, 0x61, regm); + + regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */ + pci_write_config8(dev, 0x62, regm); + + regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */ + pci_write_config8(dev, 0xe6, regm); + + regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */ + + /* + * All access bits for 0xE0000-0xEFFFF encode as just 2 bits! + * So the NB reg is quite inconsistent, we expect there only 0xff or 0x00, + * and write them to 0x63 7-6 but! VIA 8237A has the mirror at 0x64! + */ + if (regm3 == 0xff) + regm3 = 0xc0; + else + regm3 = 0x0; + + /* Shadow page F + memhole copy */ + regm = pci_read_config8(devfun3, 0x83); + pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F)); +} + + + +/** + * Setup the V-Link for VT8237R, 8X mode. + * + * For K8T890CF VIA recommends what is in VIA column, AW is award 8X: + * + * REG DEF AW VIA-8X VIA-4X + * ----------------------------- + * NB V-Link Manual Driving Control strobe 0xb5 0x46 0x46 0x88 0x88 + * NB V-Link Manual Driving Control - Data 0xb6 0x46 0x46 0x88 0x88 + * NB V-Link Receiving Strobe Delay 0xb7 0x02 0x02 0x61 0x01 + * NB V-Link Compensation Control bit4,0 (b5,b6) 0xb4 0x10 0x10 0x11 0x11 + * SB V-Link Strobe Drive Control 0xb9 0x00 0xa5 0x98 0x98 + * SB V-Link Data drive Control???? 0xba 0x00 0xbb 0x77 0x77 + * SB V-Link Receive Strobe Delay???? 0xbb 0x04 0x11 0x11 0x11 + * SB V-Link Compensation Control bit0 (use b9) 0xb8 0x00 0x01 0x01 0x01 + * V-Link CKG Control 0xb0 0x05 0x05 0x06 0x03 + * V-Link CKG Control 0xb1 0x05 0x05 0x01 0x03 + */ + +static void vt8237r_vlink_init(struct device *dev) +{ + u8 reg; + + /* + * This init code is valid only for the VT8237R! For different + * sounthbridges (e.g. VT8237A, VT8237S, VT8237 (without plus R) + * and VT8251) a different init code is required. + */ + + pci_write_config8(dev, 0xb5, 0x88); + pci_write_config8(dev, 0xb6, 0x88); + pci_write_config8(dev, 0xb7, 0x61); + + reg = pci_read_config8(dev, 0xb4); + reg |= 0x11; + pci_write_config8(dev, 0xb4, reg); + + pci_write_config8(dev, 0xb9, 0x98); + pci_write_config8(dev, 0xba, 0x77); + pci_write_config8(dev, 0xbb, 0x11); + + reg = pci_read_config8(dev, 0xb8); + reg |= 0x1; + pci_write_config8(dev, 0xb8, reg); + + pci_write_config8(dev, 0xb0, 0x06); + pci_write_config8(dev, 0xb1, 0x01); + + /* Program V-link 8X 16bit full duplex, parity enabled. */ + pci_write_config8(dev, 0x48, 0xa3); +} + +static void ctrl_init(struct device *dev) { + + /* TODO: Fix some ordering issue fo V-link set Rx77[6] and PCI1_Rx4F[0] + should to 1 */ + + /* C2P Read ACK Return Priority */ + /* PCI CFG Address bits[27:24] are used as extended register address + bit[11:8] */ + + pci_write_config8(dev, 0x47, 0x30); + + /* VT8237R specific configuration other SB are done in their own directories */ + + device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); + if (devsb) { + vt8237r_vlink_init(dev); + vt8237r_cfg(dev, devsb); + } + +} + +static const struct device_operations ctrl_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ctrl_init, + .ops_pci = 0, +}; + +static const struct pci_driver northbridge_driver_t __pci_driver = { + .ops = &ctrl_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_7, +}; + +static const struct pci_driver northbridge_driver_tcf __pci_driver = { + .ops = &ctrl_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CF_7, +}; + +static const struct pci_driver northbridge_driver_m __pci_driver = { + .ops = &ctrl_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8M890CE_7, +}; diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c new file mode 100644 index 0000000000..6c52fb1d02 --- /dev/null +++ b/src/southbridge/via/k8t890/dram.c @@ -0,0 +1,183 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "k8t890.h" + +static void dram_enable(struct device *dev) +{ + msr_t msr; + u16 reg; + + /* + * Enable Lowest Interrupt arbitration for APIC, enable NB APIC + * decoding, MSI support, no SMRAM, compatible SMM. + */ + pci_write_config8(dev, 0x86, 0x39); + + /* + * We want to use the 0xC0000-0xEFFFF as RAM mark area as RW, even if + * memory is doing K8 the DMA from SB will fail if we have it wrong, + * AND even we have it here, we must later copy it to SB to make it work :/ + */ + + /* For CC000-CFFFF, bits 7:6 (10 = REn, 01 = WEn) bits 1:0 for + * C0000-C3FFF etc. + */ + pci_write_config8(dev, 0x80, 0xff); + /* For page D0000-DFFFF */ + pci_write_config8(dev, 0x81, 0xff); + /* For page E0000-EFFFF */ + pci_write_config8(dev, 0x82, 0xff); + pci_write_config8(dev, 0x83, 0x30); + + msr = rdmsr(TOP_MEM); + reg = pci_read_config16(dev, 0x84); + reg &= 0xf; + pci_write_config16(dev, 0x84, (msr.lo >> 16) | reg); + + reg = pci_read_config16(dev, 0x88); + reg &= 0xf800; + + /* The Address Next to the Last Valid DRAM Address */ + pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg); + +} + +#if CONFIG_GFXUMA +extern uint64_t uma_memory_base, uma_memory_size; +#endif + +static void dram_enable_k8m890(struct device *dev) +{ +#if CONFIG_GFXUMA + msr_t msr; + int ret; + unsigned int fbbits; + + /* use CMOS */ + if (CONFIG_VIDEO_MB == -1) { + ret = get_option(&fbbits, "videoram_size"); + if (ret) { + printk(BIOS_WARNING, "Failed to get videoram size (error %d), using default.\n", ret); + fbbits = 5; + } + + if ((fbbits < 1) || (fbbits > 7)) { + printk(BIOS_WARNING, "Invalid videoram size (%d), using default.\n", + 4 << fbbits); + fbbits = 5; + } + uma_memory_size = 4 << (fbbits + 20); + } else { + uma_memory_size = (CONFIG_VIDEO_MB << 20); + } + + msr = rdmsr(TOP_MEM); + uma_memory_base = msr.lo - uma_memory_size; + printk(BIOS_INFO, "K8M890: UMA base is %llx size is %u (MB)\n", uma_memory_base, + (u32) (uma_memory_size / 1024 / 1024)); + /* enable VGA, so the bridges gets VGA_EN and resources are set */ + pci_write_config8(dev, 0xa1, 0x80); +#endif + dram_enable(dev); +} + +int +k8m890_host_fb_size_get(void) +{ + struct device *dev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8M890CE_3, 0); + unsigned char tmp; + + tmp = pci_read_config8(dev, 0xA1); + tmp >>= 4; + if (tmp & 0x08) + return 4 << (tmp & 7); + else + return 0; +} + +static void dram_init_fb(struct device *dev) +{ +#if CONFIG_GFXUMA + /* Important bits: + * Enable the internal GFX bit 7 of reg 0xa1 plus in same reg: + * bits 6:4 X fbuffer size will be 2^(X+2) or 100 = 64MB, 101 = 128MB + * bits 3:0 BASE [31:28] + * reg 0xa0 bits 7:1 BASE [27:21] bit0 enable CPU access + */ + unsigned int fbbits = 0; + u8 tmp; + + fbbits = ((log2(uma_memory_size >> 20) - 2) << 4); + printk(BIOS_INFO, "K8M890: Using a %dMB framebuffer.\n", (unsigned int) (uma_memory_size >> 20)); + + /* Step 1: enable UMA but no FB */ + pci_write_config8(dev, 0xa1, 0x80); + + /* Step 2: enough is just the FB size, the CPU accessible address is not needed */ + tmp = fbbits | 0x80; + pci_write_config8(dev, 0xa1, tmp); + + /* TODO K8 needs some UMA fine tuning too maybe call some generic routine here? */ +#endif +} + +static const struct device_operations dram_ops_t = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = dram_enable, + .ops_pci = 0, +}; + +static const struct device_operations dram_ops_m = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = dram_enable_k8m890, + .init = dram_init_fb, + .ops_pci = 0, +}; + +static const struct pci_driver northbridge_driver_t __pci_driver = { + .ops = &dram_ops_t, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_3, +}; + +static const struct pci_driver northbridge_driver_tcf __pci_driver = { + .ops = &dram_ops_t, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CF_3, +}; + +static const struct pci_driver northbridge_driver_m __pci_driver = { + .ops = &dram_ops_m, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8M890CE_3, +}; diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c new file mode 100644 index 0000000000..94162cb90c --- /dev/null +++ b/src/southbridge/via/k8t890/early_car.c @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Seems the link and width of HT link needs to be setup too, you need to + * generate PCI reset or LDTSTOP to apply. + */ + +#include +#include +#include +#include "k8t890.h" + +/* The 256 bytes of NVRAM for S3 storage, 256B aligned */ +#define K8T890_NVRAM_IO_BASE 0xf00 +#define K8T890_MULTIPLE_FN_EN 0x4f + +/* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */ +static u8 ldtreg[3] = {0x86, 0xa6, 0xc6}; + +/* This functions sets KT890 link frequency and width to same values as + * it has been setup on K8 side, by AMD NB init. + */ + +u8 k8t890_early_setup_ht(void) +{ + u8 awidth, afreq, cldtfreq, reg; + u8 cldtwidth_in, cldtwidth_out, vldtwidth_in, vldtwidth_out, ldtnr, width; + u16 vldtcaps; + + /* hack, enable NVRAM in chipset */ + pci_write_config8(PCI_DEV(0, 0x0, 0), K8T890_MULTIPLE_FN_EN, 0x01); + + /* + * NVRAM I/O base at K8T890_NVRAM_IO_BASE + */ + + pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa2, (K8T890_NVRAM_IO_BASE >> 8)); + reg = pci_read_config8(PCI_DEV(0, 0x0, 2), 0xa1); + reg |= 0x1; + pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa1, reg); + + /* check if connected non coherent, initcomplete (find the SB on K8 side) */ + ldtnr = 0; + if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0x98)) { + ldtnr = 0; + } else if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0xb8)) { + ldtnr = 1; + } else if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0xd8)) { + ldtnr = 2; + } + + print_debug("K8T890 found at LDT "); + print_debug_hex8(ldtnr); + + /* get the maximum widths for both sides */ + cldtwidth_in = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) & 0x7; + cldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) >> 4) & 0x7; + vldtwidth_in = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x66) & 0x7; + vldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x0, 0), 0x66) >> 4) & 0x7; + + width = MIN(MIN(MIN(cldtwidth_out, cldtwidth_in), vldtwidth_out), vldtwidth_in); + print_debug(" Agreed on width: "); + print_debug_hex8(width); + + awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x67); + + /* Update the desired HT LNK to match AMD NB max from VIA NB is 0x1 */ + width = (width == 0x01) ? 0x11 : 0x00; + + pci_write_config8(PCI_DEV(0, 0x0, 0), 0x67, width); + + /* Get programmed HT freq at base 0x89 */ + cldtfreq = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr] + 3) & 0xf; + print_debug(" CPU programmed to HT freq: "); + print_debug_hex8(cldtfreq); + + print_debug(" VIA HT caps: "); + vldtcaps = pci_read_config16(PCI_DEV(0, 0, 0), 0x6e); + print_debug_hex16(vldtcaps); + + if (!(vldtcaps & (1 << cldtfreq ))) { + die("Chipset does not support desired HT frequency\n"); + } + + afreq = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x6d); + pci_write_config8(PCI_DEV(0, 0x0, 0), 0x6d, cldtfreq); + print_debug("\n"); + + /* no reset needed */ + if ((width == awidth) && (afreq == cldtfreq)) { + return 0; + } + + return 1; +} + +static inline int s3_save_nvram_early(u32 dword, int size, int nvram_pos) +{ + + printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); + switch (size) { + case 1: + outb((dword & 0xff), K8T890_NVRAM_IO_BASE+nvram_pos); + nvram_pos +=1; + break; + case 2: + outw((dword & 0xffff), K8T890_NVRAM_IO_BASE+nvram_pos); + nvram_pos +=2; + break; + default: + outl(dword, K8T890_NVRAM_IO_BASE+nvram_pos); + nvram_pos +=4; + break; + } + return nvram_pos; +} + +static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) +{ + switch (size) { + case 1: + *old_dword &= ~0xff; + *old_dword |= inb(K8T890_NVRAM_IO_BASE+nvram_pos); + nvram_pos +=1; + break; + case 2: + *old_dword &= ~0xffff; + *old_dword |= inw(K8T890_NVRAM_IO_BASE+nvram_pos); + nvram_pos +=2; + break; + default: + *old_dword = inl(K8T890_NVRAM_IO_BASE+nvram_pos); + nvram_pos +=4; + break; + } + printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", * old_dword, size, nvram_pos-size); + return nvram_pos; +} + +/* this should be a function +struct cbmem_entry *get_cbmem_toc(void) { +*/ + +#define get_cbmem_toc() ((struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC)) diff --git a/src/southbridge/via/k8t890/error.c b/src/southbridge/via/k8t890/error.c new file mode 100644 index 0000000000..a9b10d56bc --- /dev/null +++ b/src/southbridge/via/k8t890/error.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include + +static void error_enable(struct device *dev) +{ + /* + * bit0 - Enable V-link parity error reporting in 0x50 bit0 (RWC) + * bit6 - Parity Error/SERR# Report Through V-Link to SB + * bit7 - Parity Error/SERR# Report Through NMI + */ + pci_write_config8(dev, 0x58, 0x81); + + /* TODO: enable AGP errors reporting on K8M890 */ +} + +static const struct device_operations error_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = error_enable, + .ops_pci = 0, +}; + +static const struct pci_driver northbridge_driver_t __pci_driver = { + .ops = &error_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_1, +}; + +static const struct pci_driver northbridge_driver_tcf __pci_driver = { + .ops = &error_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CF_1, +}; + +static const struct pci_driver northbridge_driver_m __pci_driver = { + .ops = &error_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8M890CE_1, +}; diff --git a/src/southbridge/via/k8t890/host.c b/src/southbridge/via/k8t890/host.c new file mode 100644 index 0000000000..9a0118c778 --- /dev/null +++ b/src/southbridge/via/k8t890/host.c @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include "k8t890.h" + +static void host_enable(struct device *dev) +{ + /* Multiple function control */ + pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01); + +} + + +static void host_init(struct device *dev) +{ + u8 reg; + + /* AGP Capability Header Control */ + reg = pci_read_config8(dev, 0x4d); + reg |= 0x20; /* GART access enabled by either D0F0 Rx90[8] or D1F0 Rx90[8] */ + pci_write_config8(dev, 0x4d, reg); + + /* GD Output Stagger Delay */ + reg = pci_read_config8(dev, 0x42); + reg |= 0x10; /* AD[31:16] with 1ns */ + pci_write_config8(dev, 0x42, reg); + + /* AGP Control */ + reg = pci_read_config8(dev, 0xbc); + reg |= 0x20; /* AGP Read Snoop DRAM Post-Write Buffer */ + pci_write_config8(dev, 0xbc, reg); + +} + +static const struct device_operations host_ops_t = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = host_enable, + .ops_pci = 0, +}; + +static const struct device_operations host_ops_m = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = host_enable, + .init = host_init, + .ops_pci = 0, +}; + +static const struct pci_driver northbridge_driver_t __pci_driver = { + .ops = &host_ops_t, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_0, +}; + +static const struct pci_driver northbridge_driver_tcf __pci_driver = { + .ops = &host_ops_t, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CF_0, +}; + +static const struct pci_driver northbridge_driver_m __pci_driver = { + .ops = &host_ops_m, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8M890CE_0, +}; diff --git a/src/southbridge/via/k8t890/host_ctrl.c b/src/southbridge/via/k8t890/host_ctrl.c new file mode 100644 index 0000000000..43d01ee369 --- /dev/null +++ b/src/southbridge/via/k8t890/host_ctrl.c @@ -0,0 +1,151 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "k8t890.h" + +/* this may be later merged */ + +/* This fine tunes the HT link settings, which were loaded by ROM strap. */ +static void host_ctrl_enable_k8t890(struct device *dev) +{ + dump_south(dev); + + /* + * Bit 4 is reserved but set by AW. Set PCI to HT outstanding + * requests to 3. + */ + pci_write_config8(dev, 0xa0, 0x13); + + /* + * NVRAM I/O base at K8T890_NVRAM_IO_BASE + * Some bits are set and reserved. + */ + pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8)); + + /* enable NB NVRAM and enable non-posted PCI writes. */ + pci_write_config8(dev, 0xa1, 0x8f); + /* Arbitration control, some bits are reserved. */ + pci_write_config8(dev, 0xa5, 0x3c); + + /* Arbitration control 2 */ + pci_write_config8(dev, 0xa6, 0x80); + + /* this will be possibly removed, when I figure out + * if the ROM SIP is good, second reason is that the + * unknown bits are AGP related, which are dummy on K8T890 + */ + + writeback(dev, 0xa0, 0x13); /* Bit4 is reserved! */ + writeback(dev, 0xa1, 0x8e); /* Some bits are reserved. */ + writeback(dev, 0xa2, 0x0e); /* I/O NVRAM base 0xe00-0xeff disabled. */ + writeback(dev, 0xa3, 0x31); + writeback(dev, 0xa4, 0x30); + + writeback(dev, 0xa5, 0x3c); /* Some bits reserved. */ + writeback(dev, 0xa6, 0x80); /* Some bits reserved. */ + writeback(dev, 0xa7, 0x86); /* Some bits reserved. */ + writeback(dev, 0xa8, 0x7f); /* Some bits reserved. */ + writeback(dev, 0xa9, 0xcf); /* Some bits reserved. */ + writeback(dev, 0xaa, 0x44); + writeback(dev, 0xab, 0x22); + writeback(dev, 0xac, 0x35); /* Maybe bit0 is read-only? */ + + writeback(dev, 0xae, 0x22); + writeback(dev, 0xaf, 0x40); + /* b0 is missing. */ + writeback(dev, 0xb1, 0x13); + writeback(dev, 0xb4, 0x02); /* Some bits are reserved. */ + writeback(dev, 0xc0, 0x20); + writeback(dev, 0xc1, 0xaa); + writeback(dev, 0xc2, 0xaa); + writeback(dev, 0xc3, 0x02); + writeback(dev, 0xc4, 0x50); + writeback(dev, 0xc5, 0x50); + + dump_south(dev); +} + +/* This fine tunes the HT link settings, which were loaded by ROM strap. */ +static void host_ctrl_enable_k8m890(struct device *dev) { + + /* + * Set PCI to HT outstanding requests to 03. + * Bit 4 32 AGP ADS Read Outstanding Request Number + */ + pci_write_config8(dev, 0xa0, 0x13); + + /* + * NVRAM I/O base at K8T890_NVRAM_IO_BASE + */ + + pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8)); + + /* Enable NVRAM and enable non-posted PCI writes. */ + pci_write_config8(dev, 0xa1, 0x8f); + + /* Arbitration control */ + pci_write_config8(dev, 0xa5, 0x3c); + + /* Arbitration control 2, Enable C2NOW delay to PSTATECTL */ + pci_write_config8(dev, 0xa6, 0x83); + +} +#if 0 +struct cbmem_entry *get_cbmem_toc(void) { + return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); +} +#endif +void set_cbmem_toc(struct cbmem_entry *toc) { + outl((u32) toc, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); +} + +static const struct device_operations host_ctrl_ops_t = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = host_ctrl_enable_k8t890, + .ops_pci = 0, +}; + +static const struct device_operations host_ctrl_ops_m = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = host_ctrl_enable_k8m890, + .ops_pci = 0, +}; + +static const struct pci_driver northbridge_driver_t __pci_driver = { + .ops = &host_ctrl_ops_t, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_2, +}; + +static const struct pci_driver northbridge_driver_m __pci_driver = { + .ops = &host_ctrl_ops_m, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8M890CE_2, +}; diff --git a/src/southbridge/via/k8t890/k8m890_chrome.c b/src/southbridge/via/k8t890/k8m890_chrome.c deleted file mode 100644 index 5880026552..0000000000 --- a/src/southbridge/via/k8t890/k8m890_chrome.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 Luc Verhaegen - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include /* for memset */ -#include "k8t890.h" - -#if CONFIG_VGA -#include -#include -#include - -/* - * - */ -static void -chrome_vga_init(struct device *dev) -{ - vga_sr_write(0x10, 0x01); /* unlock extended regs */ - - vga_sr_mask(0x1A, 0x02, 0x02); /* enable mmio */ - - vga_sr_mask(0x1A, 0x40, 0x40); /* Software Reset */ - - vga_cr_mask(0x6A, 0x00, 0xC8); /* Disable CRTC2 & Simultaneous */ - - /* Make sure that non of the primary VGA overflow registers are set */ - vga_cr_write(0x33, 0x00); - vga_cr_write(0x35, 0x00); - vga_cr_mask(0x11, 0x00, 0x30); - - vga_sr_mask(0x16, 0x00, 0x40); /* Wire CRT to CRTC1 */ - vga_cr_mask(0x36, 0x00, 0x30); /* Power on CRT */ - - /* Disable Extended Display Mode */ - vga_sr_mask(0x15, 0x00, 0x02); - - /* Disable Wrap-around */ - vga_sr_mask(0x15, 0x00, 0x20); - - /* Disable Extended Mode memory access */ - vga_sr_mask(0x1A, 0x00, 0x08); - - /* Make sure that we only touch CRTC1s DAC */ - vga_sr_mask(0x1A, 0x00, 0x01); - - /* Set up power to the clocks/crtcs */ - vga_sr_mask(0x19, 0x7F, 0x7F); /* enable clock gating for all. */ - vga_sr_mask(0x1B, 0xC0, 0xC0); /* secondary clock according to pm */ - vga_sr_mask(0x1B, 0x20, 0x30); /* primary clock is always on */ - - /* set everything according to PM/Engine idle state except pci dma */ - vga_sr_write(0x2D, 0xFF); /* Power management control 1 */ - vga_sr_write(0x2E, 0xFB); /* Power management control 2 */ - vga_sr_write(0x3F, 0xFF); /* Power management control 3 */ - - /* now set up the engine clock. */ - vga_sr_write(0x47, 0xB8); - vga_sr_write(0x48, 0x08); - vga_sr_write(0x49, 0x03); - - /* trigger engine clock setting */ - vga_sr_mask(0x40, 0x01, 0x01); - vga_sr_mask(0x40, 0, 0x01); - - vga_cr_mask(0x30, 0x04, 0x04); /* Enable PowerNow in primary path */ - vga_cr_mask(0x36, 0x01, 0x01); /* Enable PCI Power Management */ - - /* Power now indicators... */ - vga_cr_write(0x41, 0xB9); - vga_cr_write(0x42, 0xB4); - /* could these be the CRTC2 power now indicators? */ - vga_cr_write(0x9D, 0x80); /* Power Now Ending position enable */ - vga_cr_write(0x9E, 0xB4); /* Power Now Control 3 */ - - /* primary fifo setting */ - vga_sr_mask(0x16, 0x28, 0xBF); /* pthreshold: 160 */ - vga_sr_write(0x17, 0x60); /* max depth: 194 */ - vga_sr_mask(0x18, 0x0E, 0xBF); /* high priority threshold: 56 */ - vga_sr_write(0x1C, 0x54); /* Fetch count */ - - vga_sr_write(0x20, 0x40); /* display queue typical arbiter control 0 */ - vga_sr_write(0x21, 0x40); /* display queue typical arbiter control 1 */ - vga_sr_mask(0x22, 0x14, 0x1F); /* display queue expire number */ - - /* Typical Arbiter Control */ - vga_sr_mask(0x41, 0x40, 0xF0); /* Request threshold */ - vga_sr_mask(0x42, 0x20, 0x20); /* Support Fetch Cycle with Length 2 */ - - vga_sr_write(0x50, 0x1F); /* AGP Control Register */ - vga_sr_write(0x51, 0xF5); /* AGP FIFO Control 1 */ - - vga_cr_mask(0x33, 0x08, 0x08); /* Enable Prefetch Mode */ -} - -#endif /* CONFIG_VGA */ - -/* - * - */ -static void -chrome_init(struct device *dev) -{ - uint32_t fb_size, fb_address; - - fb_size = k8m890_host_fb_size_get(); - if (!fb_size) { - printk(BIOS_WARNING, "Chrome: Device has not been initialised in the" - " ramcontroller!\n"); - return; - } - - fb_address = pci_read_config32(dev, 0x10); - fb_address &= ~0x0F; - if (!fb_address) { - printk(BIOS_WARNING, "Chrome: No FB BAR assigned!\n"); - return; - } - - printk(BIOS_INFO, "Chrome: Using %dMB Framebuffer at 0x%08X.\n", - fb_size, fb_address); - - //k8m890_host_fb_direct_set(fb_address); - -#if CONFIG_VGA - /* Now set up the VGA console */ - vga_io_init(); /* Enable full IO access */ - - chrome_vga_init(dev); - - vga_textmode_init(); - - printk(BIOS_INFO, "Chrome VGA Textmode initialized.\n"); - - /* if we don't have console, at least print something... */ - vga_line_write(0, "Chrome VGA Textmode initialized."); -#endif /* CONFIG_VGA */ -} - -static struct device_operations -chrome_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = chrome_init, - .scan_bus = 0, - .enable = 0, -}; - -static const struct pci_driver unichrome_driver __pci_driver = { - .ops = &chrome_ops, - .vendor = 0x1106, - .device = 0x3230, -}; diff --git a/src/southbridge/via/k8t890/k8t890_bridge.c b/src/southbridge/via/k8t890/k8t890_bridge.c deleted file mode 100644 index 3e1e81730d..0000000000 --- a/src/southbridge/via/k8t890/k8t890_bridge.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Rudolf Marek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include "k8t890.h" - -static void bridge_enable(struct device *dev) -{ - u8 tmp; - print_debug("B188 device dump\n"); - /* VIA recommends this, sorry no known info. */ - - writeback(dev, 0x40, 0x91); - writeback(dev, 0x41, 0x40); - writeback(dev, 0x43, 0x44); - writeback(dev, 0x44, 0x31); /* K8M890 should have 0x35 datasheet - * says it is reserved - */ - writeback(dev, 0x45, 0x3a); - writeback(dev, 0x46, 0x88); /* PCI ID lo */ - writeback(dev, 0x47, 0xb1); /* PCI ID hi */ - - /* Bridge control, K8M890 bit 3 should be set to enable VGA on AGP - * (Forward VGA compatible memory and I/O cycles ) - */ - - writeback(dev, 0x3e, 0x16); - dump_south(dev); - - /* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */ - tmp = pci_read_config8(dev, PCI_COMMAND); - tmp &= ~0x3; - pci_write_config8(dev, PCI_COMMAND, tmp); - -} - -static const struct device_operations bridge_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .enable = bridge_enable, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, -}; - -static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &bridge_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_BR, -}; diff --git a/src/southbridge/via/k8t890/k8t890_ctrl.c b/src/southbridge/via/k8t890/k8t890_ctrl.c deleted file mode 100644 index bb3cc02217..0000000000 --- a/src/southbridge/via/k8t890/k8t890_ctrl.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Rudolf Marek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include - -/* We support here K8M890/K8T890 and VT8237R PCI1/Vlink which setup is not in separate - * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1) - */ - -static void vt8237r_cfg(struct device *dev, struct device *devsb) -{ - u8 regm, regm3; - - device_t devfun3; - - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_3, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CF_3, 0); - - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M890CE_3, 0); - - pci_write_config8(dev, 0x70, 0xc2); - - /* PCI Control */ - pci_write_config8(dev, 0x72, 0xee); - pci_write_config8(dev, 0x73, 0x01); - pci_write_config8(dev, 0x74, 0x24); - pci_write_config8(dev, 0x75, 0x0f); - pci_write_config8(dev, 0x76, 0x50); - pci_write_config8(dev, 0x77, 0x08); - pci_write_config8(dev, 0x78, 0x01); - /* APIC on HT */ - pci_write_config8(dev, 0x7c, 0x7f); - pci_write_config8(dev, 0x7f, 0x02); - - /* WARNING: Need to copy some registers from NB (D0F3) to SB (D0F7). */ - - regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */ - pci_write_config8(dev, 0x57, regm); - - regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */ - pci_write_config8(dev, 0x61, regm); - - regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */ - pci_write_config8(dev, 0x62, regm); - - regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */ - pci_write_config8(dev, 0xe6, regm); - - regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */ - - /* - * All access bits for 0xE0000-0xEFFFF encode as just 2 bits! - * So the NB reg is quite inconsistent, we expect there only 0xff or 0x00, - * and write them to 0x63 7-6 but! VIA 8237A has the mirror at 0x64! - */ - if (regm3 == 0xff) - regm3 = 0xc0; - else - regm3 = 0x0; - - /* Shadow page F + memhole copy */ - regm = pci_read_config8(devfun3, 0x83); - pci_write_config8(dev, 0x63, regm3 | (regm & 0x3F)); -} - - - -/** - * Setup the V-Link for VT8237R, 8X mode. - * - * For K8T890CF VIA recommends what is in VIA column, AW is award 8X: - * - * REG DEF AW VIA-8X VIA-4X - * ----------------------------- - * NB V-Link Manual Driving Control strobe 0xb5 0x46 0x46 0x88 0x88 - * NB V-Link Manual Driving Control - Data 0xb6 0x46 0x46 0x88 0x88 - * NB V-Link Receiving Strobe Delay 0xb7 0x02 0x02 0x61 0x01 - * NB V-Link Compensation Control bit4,0 (b5,b6) 0xb4 0x10 0x10 0x11 0x11 - * SB V-Link Strobe Drive Control 0xb9 0x00 0xa5 0x98 0x98 - * SB V-Link Data drive Control???? 0xba 0x00 0xbb 0x77 0x77 - * SB V-Link Receive Strobe Delay???? 0xbb 0x04 0x11 0x11 0x11 - * SB V-Link Compensation Control bit0 (use b9) 0xb8 0x00 0x01 0x01 0x01 - * V-Link CKG Control 0xb0 0x05 0x05 0x06 0x03 - * V-Link CKG Control 0xb1 0x05 0x05 0x01 0x03 - */ - -static void vt8237r_vlink_init(struct device *dev) -{ - u8 reg; - - /* - * This init code is valid only for the VT8237R! For different - * sounthbridges (e.g. VT8237A, VT8237S, VT8237 (without plus R) - * and VT8251) a different init code is required. - */ - - pci_write_config8(dev, 0xb5, 0x88); - pci_write_config8(dev, 0xb6, 0x88); - pci_write_config8(dev, 0xb7, 0x61); - - reg = pci_read_config8(dev, 0xb4); - reg |= 0x11; - pci_write_config8(dev, 0xb4, reg); - - pci_write_config8(dev, 0xb9, 0x98); - pci_write_config8(dev, 0xba, 0x77); - pci_write_config8(dev, 0xbb, 0x11); - - reg = pci_read_config8(dev, 0xb8); - reg |= 0x1; - pci_write_config8(dev, 0xb8, reg); - - pci_write_config8(dev, 0xb0, 0x06); - pci_write_config8(dev, 0xb1, 0x01); - - /* Program V-link 8X 16bit full duplex, parity enabled. */ - pci_write_config8(dev, 0x48, 0xa3); -} - -static void ctrl_init(struct device *dev) { - - /* TODO: Fix some ordering issue fo V-link set Rx77[6] and PCI1_Rx4F[0] - should to 1 */ - - /* C2P Read ACK Return Priority */ - /* PCI CFG Address bits[27:24] are used as extended register address - bit[11:8] */ - - pci_write_config8(dev, 0x47, 0x30); - - /* VT8237R specific configuration other SB are done in their own directories */ - - device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); - if (devsb) { - vt8237r_vlink_init(dev); - vt8237r_cfg(dev, devsb); - } - -} - -static const struct device_operations ctrl_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ctrl_init, - .ops_pci = 0, -}; - -static const struct pci_driver northbridge_driver_t __pci_driver = { - .ops = &ctrl_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_7, -}; - -static const struct pci_driver northbridge_driver_tcf __pci_driver = { - .ops = &ctrl_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CF_7, -}; - -static const struct pci_driver northbridge_driver_m __pci_driver = { - .ops = &ctrl_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8M890CE_7, -}; diff --git a/src/southbridge/via/k8t890/k8t890_dram.c b/src/southbridge/via/k8t890/k8t890_dram.c deleted file mode 100644 index 6c52fb1d02..0000000000 --- a/src/southbridge/via/k8t890/k8t890_dram.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Rudolf Marek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "k8t890.h" - -static void dram_enable(struct device *dev) -{ - msr_t msr; - u16 reg; - - /* - * Enable Lowest Interrupt arbitration for APIC, enable NB APIC - * decoding, MSI support, no SMRAM, compatible SMM. - */ - pci_write_config8(dev, 0x86, 0x39); - - /* - * We want to use the 0xC0000-0xEFFFF as RAM mark area as RW, even if - * memory is doing K8 the DMA from SB will fail if we have it wrong, - * AND even we have it here, we must later copy it to SB to make it work :/ - */ - - /* For CC000-CFFFF, bits 7:6 (10 = REn, 01 = WEn) bits 1:0 for - * C0000-C3FFF etc. - */ - pci_write_config8(dev, 0x80, 0xff); - /* For page D0000-DFFFF */ - pci_write_config8(dev, 0x81, 0xff); - /* For page E0000-EFFFF */ - pci_write_config8(dev, 0x82, 0xff); - pci_write_config8(dev, 0x83, 0x30); - - msr = rdmsr(TOP_MEM); - reg = pci_read_config16(dev, 0x84); - reg &= 0xf; - pci_write_config16(dev, 0x84, (msr.lo >> 16) | reg); - - reg = pci_read_config16(dev, 0x88); - reg &= 0xf800; - - /* The Address Next to the Last Valid DRAM Address */ - pci_write_config16(dev, 0x88, (msr.lo >> 24) | reg); - -} - -#if CONFIG_GFXUMA -extern uint64_t uma_memory_base, uma_memory_size; -#endif - -static void dram_enable_k8m890(struct device *dev) -{ -#if CONFIG_GFXUMA - msr_t msr; - int ret; - unsigned int fbbits; - - /* use CMOS */ - if (CONFIG_VIDEO_MB == -1) { - ret = get_option(&fbbits, "videoram_size"); - if (ret) { - printk(BIOS_WARNING, "Failed to get videoram size (error %d), using default.\n", ret); - fbbits = 5; - } - - if ((fbbits < 1) || (fbbits > 7)) { - printk(BIOS_WARNING, "Invalid videoram size (%d), using default.\n", - 4 << fbbits); - fbbits = 5; - } - uma_memory_size = 4 << (fbbits + 20); - } else { - uma_memory_size = (CONFIG_VIDEO_MB << 20); - } - - msr = rdmsr(TOP_MEM); - uma_memory_base = msr.lo - uma_memory_size; - printk(BIOS_INFO, "K8M890: UMA base is %llx size is %u (MB)\n", uma_memory_base, - (u32) (uma_memory_size / 1024 / 1024)); - /* enable VGA, so the bridges gets VGA_EN and resources are set */ - pci_write_config8(dev, 0xa1, 0x80); -#endif - dram_enable(dev); -} - -int -k8m890_host_fb_size_get(void) -{ - struct device *dev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M890CE_3, 0); - unsigned char tmp; - - tmp = pci_read_config8(dev, 0xA1); - tmp >>= 4; - if (tmp & 0x08) - return 4 << (tmp & 7); - else - return 0; -} - -static void dram_init_fb(struct device *dev) -{ -#if CONFIG_GFXUMA - /* Important bits: - * Enable the internal GFX bit 7 of reg 0xa1 plus in same reg: - * bits 6:4 X fbuffer size will be 2^(X+2) or 100 = 64MB, 101 = 128MB - * bits 3:0 BASE [31:28] - * reg 0xa0 bits 7:1 BASE [27:21] bit0 enable CPU access - */ - unsigned int fbbits = 0; - u8 tmp; - - fbbits = ((log2(uma_memory_size >> 20) - 2) << 4); - printk(BIOS_INFO, "K8M890: Using a %dMB framebuffer.\n", (unsigned int) (uma_memory_size >> 20)); - - /* Step 1: enable UMA but no FB */ - pci_write_config8(dev, 0xa1, 0x80); - - /* Step 2: enough is just the FB size, the CPU accessible address is not needed */ - tmp = fbbits | 0x80; - pci_write_config8(dev, 0xa1, tmp); - - /* TODO K8 needs some UMA fine tuning too maybe call some generic routine here? */ -#endif -} - -static const struct device_operations dram_ops_t = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .enable = dram_enable, - .ops_pci = 0, -}; - -static const struct device_operations dram_ops_m = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .enable = dram_enable_k8m890, - .init = dram_init_fb, - .ops_pci = 0, -}; - -static const struct pci_driver northbridge_driver_t __pci_driver = { - .ops = &dram_ops_t, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_3, -}; - -static const struct pci_driver northbridge_driver_tcf __pci_driver = { - .ops = &dram_ops_t, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CF_3, -}; - -static const struct pci_driver northbridge_driver_m __pci_driver = { - .ops = &dram_ops_m, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8M890CE_3, -}; diff --git a/src/southbridge/via/k8t890/k8t890_early_car.c b/src/southbridge/via/k8t890/k8t890_early_car.c deleted file mode 100644 index 94162cb90c..0000000000 --- a/src/southbridge/via/k8t890/k8t890_early_car.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Rudolf Marek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* - * Seems the link and width of HT link needs to be setup too, you need to - * generate PCI reset or LDTSTOP to apply. - */ - -#include -#include -#include -#include "k8t890.h" - -/* The 256 bytes of NVRAM for S3 storage, 256B aligned */ -#define K8T890_NVRAM_IO_BASE 0xf00 -#define K8T890_MULTIPLE_FN_EN 0x4f - -/* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */ -static u8 ldtreg[3] = {0x86, 0xa6, 0xc6}; - -/* This functions sets KT890 link frequency and width to same values as - * it has been setup on K8 side, by AMD NB init. - */ - -u8 k8t890_early_setup_ht(void) -{ - u8 awidth, afreq, cldtfreq, reg; - u8 cldtwidth_in, cldtwidth_out, vldtwidth_in, vldtwidth_out, ldtnr, width; - u16 vldtcaps; - - /* hack, enable NVRAM in chipset */ - pci_write_config8(PCI_DEV(0, 0x0, 0), K8T890_MULTIPLE_FN_EN, 0x01); - - /* - * NVRAM I/O base at K8T890_NVRAM_IO_BASE - */ - - pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa2, (K8T890_NVRAM_IO_BASE >> 8)); - reg = pci_read_config8(PCI_DEV(0, 0x0, 2), 0xa1); - reg |= 0x1; - pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa1, reg); - - /* check if connected non coherent, initcomplete (find the SB on K8 side) */ - ldtnr = 0; - if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0x98)) { - ldtnr = 0; - } else if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0xb8)) { - ldtnr = 1; - } else if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0xd8)) { - ldtnr = 2; - } - - print_debug("K8T890 found at LDT "); - print_debug_hex8(ldtnr); - - /* get the maximum widths for both sides */ - cldtwidth_in = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) & 0x7; - cldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) >> 4) & 0x7; - vldtwidth_in = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x66) & 0x7; - vldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x0, 0), 0x66) >> 4) & 0x7; - - width = MIN(MIN(MIN(cldtwidth_out, cldtwidth_in), vldtwidth_out), vldtwidth_in); - print_debug(" Agreed on width: "); - print_debug_hex8(width); - - awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x67); - - /* Update the desired HT LNK to match AMD NB max from VIA NB is 0x1 */ - width = (width == 0x01) ? 0x11 : 0x00; - - pci_write_config8(PCI_DEV(0, 0x0, 0), 0x67, width); - - /* Get programmed HT freq at base 0x89 */ - cldtfreq = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr] + 3) & 0xf; - print_debug(" CPU programmed to HT freq: "); - print_debug_hex8(cldtfreq); - - print_debug(" VIA HT caps: "); - vldtcaps = pci_read_config16(PCI_DEV(0, 0, 0), 0x6e); - print_debug_hex16(vldtcaps); - - if (!(vldtcaps & (1 << cldtfreq ))) { - die("Chipset does not support desired HT frequency\n"); - } - - afreq = pci_read_config8(PCI_DEV(0, 0x0, 0), 0x6d); - pci_write_config8(PCI_DEV(0, 0x0, 0), 0x6d, cldtfreq); - print_debug("\n"); - - /* no reset needed */ - if ((width == awidth) && (afreq == cldtfreq)) { - return 0; - } - - return 1; -} - -static inline int s3_save_nvram_early(u32 dword, int size, int nvram_pos) -{ - - printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); - switch (size) { - case 1: - outb((dword & 0xff), K8T890_NVRAM_IO_BASE+nvram_pos); - nvram_pos +=1; - break; - case 2: - outw((dword & 0xffff), K8T890_NVRAM_IO_BASE+nvram_pos); - nvram_pos +=2; - break; - default: - outl(dword, K8T890_NVRAM_IO_BASE+nvram_pos); - nvram_pos +=4; - break; - } - return nvram_pos; -} - -static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) -{ - switch (size) { - case 1: - *old_dword &= ~0xff; - *old_dword |= inb(K8T890_NVRAM_IO_BASE+nvram_pos); - nvram_pos +=1; - break; - case 2: - *old_dword &= ~0xffff; - *old_dword |= inw(K8T890_NVRAM_IO_BASE+nvram_pos); - nvram_pos +=2; - break; - default: - *old_dword = inl(K8T890_NVRAM_IO_BASE+nvram_pos); - nvram_pos +=4; - break; - } - printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", * old_dword, size, nvram_pos-size); - return nvram_pos; -} - -/* this should be a function -struct cbmem_entry *get_cbmem_toc(void) { -*/ - -#define get_cbmem_toc() ((struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC)) diff --git a/src/southbridge/via/k8t890/k8t890_error.c b/src/southbridge/via/k8t890/k8t890_error.c deleted file mode 100644 index a9b10d56bc..0000000000 --- a/src/southbridge/via/k8t890/k8t890_error.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Rudolf Marek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include - -static void error_enable(struct device *dev) -{ - /* - * bit0 - Enable V-link parity error reporting in 0x50 bit0 (RWC) - * bit6 - Parity Error/SERR# Report Through V-Link to SB - * bit7 - Parity Error/SERR# Report Through NMI - */ - pci_write_config8(dev, 0x58, 0x81); - - /* TODO: enable AGP errors reporting on K8M890 */ -} - -static const struct device_operations error_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .enable = error_enable, - .ops_pci = 0, -}; - -static const struct pci_driver northbridge_driver_t __pci_driver = { - .ops = &error_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_1, -}; - -static const struct pci_driver northbridge_driver_tcf __pci_driver = { - .ops = &error_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CF_1, -}; - -static const struct pci_driver northbridge_driver_m __pci_driver = { - .ops = &error_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8M890CE_1, -}; diff --git a/src/southbridge/via/k8t890/k8t890_host.c b/src/southbridge/via/k8t890/k8t890_host.c deleted file mode 100644 index 9a0118c778..0000000000 --- a/src/southbridge/via/k8t890/k8t890_host.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Rudolf Marek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include "k8t890.h" - -static void host_enable(struct device *dev) -{ - /* Multiple function control */ - pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01); - -} - - -static void host_init(struct device *dev) -{ - u8 reg; - - /* AGP Capability Header Control */ - reg = pci_read_config8(dev, 0x4d); - reg |= 0x20; /* GART access enabled by either D0F0 Rx90[8] or D1F0 Rx90[8] */ - pci_write_config8(dev, 0x4d, reg); - - /* GD Output Stagger Delay */ - reg = pci_read_config8(dev, 0x42); - reg |= 0x10; /* AD[31:16] with 1ns */ - pci_write_config8(dev, 0x42, reg); - - /* AGP Control */ - reg = pci_read_config8(dev, 0xbc); - reg |= 0x20; /* AGP Read Snoop DRAM Post-Write Buffer */ - pci_write_config8(dev, 0xbc, reg); - -} - -static const struct device_operations host_ops_t = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .enable = host_enable, - .ops_pci = 0, -}; - -static const struct device_operations host_ops_m = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .enable = host_enable, - .init = host_init, - .ops_pci = 0, -}; - -static const struct pci_driver northbridge_driver_t __pci_driver = { - .ops = &host_ops_t, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_0, -}; - -static const struct pci_driver northbridge_driver_tcf __pci_driver = { - .ops = &host_ops_t, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CF_0, -}; - -static const struct pci_driver northbridge_driver_m __pci_driver = { - .ops = &host_ops_m, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8M890CE_0, -}; diff --git a/src/southbridge/via/k8t890/k8t890_host_ctrl.c b/src/southbridge/via/k8t890/k8t890_host_ctrl.c deleted file mode 100644 index 43d01ee369..0000000000 --- a/src/southbridge/via/k8t890/k8t890_host_ctrl.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Rudolf Marek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include "k8t890.h" - -/* this may be later merged */ - -/* This fine tunes the HT link settings, which were loaded by ROM strap. */ -static void host_ctrl_enable_k8t890(struct device *dev) -{ - dump_south(dev); - - /* - * Bit 4 is reserved but set by AW. Set PCI to HT outstanding - * requests to 3. - */ - pci_write_config8(dev, 0xa0, 0x13); - - /* - * NVRAM I/O base at K8T890_NVRAM_IO_BASE - * Some bits are set and reserved. - */ - pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8)); - - /* enable NB NVRAM and enable non-posted PCI writes. */ - pci_write_config8(dev, 0xa1, 0x8f); - /* Arbitration control, some bits are reserved. */ - pci_write_config8(dev, 0xa5, 0x3c); - - /* Arbitration control 2 */ - pci_write_config8(dev, 0xa6, 0x80); - - /* this will be possibly removed, when I figure out - * if the ROM SIP is good, second reason is that the - * unknown bits are AGP related, which are dummy on K8T890 - */ - - writeback(dev, 0xa0, 0x13); /* Bit4 is reserved! */ - writeback(dev, 0xa1, 0x8e); /* Some bits are reserved. */ - writeback(dev, 0xa2, 0x0e); /* I/O NVRAM base 0xe00-0xeff disabled. */ - writeback(dev, 0xa3, 0x31); - writeback(dev, 0xa4, 0x30); - - writeback(dev, 0xa5, 0x3c); /* Some bits reserved. */ - writeback(dev, 0xa6, 0x80); /* Some bits reserved. */ - writeback(dev, 0xa7, 0x86); /* Some bits reserved. */ - writeback(dev, 0xa8, 0x7f); /* Some bits reserved. */ - writeback(dev, 0xa9, 0xcf); /* Some bits reserved. */ - writeback(dev, 0xaa, 0x44); - writeback(dev, 0xab, 0x22); - writeback(dev, 0xac, 0x35); /* Maybe bit0 is read-only? */ - - writeback(dev, 0xae, 0x22); - writeback(dev, 0xaf, 0x40); - /* b0 is missing. */ - writeback(dev, 0xb1, 0x13); - writeback(dev, 0xb4, 0x02); /* Some bits are reserved. */ - writeback(dev, 0xc0, 0x20); - writeback(dev, 0xc1, 0xaa); - writeback(dev, 0xc2, 0xaa); - writeback(dev, 0xc3, 0x02); - writeback(dev, 0xc4, 0x50); - writeback(dev, 0xc5, 0x50); - - dump_south(dev); -} - -/* This fine tunes the HT link settings, which were loaded by ROM strap. */ -static void host_ctrl_enable_k8m890(struct device *dev) { - - /* - * Set PCI to HT outstanding requests to 03. - * Bit 4 32 AGP ADS Read Outstanding Request Number - */ - pci_write_config8(dev, 0xa0, 0x13); - - /* - * NVRAM I/O base at K8T890_NVRAM_IO_BASE - */ - - pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8)); - - /* Enable NVRAM and enable non-posted PCI writes. */ - pci_write_config8(dev, 0xa1, 0x8f); - - /* Arbitration control */ - pci_write_config8(dev, 0xa5, 0x3c); - - /* Arbitration control 2, Enable C2NOW delay to PSTATECTL */ - pci_write_config8(dev, 0xa6, 0x83); - -} -#if 0 -struct cbmem_entry *get_cbmem_toc(void) { - return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); -} -#endif -void set_cbmem_toc(struct cbmem_entry *toc) { - outl((u32) toc, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); -} - -static const struct device_operations host_ctrl_ops_t = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .enable = host_ctrl_enable_k8t890, - .ops_pci = 0, -}; - -static const struct device_operations host_ctrl_ops_m = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .enable = host_ctrl_enable_k8m890, - .ops_pci = 0, -}; - -static const struct pci_driver northbridge_driver_t __pci_driver = { - .ops = &host_ctrl_ops_t, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_2, -}; - -static const struct pci_driver northbridge_driver_m __pci_driver = { - .ops = &host_ctrl_ops_m, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8M890CE_2, -}; diff --git a/src/southbridge/via/k8t890/k8t890_pcie.c b/src/southbridge/via/k8t890/k8t890_pcie.c deleted file mode 100644 index 2840bf3b2d..0000000000 --- a/src/southbridge/via/k8t890/k8t890_pcie.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Rudolf Marek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include -#include "k8t890.h" - -/* - * Note: - * The pcie bridges are similar to the VX800 ones documented at - * http://linux.via.com.tw/ - */ - -static void pcie_common_init(struct device *dev) -{ - u8 reg; - int i, up; - - /* Disable downstream read cycle retry, - * otherwise the bus scan will hang if no device is plugged in. */ - reg = pci_read_config8(dev, 0xa3); - pci_write_config8(dev, 0xa3, reg & ~0x01); - - /* Use PHY negotiation for lane config */ - reg = pci_read_config8(dev, 0xc1); - pci_write_config8(dev, 0xc1, reg & ~0x1f); - - /* Award has 0xb, VIA recommends 0xd, default 0x8. - * bit4: receive polarity change control - * bits3:2: squelch window select 64~175mv - * bit1: Number of non-idle bits detected before exiting idle state - * 0: 10 bits, 1: 2 bits - * bit0: Number of idle bits detected before entering idle state - * 0: 10 bits, 1: 2 bits - */ - pci_write_config8(dev, 0xe1, 0xb); - - /* Set replay timer limit. */ - pci_write_config8(dev, 0xb1, 0xf0); - - /* Enable link. */ - reg = pci_read_config8(dev, 0x50); - pci_write_config8(dev, 0x50, reg & ~0x10); - - /* Wait up to 100ms for link to come up */ - up = 0; - for (i=0; i<1000; i++) { - if (pci_read_config16(dev, 0x52) & (1<<13)) { - up = 1; - break; - } - udelay(100); - } - - printk(BIOS_SPEW, "%s PCIe link ", dev_path(dev)); - if (up) - printk(BIOS_SPEW, "up after %d us\n", i*100); - else - printk(BIOS_SPEW, "timeout\n"); - - dump_south(dev); -} - -static void peg_init(struct device *dev) -{ - u8 reg; - - printk(BIOS_DEBUG, "Configuring PCIe PEG\n"); - dump_south(dev); - - /* Disable link. */ - reg = pci_read_config8(dev, 0x50); - pci_write_config8(dev, 0x50, reg | 0x10); - - /* - * pci_write_config8(dev, 0xe2, 0x0); - * pci_write_config8(dev, 0xe3, 0x92); - */ - - /* Bit0 = 1 SDP (Start DLLP) always at Lane0. */ - reg = pci_read_config8(dev, 0xb8); - pci_write_config8(dev, 0xb8, reg | 0x1); - - /* - * Downstream wait and Upstream Checking Malformed TLP through - * "Byte Enable Rule" And "Over 4K Boundary Rule". - */ - reg = pci_read_config8(dev, 0xa4); - pci_write_config8(dev, 0xa4, reg | 0x30); - - pcie_common_init(dev); -} - -static void pcie_init(struct device *dev) -{ - u8 reg; - - printk(BIOS_DEBUG, "Configuring PCIe PEXs\n"); - dump_south(dev); - - /* Disable link. */ - reg = pci_read_config8(dev, 0x50); - pci_write_config8(dev, 0x50, reg | 0x10); - - pcie_common_init(dev); -} - -static const struct device_operations peg_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .enable = peg_init, - .scan_bus = pciexp_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, -}; - -static const struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .enable = pcie_init, - .scan_bus = pciexp_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, -}; - -static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &peg_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_PEG, -}; - -static const struct pci_driver pcie_drvd3f0 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX0, -}; - -static const struct pci_driver pcie_drvd3f1 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX1, -}; - -static const struct pci_driver pcie_drvd3f2 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX2, -}; - -static const struct pci_driver pcie_drvd3f3 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX3, -}; diff --git a/src/southbridge/via/k8t890/k8t890_traf_ctrl.c b/src/southbridge/via/k8t890/k8t890_traf_ctrl.c deleted file mode 100644 index 55b3a13ac7..0000000000 --- a/src/southbridge/via/k8t890/k8t890_traf_ctrl.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Rudolf Marek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include "k8t890.h" - -extern unsigned long log2(unsigned long x); - -static void mmconfig_set_resources(device_t dev) -{ - struct resource *resource; - u8 reg; - - resource = find_resource(dev, K8T890_MMCONFIG_MBAR); - if (resource) { - report_resource_stored(dev, resource, ""); - - /* Remember this resource has been stored. */ - resource->flags |= IORESOURCE_STORED; - pci_write_config8(dev, K8T890_MMCONFIG_MBAR, - (resource->base >> 28)); - reg = pci_read_config8(dev, 0x60); - reg |= 0x3; - /* Enable MMCONFIG decoding. */ - pci_write_config8(dev, 0x60, reg); - } - pci_dev_set_resources(dev); -} - -static void apic_mmconfig_read_resources(device_t dev) -{ - struct resource *res; - pci_dev_read_resources(dev); - - res = new_resource(dev, 0x40); - /* NB APIC fixed to this address. */ - res->base = K8T890_APIC_BASE; - res->size = 256; - res->limit = res->base + res->size - 1; - res->align = 8; - res->gran = 8; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Add an MMCONFIG resource. */ - res = new_resource(dev, K8T890_MMCONFIG_MBAR); - res->size = 256 * 1024 * 1024; - res->align = log2(res->size); - res->gran = log2(res->size); - res->limit = 0xffffffff; /* 4G */ - res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE; -} - -static void traf_ctrl_enable_generic(struct device *dev) -{ - volatile u32 *apic; - u32 data; - - /* no device2 redirect, enable just one device behind - * bridge device 2 and device 3). - */ - pci_write_config8(dev, 0x60, 0x08); - - /* Will enable MMCONFIG later. */ - pci_write_config8(dev, 0x64, 0x23); - /* No extended RCRB Base Address. */ - pci_write_config8(dev, 0x62, 0x00); - - /* Offset80 ->95 bit 4 in 1 in Award. */ - - /* Enable APIC, to K8T890_APIC_BASE. */ - pci_write_config8(dev, 0x41, 0x00); - pci_write_config8(dev, 0x40, 0x8c); - /* BT_INTR enable, APIC Nonshare Mode Enable. */ - pci_write_config8(dev, 0x42, 0x5); - - apic = (u32 *)K8T890_APIC_BASE; - - /* Set APIC to FSB transported messages. */ - apic[0] = 3; - data = apic[4]; - apic[4] = (data & 0xFFFFFE) | 1; - - /* Set APIC ID. */ - apic[0] = 0; - data = apic[4]; - apic[4] = (data & 0xF0FFFF) | (K8T890_APIC_ID << 24); -} - -static void traf_ctrl_enable_k8m890(struct device *dev) -{ - traf_ctrl_enable_generic(dev); -} - -static void traf_ctrl_enable_k8t890(struct device *dev) -{ - u8 reg; - - traf_ctrl_enable_generic(dev); - - /* Enable D3F1-D3F3 */ - reg = pci_read_config8(dev, 0x60); - pci_write_config8(dev, 0x60, 0x80 | reg); -} - -static const struct device_operations traf_ctrl_ops_m = { - .read_resources = apic_mmconfig_read_resources, - .set_resources = mmconfig_set_resources, - .enable_resources = pci_dev_enable_resources, - .enable = traf_ctrl_enable_k8m890, - .ops_pci = 0, -}; - -static const struct device_operations traf_ctrl_ops_t = { - .read_resources = apic_mmconfig_read_resources, - .set_resources = mmconfig_set_resources, - .enable_resources = pci_dev_enable_resources, - .enable = traf_ctrl_enable_k8t890, - .ops_pci = 0, -}; - -static const struct pci_driver northbridge_driver_t __pci_driver = { - .ops = &traf_ctrl_ops_t, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_5, -}; - -static const struct pci_driver northbridge_driver_tcf __pci_driver = { - .ops = &traf_ctrl_ops_t, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CF_5, -}; - -static const struct pci_driver northbridge_driver_m __pci_driver = { - .ops = &traf_ctrl_ops_m, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8M890CE_5, -}; diff --git a/src/southbridge/via/k8t890/pcie.c b/src/southbridge/via/k8t890/pcie.c new file mode 100644 index 0000000000..2840bf3b2d --- /dev/null +++ b/src/southbridge/via/k8t890/pcie.c @@ -0,0 +1,176 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include "k8t890.h" + +/* + * Note: + * The pcie bridges are similar to the VX800 ones documented at + * http://linux.via.com.tw/ + */ + +static void pcie_common_init(struct device *dev) +{ + u8 reg; + int i, up; + + /* Disable downstream read cycle retry, + * otherwise the bus scan will hang if no device is plugged in. */ + reg = pci_read_config8(dev, 0xa3); + pci_write_config8(dev, 0xa3, reg & ~0x01); + + /* Use PHY negotiation for lane config */ + reg = pci_read_config8(dev, 0xc1); + pci_write_config8(dev, 0xc1, reg & ~0x1f); + + /* Award has 0xb, VIA recommends 0xd, default 0x8. + * bit4: receive polarity change control + * bits3:2: squelch window select 64~175mv + * bit1: Number of non-idle bits detected before exiting idle state + * 0: 10 bits, 1: 2 bits + * bit0: Number of idle bits detected before entering idle state + * 0: 10 bits, 1: 2 bits + */ + pci_write_config8(dev, 0xe1, 0xb); + + /* Set replay timer limit. */ + pci_write_config8(dev, 0xb1, 0xf0); + + /* Enable link. */ + reg = pci_read_config8(dev, 0x50); + pci_write_config8(dev, 0x50, reg & ~0x10); + + /* Wait up to 100ms for link to come up */ + up = 0; + for (i=0; i<1000; i++) { + if (pci_read_config16(dev, 0x52) & (1<<13)) { + up = 1; + break; + } + udelay(100); + } + + printk(BIOS_SPEW, "%s PCIe link ", dev_path(dev)); + if (up) + printk(BIOS_SPEW, "up after %d us\n", i*100); + else + printk(BIOS_SPEW, "timeout\n"); + + dump_south(dev); +} + +static void peg_init(struct device *dev) +{ + u8 reg; + + printk(BIOS_DEBUG, "Configuring PCIe PEG\n"); + dump_south(dev); + + /* Disable link. */ + reg = pci_read_config8(dev, 0x50); + pci_write_config8(dev, 0x50, reg | 0x10); + + /* + * pci_write_config8(dev, 0xe2, 0x0); + * pci_write_config8(dev, 0xe3, 0x92); + */ + + /* Bit0 = 1 SDP (Start DLLP) always at Lane0. */ + reg = pci_read_config8(dev, 0xb8); + pci_write_config8(dev, 0xb8, reg | 0x1); + + /* + * Downstream wait and Upstream Checking Malformed TLP through + * "Byte Enable Rule" And "Over 4K Boundary Rule". + */ + reg = pci_read_config8(dev, 0xa4); + pci_write_config8(dev, 0xa4, reg | 0x30); + + pcie_common_init(dev); +} + +static void pcie_init(struct device *dev) +{ + u8 reg; + + printk(BIOS_DEBUG, "Configuring PCIe PEXs\n"); + dump_south(dev); + + /* Disable link. */ + reg = pci_read_config8(dev, 0x50); + pci_write_config8(dev, 0x50, reg | 0x10); + + pcie_common_init(dev); +} + +static const struct device_operations peg_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .enable = peg_init, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, +}; + +static const struct device_operations pcie_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .enable = pcie_init, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, +}; + +static const struct pci_driver northbridge_driver __pci_driver = { + .ops = &peg_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_PEG, +}; + +static const struct pci_driver pcie_drvd3f0 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX0, +}; + +static const struct pci_driver pcie_drvd3f1 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX1, +}; + +static const struct pci_driver pcie_drvd3f2 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX2, +}; + +static const struct pci_driver pcie_drvd3f3 __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_PEX3, +}; diff --git a/src/southbridge/via/k8t890/traf_ctrl.c b/src/southbridge/via/k8t890/traf_ctrl.c new file mode 100644 index 0000000000..55b3a13ac7 --- /dev/null +++ b/src/southbridge/via/k8t890/traf_ctrl.c @@ -0,0 +1,157 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "k8t890.h" + +extern unsigned long log2(unsigned long x); + +static void mmconfig_set_resources(device_t dev) +{ + struct resource *resource; + u8 reg; + + resource = find_resource(dev, K8T890_MMCONFIG_MBAR); + if (resource) { + report_resource_stored(dev, resource, ""); + + /* Remember this resource has been stored. */ + resource->flags |= IORESOURCE_STORED; + pci_write_config8(dev, K8T890_MMCONFIG_MBAR, + (resource->base >> 28)); + reg = pci_read_config8(dev, 0x60); + reg |= 0x3; + /* Enable MMCONFIG decoding. */ + pci_write_config8(dev, 0x60, reg); + } + pci_dev_set_resources(dev); +} + +static void apic_mmconfig_read_resources(device_t dev) +{ + struct resource *res; + pci_dev_read_resources(dev); + + res = new_resource(dev, 0x40); + /* NB APIC fixed to this address. */ + res->base = K8T890_APIC_BASE; + res->size = 256; + res->limit = res->base + res->size - 1; + res->align = 8; + res->gran = 8; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* Add an MMCONFIG resource. */ + res = new_resource(dev, K8T890_MMCONFIG_MBAR); + res->size = 256 * 1024 * 1024; + res->align = log2(res->size); + res->gran = log2(res->size); + res->limit = 0xffffffff; /* 4G */ + res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE; +} + +static void traf_ctrl_enable_generic(struct device *dev) +{ + volatile u32 *apic; + u32 data; + + /* no device2 redirect, enable just one device behind + * bridge device 2 and device 3). + */ + pci_write_config8(dev, 0x60, 0x08); + + /* Will enable MMCONFIG later. */ + pci_write_config8(dev, 0x64, 0x23); + /* No extended RCRB Base Address. */ + pci_write_config8(dev, 0x62, 0x00); + + /* Offset80 ->95 bit 4 in 1 in Award. */ + + /* Enable APIC, to K8T890_APIC_BASE. */ + pci_write_config8(dev, 0x41, 0x00); + pci_write_config8(dev, 0x40, 0x8c); + /* BT_INTR enable, APIC Nonshare Mode Enable. */ + pci_write_config8(dev, 0x42, 0x5); + + apic = (u32 *)K8T890_APIC_BASE; + + /* Set APIC to FSB transported messages. */ + apic[0] = 3; + data = apic[4]; + apic[4] = (data & 0xFFFFFE) | 1; + + /* Set APIC ID. */ + apic[0] = 0; + data = apic[4]; + apic[4] = (data & 0xF0FFFF) | (K8T890_APIC_ID << 24); +} + +static void traf_ctrl_enable_k8m890(struct device *dev) +{ + traf_ctrl_enable_generic(dev); +} + +static void traf_ctrl_enable_k8t890(struct device *dev) +{ + u8 reg; + + traf_ctrl_enable_generic(dev); + + /* Enable D3F1-D3F3 */ + reg = pci_read_config8(dev, 0x60); + pci_write_config8(dev, 0x60, 0x80 | reg); +} + +static const struct device_operations traf_ctrl_ops_m = { + .read_resources = apic_mmconfig_read_resources, + .set_resources = mmconfig_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = traf_ctrl_enable_k8m890, + .ops_pci = 0, +}; + +static const struct device_operations traf_ctrl_ops_t = { + .read_resources = apic_mmconfig_read_resources, + .set_resources = mmconfig_set_resources, + .enable_resources = pci_dev_enable_resources, + .enable = traf_ctrl_enable_k8t890, + .ops_pci = 0, +}; + +static const struct pci_driver northbridge_driver_t __pci_driver = { + .ops = &traf_ctrl_ops_t, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_5, +}; + +static const struct pci_driver northbridge_driver_tcf __pci_driver = { + .ops = &traf_ctrl_ops_t, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CF_5, +}; + +static const struct pci_driver northbridge_driver_m __pci_driver = { + .ops = &traf_ctrl_ops_m, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8M890CE_5, +}; diff --git a/src/southbridge/via/vt8231/Makefile.inc b/src/southbridge/via/vt8231/Makefile.inc index 938d3cebe3..b9e7ef6f1d 100644 --- a/src/southbridge/via/vt8231/Makefile.inc +++ b/src/southbridge/via/vt8231/Makefile.inc @@ -18,8 +18,8 @@ ## driver-y += vt8231.c -driver-y += vt8231_lpc.c -driver-y += vt8231_acpi.c -driver-y += vt8231_ide.c -driver-y += vt8231_nic.c -#driver-y += vt8231_usb.c +driver-y += lpc.c +driver-y += acpi.c +driver-y += ide.c +driver-y += nic.c +#driver-y += usb.c diff --git a/src/southbridge/via/vt8231/acpi.c b/src/southbridge/via/vt8231/acpi.c new file mode 100644 index 0000000000..647910aef6 --- /dev/null +++ b/src/southbridge/via/vt8231/acpi.c @@ -0,0 +1,43 @@ +#include +#include +#include +#include +#include + +static void acpi_init(struct device *dev) +{ + printk(BIOS_DEBUG, "Configuring VIA ACPI\n"); + + // Set ACPI base address to IO 0x4000 + pci_write_config32(dev, 0x48, 0x4001); + + // Enable ACPI access (and setup like award) + pci_write_config8(dev, 0x41, 0x84); + + // Set hardware monitor base address to IO 0x6000 + pci_write_config32(dev, 0x70, 0x6001); + + // Enable hardware monitor (and setup like award) + pci_write_config8(dev, 0x74, 0x01); + + // set IO base address to 0x5000 + pci_write_config32(dev, 0x90, 0x5001); + + // Enable SMBus + pci_write_config8(dev, 0xd2, 0x01); +} + +static struct device_operations acpi_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = acpi_init, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver northbridge_driver __pci_driver = { + .ops = &acpi_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_8231_4, +}; diff --git a/src/southbridge/via/vt8231/early_serial.c b/src/southbridge/via/vt8231/early_serial.c new file mode 100644 index 0000000000..af5a7729ee --- /dev/null +++ b/src/southbridge/via/vt8231/early_serial.c @@ -0,0 +1,74 @@ +/* + * Enable the serial evices on the VIA + */ + + +/* The base address is 0x15c, 0x2e, depending on config bytes */ + +#define SIO_BASE 0x3f0 +#define SIO_DATA SIO_BASE+1 + +static void vt8231_writesuper(uint8_t reg, uint8_t val) +{ + outb(reg, SIO_BASE); + outb(val, SIO_DATA); +} + +static void vt8231_writesiobyte(uint16_t reg, uint8_t val) +{ + outb(val, reg); +} + +static void vt8231_writesioword(uint16_t reg, uint16_t val) +{ + outw(val, reg); +} + + +/* regs we use: 85, and the southbridge devfn is defined by the + mainboard + */ + +static void enable_vt8231_serial(void) +{ + uint8_t c; + device_t dev; + outb(6, 0x80); + dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); + + if (dev == PCI_DEV_INVALID) { + outb(7, 0x80); + die("Serial controller not found\n"); + } + + /* first, you have to enable the superio and superio config. + put a 6 reg 80 + */ + c = pci_read_config8(dev, 0x50); + c |= 6; + pci_write_config8(dev, 0x50, c); + outb(2, 0x80); + // now go ahead and set up com1. + // set address + vt8231_writesuper(0xf4, 0xfe); + // enable serial out + vt8231_writesuper(0xf2, 7); + // That's it for the sio stuff. + // movl $SUPERIOCONFIG, %eax + // movb $9, %dl + // PCI_WRITE_CONFIG_BYTE + // set up reg to set baud rate. + vt8231_writesiobyte(0x3fb, 0x80); + // Set 115 kb + vt8231_writesioword(0x3f8, 1); + // Set 9.6 kb + // WRITESIOWORD(0x3f8, 12) + // now set no parity, one stop, 8 bits + vt8231_writesiobyte(0x3fb, 3); + // now turn on RTS, DRT + vt8231_writesiobyte(0x3fc, 3); + // Enable interrupts + vt8231_writesiobyte(0x3f9, 0xf); + // should be done. Dump a char for fun. + vt8231_writesiobyte(0x3f8, 48); +} diff --git a/src/southbridge/via/vt8231/early_smbus.c b/src/southbridge/via/vt8231/early_smbus.c new file mode 100644 index 0000000000..7bf1267b75 --- /dev/null +++ b/src/southbridge/via/vt8231/early_smbus.c @@ -0,0 +1,295 @@ +#define SMBUS_IO_BASE 0x5000 + +#define SMBHSTSTAT 0x0 +#define SMBSLVSTAT 0x1 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBBLKDAT 0x7 +#define SMBSLVCTL 0x8 +#define SMBTRNSADD 0x9 +#define SMBSLVDATA 0xa +#define SMLINK_PIN_CTL 0xe +#define SMBUS_PIN_CTL 0xf + +/* Define register settings */ +#define HOST_RESET 0xff +#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ + + +#define SMBUS_TIMEOUT (100*1000*10) + +static void enable_smbus(void) +{ + device_t dev; + unsigned char c; + /* Power management controller */ + dev = pci_locate_device(PCI_ID(0x1106, 0x8235), 0); + + if (dev == PCI_DEV_INVALID) { + die("SMBUS controller not found\n"); + } + // set IO base address to SMBUS_IO_BASE + pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1); + + // Enable SMBus + c = pci_read_config8(dev, 0xd2); + c |= 5; + pci_write_config8(dev, 0xd2, c); + + /* make it work for I/O ... + */ + dev = pci_locate_device(PCI_ID(0x1106, 0x8231), 0); + c = pci_read_config8(dev, 4); + c |= 1; + pci_write_config8(dev, 4, c); + print_debug_hex8(c); + print_debug(" is the comm register\n"); + + print_debug("SMBus controller enabled\n"); +} + + +static inline void smbus_delay(void) +{ + outb(0x80, 0x80); +} + +static int smbus_wait_until_active(void) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + val = inb(SMBUS_IO_BASE + SMBHSTSTAT); + if ((val & 1)) { + break; + } + } while (--loops); + return loops ? 0 : -4; +} + +static int smbus_wait_until_ready(void) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + val = inb(SMBUS_IO_BASE + SMBHSTSTAT); + if ((val & 1) == 0) { + break; + } + if (loops == (SMBUS_TIMEOUT / 2)) { + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + } + } while (--loops); + return loops ? 0 : -2; +} + +static int smbus_wait_until_done(void) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + + val = inb(SMBUS_IO_BASE + SMBHSTSTAT); + if ((val & 1) == 0) { + break; + } + } while (--loops); + return loops ? 0 : -3; +} + +#if 0 +void smbus_reset(void) +{ + outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); + outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); + outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); + outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); + + smbus_wait_until_ready(); + print_debug("After reset status "); + print_debug_hex8(inb(SMBUS_IO_BASE + SMBHSTSTAT)); + print_debug("\n"); +} +#endif + +#if CONFIG_DEBUG_SMBUS +static void smbus_print_error(unsigned char host_status_register) +{ + + print_err("smbus_error: "); + print_err_hex8(host_status_register); + print_err("\n"); + if (host_status_register & (1 << 4)) { + print_err("Interrup/SMI# was Failed Bus Transaction\n"); + } + if (host_status_register & (1 << 3)) { + print_err("Bus Error\n"); + } + if (host_status_register & (1 << 2)) { + print_err("Device Error\n"); + } + if (host_status_register & (1 << 1)) { + print_err("Interrupt/SMI# was Successful Completion\n"); + } + if (host_status_register & (1 << 0)) { + print_err("Host Busy\n"); + } +} +#endif + +/* + * Copied from intel/i82801dbm early smbus code - suggested by rgm. + * Modifications/check against i2c-viapro driver code from linux-2.4.22 + * and VT8231 Reference Docs - mw. + */ +static int smbus_read_byte(unsigned device, unsigned address) +{ + unsigned char global_status_register; + unsigned char byte; + + if (smbus_wait_until_ready() < 0) { + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + if (smbus_wait_until_ready() < 0) { + return -2; + } + } + + /* setup transaction */ + /* disable interrupts */ + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); + /* set the command/address... */ + outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); + /* set up for a byte data read */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL); + + /* clear any lingering errors, so the transaction will run */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + + /* clear the data byte... */ + outb(0, SMBUS_IO_BASE + SMBHSTDAT0); + + /* start a byte read, with interrupts disabled */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); + /* poll for it to start */ + if (smbus_wait_until_active() < 0) { + return -4; + } + + /* poll for transaction completion */ + if (smbus_wait_until_done() < 0) { + return -3; + } + + /* Ignore the Host Busy & Command Complete ? */ + global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~((1 << 1) | (1 << 0)); + + /* read results of transaction */ + byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); + + if (global_status_register != 0) { + return -1; + } + return byte; +} + +#if 0 +/* SMBus routines borrowed from VIA's Trident Driver */ +/* this works, so I am not going to touch it for now -- rgm */ +static unsigned char smbus_read_byte(unsigned char devAdr, unsigned char bIndex) +{ + unsigned int i; + unsigned char bData; + unsigned char sts = 0; + + /* clear host status */ + outb(0xff, SMBUS_IO_BASE); + + /* check SMBUS ready */ + for (i = 0; i < SMBUS_TIMEOUT; i++) + if ((inb(SMBUS_IO_BASE) & 0x01) == 0) + break; + + /* set host command */ + outb(bIndex, SMBUS_IO_BASE + 3); + + /* set slave address */ + outb(devAdr | 0x01, SMBUS_IO_BASE + 4); + + /* start */ + outb(0x48, SMBUS_IO_BASE + 2); + + /* SMBUS Wait Ready */ + for (i = 0; i < SMBUS_TIMEOUT; i++) + if (((sts = inb(SMBUS_IO_BASE)) & 0x01) == 0) + break; + if ((sts & ~3) != 0) { + smbus_print_error(sts); + return 0; + } + bData = inb(SMBUS_IO_BASE + 5); + + return bData; + +} +#endif +/* for reference, here is the fancier version which we will use at some + * point + */ +# if 0 +int smbus_read_byte(unsigned device, unsigned address, unsigned char *result) +{ + unsigned char host_status_register; + unsigned char byte; + + reset(); + + smbus_wait_until_ready(); + + /* setup transaction */ + /* disable interrupts */ + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); + /* set the command/address... */ + outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); + /* set up for a byte data read */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL); + + /* clear any lingering errors, so the transaction will run */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + + /* clear the data byte... */ + outb(0, SMBUS_IO_BASE + SMBHSTDAT0); + + /* start the command */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); + + /* poll for transaction completion */ + smbus_wait_until_done(); + + host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); + + /* Ignore the In Use Status... */ + host_status_register &= ~(1 << 6); + + /* read results of transaction */ + byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); + smbus_print_error(byte); + + *result = byte; + return host_status_register != 0x02; +} + + +#endif diff --git a/src/southbridge/via/vt8231/enable_rom.c b/src/southbridge/via/vt8231/enable_rom.c new file mode 100644 index 0000000000..bb43420610 --- /dev/null +++ b/src/southbridge/via/vt8231/enable_rom.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Uwe Hermann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include + +static void vt8231_enable_rom(void) +{ + device_t dev; + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_8231), 0); + + /* + * ROM decode control register (0x43): + * + * Bit Decode range + * ----------------- + * 7 0xFFFE0000-0xFFFEFFFF + * 6 0xFFF80000-0xFFFDFFFF + * 5 0xFFF00000-0xFFF7FFFF + * 4 0x000E0000-0x000EFFFF + * 3 0x000D8000-0x000DFFFF + * 2 0x000D0000-0x000D7FFF + * 1 0x000C8000-0x000CFFFF + * 0 0x000C0000-0x000C7FFF + */ + pci_write_config8(dev, 0x43, (1 << 7) | (1 << 6) | (1 << 5)); +} diff --git a/src/southbridge/via/vt8231/ide.c b/src/southbridge/via/vt8231/ide.c new file mode 100644 index 0000000000..46479c4af3 --- /dev/null +++ b/src/southbridge/via/vt8231/ide.c @@ -0,0 +1,113 @@ +#include +#include +#include +#include +#include +#include "chip.h" + +static void ide_init(struct device *dev) +{ + struct southbridge_via_vt8231_config *conf = (struct southbridge_via_vt8231_config *)dev->chip_info; + unsigned char enables; + + if (!conf->enable_native_ide) { + // Run the IDE controller in 'compatiblity mode - i.e. don't use PCI + // interrupts. Using PCI ints confuses linux for some reason. + /* Setting reg 0x42 here does not work. It is set in mainboard/romstage.c + * It probably can only be changed while the IDE is disabled + * or it is possibly a timing issue. Ben Hewson 29 Apr 2007. + */ + + /* + printk(BIOS_INFO, "%s: enabling compatibility IDE addresses\n", __func__); + enables = pci_read_config8(dev, 0x42); + printk(BIOS_DEBUG, "enables in reg 0x42 0x%x\n", enables); + enables &= ~0xc0; // compatability mode + pci_write_config8(dev, 0x42, enables); + enables = pci_read_config8(dev, 0x42); + printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n", enables); + */ + } + + enables = pci_read_config8(dev, 0x40); + printk(BIOS_DEBUG, "enables in reg 0x40 0x%x\n", enables); + enables |= 3; + pci_write_config8(dev, 0x40, enables); + enables = pci_read_config8(dev, 0x40); + printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables); + + // Enable prefetch buffers + enables = pci_read_config8(dev, 0x41); + enables |= 0xf0; + pci_write_config8(dev, 0x41, enables); + + // Lower thresholds (cause award does it) + enables = pci_read_config8(dev, 0x43); + enables &= ~0x0f; + enables |= 0x05; + pci_write_config8(dev, 0x43, enables); + + // PIO read prefetch counter (cause award does it) + pci_write_config8(dev, 0x44, 0x18); + + // Use memory read multiple + pci_write_config8(dev, 0x45, 0x1c); + + // address decoding. + // we want "flexible", i.e. 1f0-1f7 etc. or native PCI + // kevinh@ispiri.com - the standard linux drivers seem ass slow when + // used in native mode - I've changed back to classic + enables = pci_read_config8(dev, 0x9); + printk(BIOS_DEBUG, "enables in reg 0x9 0x%x\n", enables); + // by the book, set the low-order nibble to 0xa. + if (conf->enable_native_ide) { + enables &= ~0xf; + // cf/cg silicon needs an 'f' here. + enables |= 0xf; + } else { + enables &= ~0x5; + } + + pci_write_config8(dev, 0x9, enables); + enables = pci_read_config8(dev, 0x9); + printk(BIOS_DEBUG, "enables in reg 0x9 read back as 0x%x\n", enables); + + // standard bios sets master bit. + enables = pci_read_config8(dev, 0x4); + printk(BIOS_DEBUG, "command in reg 0x4 0x%x\n", enables); + enables |= 7; + + // No need for stepping - kevinh@ispiri.com + enables &= ~0x80; + + pci_write_config8(dev, 0x4, enables); + enables = pci_read_config8(dev, 0x4); + printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables); + + if (!conf->enable_native_ide) { + // Use compatability mode - per award bios + pci_write_config32(dev, 0x10, 0x0); + pci_write_config32(dev, 0x14, 0x0); + pci_write_config32(dev, 0x18, 0x0); + pci_write_config32(dev, 0x1c, 0x0); + + // Force interrupts to use compat mode - just like Award bios + pci_write_config8(dev, 0x3d, 00); + pci_write_config8(dev, 0x3c, 0xff); + } +} + +static struct device_operations ide_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver northbridge_driver __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_82C586_1, +}; diff --git a/src/southbridge/via/vt8231/lpc.c b/src/southbridge/via/vt8231/lpc.c new file mode 100644 index 0000000000..40854dbcf7 --- /dev/null +++ b/src/southbridge/via/vt8231/lpc.c @@ -0,0 +1,165 @@ +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +/* PIRQ init + */ +static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 }; +static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 }; +static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 }; + +/* + Our IDSEL mappings are as follows + PCI slot is AD31 (device 15) (00:14.0) + Southbridge is AD28 (device 12) (00:11.0) +*/ +static void pci_routing_fixup(struct device *dev) +{ + + printk(BIOS_INFO, "%s: dev is %p\n", __func__, dev); + if (dev) { + /* initialize PCI interupts - these assignments depend + on the PCB routing of PINTA-D + + PINTA = IRQ11 + PINTB = IRQ5 + PINTC = IRQ10 + PINTD = IRQ12 + */ + pci_write_config8(dev, 0x55, 0xb0); + pci_write_config8(dev, 0x56, 0xa5); + pci_write_config8(dev, 0x57, 0xc0); + } + + // Standard southbridge components + printk(BIOS_INFO, "setting southbridge\n"); + pci_assign_irqs(0, 0x11, southbridgeIrqs); + + // Ethernet built into southbridge + printk(BIOS_INFO, "setting ethernet\n"); + pci_assign_irqs(0, 0x12, enetIrqs); + + // PCI slot + printk(BIOS_INFO, "setting pci slot\n"); + pci_assign_irqs(0, 0x14, slotIrqs); + printk(BIOS_INFO, "%s: DONE\n", __func__); +} + +static void vt8231_init(struct device *dev) +{ + unsigned char enables; + + printk(BIOS_DEBUG, "vt8231 init\n"); + + // enable the internal I/O decode + enables = pci_read_config8(dev, 0x6C); + enables |= 0x80; + pci_write_config8(dev, 0x6C, enables); + + // Set bit 6 of 0x40, because Award does it (IO recovery time) + // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI + // interrupts can be properly marked as level triggered. + enables = pci_read_config8(dev, 0x40); + pci_write_config8(dev, 0x40, enables); + + // Set 0x42 to 0xf0 to match Award bios + enables = pci_read_config8(dev, 0x42); + enables |= 0xf0; + pci_write_config8(dev, 0x42, enables); + + // Set bit 3 of 0x4a, to match award (dummy pci request) + enables = pci_read_config8(dev, 0x4a); + enables |= 0x08; + pci_write_config8(dev, 0x4a, enables); + + // Set bit 3 of 0x4f to match award (use INIT# as cpu reset) + enables = pci_read_config8(dev, 0x4f); + enables |= 0x08; + pci_write_config8(dev, 0x4f, enables); + + // Set 0x58 to 0x03 to match Award + pci_write_config8(dev, 0x58, 0x03); + + // enable the ethernet/RTC + if (dev) { + enables = pci_read_config8(dev, 0x51); + enables |= 0x18; + pci_write_config8(dev, 0x51, enables); + } + + // enable IDE, since Linux won't do it. + // First do some more things to devfn (17,0) + // note: this should already be cleared, according to the book. + enables = pci_read_config8(dev, 0x50); + printk(BIOS_DEBUG, "IDE enable in reg. 50 is 0x%x\n", enables); + enables &= ~8; // need manifest constant here! + printk(BIOS_DEBUG, "set IDE reg. 50 to 0x%x\n", enables); + pci_write_config8(dev, 0x50, enables); + + // set default interrupt values (IDE) + enables = pci_read_config8(dev, 0x4c); + printk(BIOS_DEBUG, "IRQs in reg. 4c are 0x%x\n", enables & 0xf); + // clear out whatever was there. + enables &= ~0xf; + enables |= 4; + printk(BIOS_DEBUG, "setting reg. 4c to 0x%x\n", enables); + pci_write_config8(dev, 0x4c, enables); + + // set up the serial port interrupts. + // com2 to 3, com1 to 4 + pci_write_config8(dev, 0x46, 0x04); + pci_write_config8(dev, 0x47, 0x03); + pci_write_config8(dev, 0x6e, 0x98); + + /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */ + pci_write_config8(dev, 0x40, 0x54); + //ethernet_fixup(); + + // Start the rtc + rtc_init(0); +} + +static void vt8231_read_resources(device_t dev) +{ + struct resource *res; + + pci_dev_read_resources(dev); + + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x1000UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = IO_APIC_ADDR; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void southbridge_init(struct device *dev) +{ + vt8231_init(dev); + pci_routing_fixup(dev); +} + +static struct device_operations vt8231_lpc_ops = { + .read_resources = vt8231_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = &southbridge_init, + .scan_bus = scan_static_bus, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver lpc_driver __pci_driver = { + .ops = &vt8231_lpc_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_8231, +}; diff --git a/src/southbridge/via/vt8231/nic.c b/src/southbridge/via/vt8231/nic.c new file mode 100644 index 0000000000..5cd6cd8ca1 --- /dev/null +++ b/src/southbridge/via/vt8231/nic.c @@ -0,0 +1,36 @@ +#include +#include +#include +#include +#include + +/* + * Enable the ethernet device and turn off stepping (because it is integrated + * inside the southbridge) + */ +static void nic_init(struct device *dev) +{ + uint8_t byte; + + printk(BIOS_DEBUG, "Configuring VIA LAN\n"); + + /* We don't need stepping - though the device supports it */ + byte = pci_read_config8(dev, PCI_COMMAND); + byte &= ~PCI_COMMAND_WAIT; + pci_write_config8(dev, PCI_COMMAND, byte); +} + +static struct device_operations nic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = nic_init, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver northbridge_driver __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_8233_7, +}; diff --git a/src/southbridge/via/vt8231/usb.c b/src/southbridge/via/vt8231/usb.c new file mode 100644 index 0000000000..e12a8db85a --- /dev/null +++ b/src/southbridge/via/vt8231/usb.c @@ -0,0 +1,52 @@ + +static void usb_on(int enable) +{ + unsigned char regval; + + /* Base 8231 controller */ + device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); + /* USB controller 1 */ + device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0); + /* USB controller 2 */ + device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, dev2); + + /* enable USB1 */ + if(dev2) { + if (enable) { + pci_write_config8(dev2, 0x3c, 0x05); + pci_write_config8(dev2, 0x04, 0x07); + } else { + pci_write_config8(dev2, 0x3c, 0x00); + pci_write_config8(dev2, 0x04, 0x00); + } + } + + if(dev0) { + regval = pci_read_config8(dev0, 0x50); + if (enable) + regval &= ~(0x10); + else + regval |= 0x10; + pci_write_config8(dev0, 0x50, regval); + } + + /* enable USB2 */ + if(dev3) { + if (enable) { + pci_write_config8(dev3, 0x3c, 0x05); + pci_write_config8(dev3, 0x04, 0x07); + } else { + pci_write_config8(dev3, 0x3c, 0x00); + pci_write_config8(dev3, 0x04, 0x00); + } + } + + if(dev0) { + regval = pci_read_config8(dev0, 0x50); + if (enable) + regval &= ~(0x20); + else + regval |= 0x20; + pci_write_config8(dev0, 0x50, regval); + } +} diff --git a/src/southbridge/via/vt8231/vt8231_acpi.c b/src/southbridge/via/vt8231/vt8231_acpi.c deleted file mode 100644 index 647910aef6..0000000000 --- a/src/southbridge/via/vt8231/vt8231_acpi.c +++ /dev/null @@ -1,43 +0,0 @@ -#include -#include -#include -#include -#include - -static void acpi_init(struct device *dev) -{ - printk(BIOS_DEBUG, "Configuring VIA ACPI\n"); - - // Set ACPI base address to IO 0x4000 - pci_write_config32(dev, 0x48, 0x4001); - - // Enable ACPI access (and setup like award) - pci_write_config8(dev, 0x41, 0x84); - - // Set hardware monitor base address to IO 0x6000 - pci_write_config32(dev, 0x70, 0x6001); - - // Enable hardware monitor (and setup like award) - pci_write_config8(dev, 0x74, 0x01); - - // set IO base address to 0x5000 - pci_write_config32(dev, 0x90, 0x5001); - - // Enable SMBus - pci_write_config8(dev, 0xd2, 0x01); -} - -static struct device_operations acpi_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = acpi_init, - .enable = 0, - .ops_pci = 0, -}; - -static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &acpi_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_8231_4, -}; diff --git a/src/southbridge/via/vt8231/vt8231_early_serial.c b/src/southbridge/via/vt8231/vt8231_early_serial.c deleted file mode 100644 index af5a7729ee..0000000000 --- a/src/southbridge/via/vt8231/vt8231_early_serial.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Enable the serial evices on the VIA - */ - - -/* The base address is 0x15c, 0x2e, depending on config bytes */ - -#define SIO_BASE 0x3f0 -#define SIO_DATA SIO_BASE+1 - -static void vt8231_writesuper(uint8_t reg, uint8_t val) -{ - outb(reg, SIO_BASE); - outb(val, SIO_DATA); -} - -static void vt8231_writesiobyte(uint16_t reg, uint8_t val) -{ - outb(val, reg); -} - -static void vt8231_writesioword(uint16_t reg, uint16_t val) -{ - outw(val, reg); -} - - -/* regs we use: 85, and the southbridge devfn is defined by the - mainboard - */ - -static void enable_vt8231_serial(void) -{ - uint8_t c; - device_t dev; - outb(6, 0x80); - dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); - - if (dev == PCI_DEV_INVALID) { - outb(7, 0x80); - die("Serial controller not found\n"); - } - - /* first, you have to enable the superio and superio config. - put a 6 reg 80 - */ - c = pci_read_config8(dev, 0x50); - c |= 6; - pci_write_config8(dev, 0x50, c); - outb(2, 0x80); - // now go ahead and set up com1. - // set address - vt8231_writesuper(0xf4, 0xfe); - // enable serial out - vt8231_writesuper(0xf2, 7); - // That's it for the sio stuff. - // movl $SUPERIOCONFIG, %eax - // movb $9, %dl - // PCI_WRITE_CONFIG_BYTE - // set up reg to set baud rate. - vt8231_writesiobyte(0x3fb, 0x80); - // Set 115 kb - vt8231_writesioword(0x3f8, 1); - // Set 9.6 kb - // WRITESIOWORD(0x3f8, 12) - // now set no parity, one stop, 8 bits - vt8231_writesiobyte(0x3fb, 3); - // now turn on RTS, DRT - vt8231_writesiobyte(0x3fc, 3); - // Enable interrupts - vt8231_writesiobyte(0x3f9, 0xf); - // should be done. Dump a char for fun. - vt8231_writesiobyte(0x3f8, 48); -} diff --git a/src/southbridge/via/vt8231/vt8231_early_smbus.c b/src/southbridge/via/vt8231/vt8231_early_smbus.c deleted file mode 100644 index 7bf1267b75..0000000000 --- a/src/southbridge/via/vt8231/vt8231_early_smbus.c +++ /dev/null @@ -1,295 +0,0 @@ -#define SMBUS_IO_BASE 0x5000 - -#define SMBHSTSTAT 0x0 -#define SMBSLVSTAT 0x1 -#define SMBHSTCTL 0x2 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBBLKDAT 0x7 -#define SMBSLVCTL 0x8 -#define SMBTRNSADD 0x9 -#define SMBSLVDATA 0xa -#define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf - -/* Define register settings */ -#define HOST_RESET 0xff -#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ - - -#define SMBUS_TIMEOUT (100*1000*10) - -static void enable_smbus(void) -{ - device_t dev; - unsigned char c; - /* Power management controller */ - dev = pci_locate_device(PCI_ID(0x1106, 0x8235), 0); - - if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\n"); - } - // set IO base address to SMBUS_IO_BASE - pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1); - - // Enable SMBus - c = pci_read_config8(dev, 0xd2); - c |= 5; - pci_write_config8(dev, 0xd2, c); - - /* make it work for I/O ... - */ - dev = pci_locate_device(PCI_ID(0x1106, 0x8231), 0); - c = pci_read_config8(dev, 4); - c |= 1; - pci_write_config8(dev, 4, c); - print_debug_hex8(c); - print_debug(" is the comm register\n"); - - print_debug("SMBus controller enabled\n"); -} - - -static inline void smbus_delay(void) -{ - outb(0x80, 0x80); -} - -static int smbus_wait_until_active(void) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - val = inb(SMBUS_IO_BASE + SMBHSTSTAT); - if ((val & 1)) { - break; - } - } while (--loops); - return loops ? 0 : -4; -} - -static int smbus_wait_until_ready(void) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - val = inb(SMBUS_IO_BASE + SMBHSTSTAT); - if ((val & 1) == 0) { - break; - } - if (loops == (SMBUS_TIMEOUT / 2)) { - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - } - } while (--loops); - return loops ? 0 : -2; -} - -static int smbus_wait_until_done(void) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - - val = inb(SMBUS_IO_BASE + SMBHSTSTAT); - if ((val & 1) == 0) { - break; - } - } while (--loops); - return loops ? 0 : -3; -} - -#if 0 -void smbus_reset(void) -{ - outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); - outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); - outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); - outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); - - smbus_wait_until_ready(); - print_debug("After reset status "); - print_debug_hex8(inb(SMBUS_IO_BASE + SMBHSTSTAT)); - print_debug("\n"); -} -#endif - -#if CONFIG_DEBUG_SMBUS -static void smbus_print_error(unsigned char host_status_register) -{ - - print_err("smbus_error: "); - print_err_hex8(host_status_register); - print_err("\n"); - if (host_status_register & (1 << 4)) { - print_err("Interrup/SMI# was Failed Bus Transaction\n"); - } - if (host_status_register & (1 << 3)) { - print_err("Bus Error\n"); - } - if (host_status_register & (1 << 2)) { - print_err("Device Error\n"); - } - if (host_status_register & (1 << 1)) { - print_err("Interrupt/SMI# was Successful Completion\n"); - } - if (host_status_register & (1 << 0)) { - print_err("Host Busy\n"); - } -} -#endif - -/* - * Copied from intel/i82801dbm early smbus code - suggested by rgm. - * Modifications/check against i2c-viapro driver code from linux-2.4.22 - * and VT8231 Reference Docs - mw. - */ -static int smbus_read_byte(unsigned device, unsigned address) -{ - unsigned char global_status_register; - unsigned char byte; - - if (smbus_wait_until_ready() < 0) { - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - if (smbus_wait_until_ready() < 0) { - return -2; - } - } - - /* setup transaction */ - /* disable interrupts */ - outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xfe, SMBUS_IO_BASE + SMBHSTCTL); - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); - /* set the command/address... */ - outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); - /* set up for a byte data read */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xe3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL); - - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - - /* clear the data byte... */ - outb(0, SMBUS_IO_BASE + SMBHSTDAT0); - - /* start a byte read, with interrupts disabled */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); - /* poll for it to start */ - if (smbus_wait_until_active() < 0) { - return -4; - } - - /* poll for transaction completion */ - if (smbus_wait_until_done() < 0) { - return -3; - } - - /* Ignore the Host Busy & Command Complete ? */ - global_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT) & ~((1 << 1) | (1 << 0)); - - /* read results of transaction */ - byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); - - if (global_status_register != 0) { - return -1; - } - return byte; -} - -#if 0 -/* SMBus routines borrowed from VIA's Trident Driver */ -/* this works, so I am not going to touch it for now -- rgm */ -static unsigned char smbus_read_byte(unsigned char devAdr, unsigned char bIndex) -{ - unsigned int i; - unsigned char bData; - unsigned char sts = 0; - - /* clear host status */ - outb(0xff, SMBUS_IO_BASE); - - /* check SMBUS ready */ - for (i = 0; i < SMBUS_TIMEOUT; i++) - if ((inb(SMBUS_IO_BASE) & 0x01) == 0) - break; - - /* set host command */ - outb(bIndex, SMBUS_IO_BASE + 3); - - /* set slave address */ - outb(devAdr | 0x01, SMBUS_IO_BASE + 4); - - /* start */ - outb(0x48, SMBUS_IO_BASE + 2); - - /* SMBUS Wait Ready */ - for (i = 0; i < SMBUS_TIMEOUT; i++) - if (((sts = inb(SMBUS_IO_BASE)) & 0x01) == 0) - break; - if ((sts & ~3) != 0) { - smbus_print_error(sts); - return 0; - } - bData = inb(SMBUS_IO_BASE + 5); - - return bData; - -} -#endif -/* for reference, here is the fancier version which we will use at some - * point - */ -# if 0 -int smbus_read_byte(unsigned device, unsigned address, unsigned char *result) -{ - unsigned char host_status_register; - unsigned char byte; - - reset(); - - smbus_wait_until_ready(); - - /* setup transaction */ - /* disable interrupts */ - outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); - /* set the command/address... */ - outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); - /* set up for a byte data read */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL); - - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - - /* clear the data byte... */ - outb(0, SMBUS_IO_BASE + SMBHSTDAT0); - - /* start the command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL); - - /* poll for transaction completion */ - smbus_wait_until_done(); - - host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); - - /* Ignore the In Use Status... */ - host_status_register &= ~(1 << 6); - - /* read results of transaction */ - byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); - smbus_print_error(byte); - - *result = byte; - return host_status_register != 0x02; -} - - -#endif diff --git a/src/southbridge/via/vt8231/vt8231_enable_rom.c b/src/southbridge/via/vt8231/vt8231_enable_rom.c deleted file mode 100644 index bb43420610..0000000000 --- a/src/southbridge/via/vt8231/vt8231_enable_rom.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include - -static void vt8231_enable_rom(void) -{ - device_t dev; - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_8231), 0); - - /* - * ROM decode control register (0x43): - * - * Bit Decode range - * ----------------- - * 7 0xFFFE0000-0xFFFEFFFF - * 6 0xFFF80000-0xFFFDFFFF - * 5 0xFFF00000-0xFFF7FFFF - * 4 0x000E0000-0x000EFFFF - * 3 0x000D8000-0x000DFFFF - * 2 0x000D0000-0x000D7FFF - * 1 0x000C8000-0x000CFFFF - * 0 0x000C0000-0x000C7FFF - */ - pci_write_config8(dev, 0x43, (1 << 7) | (1 << 6) | (1 << 5)); -} diff --git a/src/southbridge/via/vt8231/vt8231_ide.c b/src/southbridge/via/vt8231/vt8231_ide.c deleted file mode 100644 index 46479c4af3..0000000000 --- a/src/southbridge/via/vt8231/vt8231_ide.c +++ /dev/null @@ -1,113 +0,0 @@ -#include -#include -#include -#include -#include -#include "chip.h" - -static void ide_init(struct device *dev) -{ - struct southbridge_via_vt8231_config *conf = (struct southbridge_via_vt8231_config *)dev->chip_info; - unsigned char enables; - - if (!conf->enable_native_ide) { - // Run the IDE controller in 'compatiblity mode - i.e. don't use PCI - // interrupts. Using PCI ints confuses linux for some reason. - /* Setting reg 0x42 here does not work. It is set in mainboard/romstage.c - * It probably can only be changed while the IDE is disabled - * or it is possibly a timing issue. Ben Hewson 29 Apr 2007. - */ - - /* - printk(BIOS_INFO, "%s: enabling compatibility IDE addresses\n", __func__); - enables = pci_read_config8(dev, 0x42); - printk(BIOS_DEBUG, "enables in reg 0x42 0x%x\n", enables); - enables &= ~0xc0; // compatability mode - pci_write_config8(dev, 0x42, enables); - enables = pci_read_config8(dev, 0x42); - printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n", enables); - */ - } - - enables = pci_read_config8(dev, 0x40); - printk(BIOS_DEBUG, "enables in reg 0x40 0x%x\n", enables); - enables |= 3; - pci_write_config8(dev, 0x40, enables); - enables = pci_read_config8(dev, 0x40); - printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables); - - // Enable prefetch buffers - enables = pci_read_config8(dev, 0x41); - enables |= 0xf0; - pci_write_config8(dev, 0x41, enables); - - // Lower thresholds (cause award does it) - enables = pci_read_config8(dev, 0x43); - enables &= ~0x0f; - enables |= 0x05; - pci_write_config8(dev, 0x43, enables); - - // PIO read prefetch counter (cause award does it) - pci_write_config8(dev, 0x44, 0x18); - - // Use memory read multiple - pci_write_config8(dev, 0x45, 0x1c); - - // address decoding. - // we want "flexible", i.e. 1f0-1f7 etc. or native PCI - // kevinh@ispiri.com - the standard linux drivers seem ass slow when - // used in native mode - I've changed back to classic - enables = pci_read_config8(dev, 0x9); - printk(BIOS_DEBUG, "enables in reg 0x9 0x%x\n", enables); - // by the book, set the low-order nibble to 0xa. - if (conf->enable_native_ide) { - enables &= ~0xf; - // cf/cg silicon needs an 'f' here. - enables |= 0xf; - } else { - enables &= ~0x5; - } - - pci_write_config8(dev, 0x9, enables); - enables = pci_read_config8(dev, 0x9); - printk(BIOS_DEBUG, "enables in reg 0x9 read back as 0x%x\n", enables); - - // standard bios sets master bit. - enables = pci_read_config8(dev, 0x4); - printk(BIOS_DEBUG, "command in reg 0x4 0x%x\n", enables); - enables |= 7; - - // No need for stepping - kevinh@ispiri.com - enables &= ~0x80; - - pci_write_config8(dev, 0x4, enables); - enables = pci_read_config8(dev, 0x4); - printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables); - - if (!conf->enable_native_ide) { - // Use compatability mode - per award bios - pci_write_config32(dev, 0x10, 0x0); - pci_write_config32(dev, 0x14, 0x0); - pci_write_config32(dev, 0x18, 0x0); - pci_write_config32(dev, 0x1c, 0x0); - - // Force interrupts to use compat mode - just like Award bios - pci_write_config8(dev, 0x3d, 00); - pci_write_config8(dev, 0x3c, 0xff); - } -} - -static struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .enable = 0, - .ops_pci = 0, -}; - -static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_82C586_1, -}; diff --git a/src/southbridge/via/vt8231/vt8231_lpc.c b/src/southbridge/via/vt8231/vt8231_lpc.c deleted file mode 100644 index 40854dbcf7..0000000000 --- a/src/southbridge/via/vt8231/vt8231_lpc.c +++ /dev/null @@ -1,165 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include "chip.h" - -/* PIRQ init - */ -static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 }; -static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 }; -static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 }; - -/* - Our IDSEL mappings are as follows - PCI slot is AD31 (device 15) (00:14.0) - Southbridge is AD28 (device 12) (00:11.0) -*/ -static void pci_routing_fixup(struct device *dev) -{ - - printk(BIOS_INFO, "%s: dev is %p\n", __func__, dev); - if (dev) { - /* initialize PCI interupts - these assignments depend - on the PCB routing of PINTA-D - - PINTA = IRQ11 - PINTB = IRQ5 - PINTC = IRQ10 - PINTD = IRQ12 - */ - pci_write_config8(dev, 0x55, 0xb0); - pci_write_config8(dev, 0x56, 0xa5); - pci_write_config8(dev, 0x57, 0xc0); - } - - // Standard southbridge components - printk(BIOS_INFO, "setting southbridge\n"); - pci_assign_irqs(0, 0x11, southbridgeIrqs); - - // Ethernet built into southbridge - printk(BIOS_INFO, "setting ethernet\n"); - pci_assign_irqs(0, 0x12, enetIrqs); - - // PCI slot - printk(BIOS_INFO, "setting pci slot\n"); - pci_assign_irqs(0, 0x14, slotIrqs); - printk(BIOS_INFO, "%s: DONE\n", __func__); -} - -static void vt8231_init(struct device *dev) -{ - unsigned char enables; - - printk(BIOS_DEBUG, "vt8231 init\n"); - - // enable the internal I/O decode - enables = pci_read_config8(dev, 0x6C); - enables |= 0x80; - pci_write_config8(dev, 0x6C, enables); - - // Set bit 6 of 0x40, because Award does it (IO recovery time) - // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI - // interrupts can be properly marked as level triggered. - enables = pci_read_config8(dev, 0x40); - pci_write_config8(dev, 0x40, enables); - - // Set 0x42 to 0xf0 to match Award bios - enables = pci_read_config8(dev, 0x42); - enables |= 0xf0; - pci_write_config8(dev, 0x42, enables); - - // Set bit 3 of 0x4a, to match award (dummy pci request) - enables = pci_read_config8(dev, 0x4a); - enables |= 0x08; - pci_write_config8(dev, 0x4a, enables); - - // Set bit 3 of 0x4f to match award (use INIT# as cpu reset) - enables = pci_read_config8(dev, 0x4f); - enables |= 0x08; - pci_write_config8(dev, 0x4f, enables); - - // Set 0x58 to 0x03 to match Award - pci_write_config8(dev, 0x58, 0x03); - - // enable the ethernet/RTC - if (dev) { - enables = pci_read_config8(dev, 0x51); - enables |= 0x18; - pci_write_config8(dev, 0x51, enables); - } - - // enable IDE, since Linux won't do it. - // First do some more things to devfn (17,0) - // note: this should already be cleared, according to the book. - enables = pci_read_config8(dev, 0x50); - printk(BIOS_DEBUG, "IDE enable in reg. 50 is 0x%x\n", enables); - enables &= ~8; // need manifest constant here! - printk(BIOS_DEBUG, "set IDE reg. 50 to 0x%x\n", enables); - pci_write_config8(dev, 0x50, enables); - - // set default interrupt values (IDE) - enables = pci_read_config8(dev, 0x4c); - printk(BIOS_DEBUG, "IRQs in reg. 4c are 0x%x\n", enables & 0xf); - // clear out whatever was there. - enables &= ~0xf; - enables |= 4; - printk(BIOS_DEBUG, "setting reg. 4c to 0x%x\n", enables); - pci_write_config8(dev, 0x4c, enables); - - // set up the serial port interrupts. - // com2 to 3, com1 to 4 - pci_write_config8(dev, 0x46, 0x04); - pci_write_config8(dev, 0x47, 0x03); - pci_write_config8(dev, 0x6e, 0x98); - - /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */ - pci_write_config8(dev, 0x40, 0x54); - //ethernet_fixup(); - - // Start the rtc - rtc_init(0); -} - -static void vt8231_read_resources(device_t dev) -{ - struct resource *res; - - pci_dev_read_resources(dev); - - res = new_resource(dev, 1); - res->base = 0x0UL; - res->size = 0x1000UL; - res->limit = 0xffffUL; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -static void southbridge_init(struct device *dev) -{ - vt8231_init(dev); - pci_routing_fixup(dev); -} - -static struct device_operations vt8231_lpc_ops = { - .read_resources = vt8231_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = &southbridge_init, - .scan_bus = scan_static_bus, - .enable = 0, - .ops_pci = 0, -}; - -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &vt8231_lpc_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_8231, -}; diff --git a/src/southbridge/via/vt8231/vt8231_nic.c b/src/southbridge/via/vt8231/vt8231_nic.c deleted file mode 100644 index 5cd6cd8ca1..0000000000 --- a/src/southbridge/via/vt8231/vt8231_nic.c +++ /dev/null @@ -1,36 +0,0 @@ -#include -#include -#include -#include -#include - -/* - * Enable the ethernet device and turn off stepping (because it is integrated - * inside the southbridge) - */ -static void nic_init(struct device *dev) -{ - uint8_t byte; - - printk(BIOS_DEBUG, "Configuring VIA LAN\n"); - - /* We don't need stepping - though the device supports it */ - byte = pci_read_config8(dev, PCI_COMMAND); - byte &= ~PCI_COMMAND_WAIT; - pci_write_config8(dev, PCI_COMMAND, byte); -} - -static struct device_operations nic_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = nic_init, - .enable = 0, - .ops_pci = 0, -}; - -static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_8233_7, -}; diff --git a/src/southbridge/via/vt8231/vt8231_usb.c b/src/southbridge/via/vt8231/vt8231_usb.c deleted file mode 100644 index e12a8db85a..0000000000 --- a/src/southbridge/via/vt8231/vt8231_usb.c +++ /dev/null @@ -1,52 +0,0 @@ - -static void usb_on(int enable) -{ - unsigned char regval; - - /* Base 8231 controller */ - device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); - /* USB controller 1 */ - device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0); - /* USB controller 2 */ - device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, dev2); - - /* enable USB1 */ - if(dev2) { - if (enable) { - pci_write_config8(dev2, 0x3c, 0x05); - pci_write_config8(dev2, 0x04, 0x07); - } else { - pci_write_config8(dev2, 0x3c, 0x00); - pci_write_config8(dev2, 0x04, 0x00); - } - } - - if(dev0) { - regval = pci_read_config8(dev0, 0x50); - if (enable) - regval &= ~(0x10); - else - regval |= 0x10; - pci_write_config8(dev0, 0x50, regval); - } - - /* enable USB2 */ - if(dev3) { - if (enable) { - pci_write_config8(dev3, 0x3c, 0x05); - pci_write_config8(dev3, 0x04, 0x07); - } else { - pci_write_config8(dev3, 0x3c, 0x00); - pci_write_config8(dev3, 0x04, 0x00); - } - } - - if(dev0) { - regval = pci_read_config8(dev0, 0x50); - if (enable) - regval &= ~(0x20); - else - regval |= 0x20; - pci_write_config8(dev0, 0x50, regval); - } -} diff --git a/src/southbridge/via/vt8235/Makefile.inc b/src/southbridge/via/vt8235/Makefile.inc index 06d533560b..02e22640bf 100644 --- a/src/southbridge/via/vt8235/Makefile.inc +++ b/src/southbridge/via/vt8235/Makefile.inc @@ -18,7 +18,7 @@ ## driver-y += vt8235.c -driver-y += vt8235_ide.c -driver-y += vt8235_lpc.c -driver-y += vt8235_nic.c -driver-y += vt8235_usb.c +driver-y += ide.c +driver-y += lpc.c +driver-y += nic.c +driver-y += usb.c diff --git a/src/southbridge/via/vt8235/early_serial.c b/src/southbridge/via/vt8235/early_serial.c new file mode 100644 index 0000000000..11f98fae39 --- /dev/null +++ b/src/southbridge/via/vt8235/early_serial.c @@ -0,0 +1,77 @@ +/* + * Enable the serial evices on the VIA + */ + + +/* The base address is 0x15c, 0x2e, depending on config bytes */ + +#define SIO_BASE 0x3f0 +#define SIO_DATA SIO_BASE+1 + +static void vt8235_writepnpaddr(uint8_t val) +{ + outb(val, 0x2e); + outb(val, 0xeb); +} + +static void vt8235_writepnpdata(uint8_t val) +{ + outb(val, 0x2f); + outb(val, 0xeb); +} + + +static void vt8235_writesiobyte(uint16_t reg, uint8_t val) +{ + outb(val, reg); +} + +static void vt8235_writesioword(uint16_t reg, uint16_t val) +{ + outw(val, reg); +} + + +/* regs we use: 85, and the southbridge devfn is defined by the + mainboard + */ + +static void enable_vt8235_serial(void) +{ + // turn on pnp + vt8235_writepnpaddr(0x87); + vt8235_writepnpaddr(0x87); + // now go ahead and set up com1. + // set address + vt8235_writepnpaddr(0x7); + vt8235_writepnpdata(0x2); + // enable serial out + vt8235_writepnpaddr(0x30); + vt8235_writepnpdata(0x1); + // serial port 1 base address (FEh) + vt8235_writepnpaddr(0x60); + vt8235_writepnpdata(0xfe); + // serial port 1 IRQ (04h) + vt8235_writepnpaddr(0x70); + vt8235_writepnpdata(0x4); + // serial port 1 control + vt8235_writepnpaddr(0xf0); + vt8235_writepnpdata(0x2); + // turn of pnp + vt8235_writepnpaddr(0xaa); + + // set up reg to set baud rate. + vt8235_writesiobyte(0x3fb, 0x80); + // Set 115 kb + vt8235_writesioword(0x3f8, 1); + // Set 9.6 kb + // WRITESIOWORD(0x3f8, 12) + // now set no parity, one stop, 8 bits + vt8235_writesiobyte(0x3fb, 3); + // now turn on RTS, DRT + vt8235_writesiobyte(0x3fc, 3); + // Enable interrupts + vt8235_writesiobyte(0x3f9, 0xf); + // should be done. Dump a char for fun. + vt8235_writesiobyte(0x3f8, 48); +} diff --git a/src/southbridge/via/vt8235/early_smbus.c b/src/southbridge/via/vt8235/early_smbus.c new file mode 100644 index 0000000000..d091099fdb --- /dev/null +++ b/src/southbridge/via/vt8235/early_smbus.c @@ -0,0 +1,249 @@ +#define SMBUS_IO_BASE 0xf00 + +#define SMBHSTSTAT 0x0 +#define SMBSLVSTAT 0x1 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBBLKDAT 0x7 +#define SMBSLVCTL 0x8 +#define SMBTRNSADD 0x9 +#define SMBSLVDATA 0xa +#define SMLINK_PIN_CTL 0xe +#define SMBUS_PIN_CTL 0xf + +/* Define register settings */ +#define HOST_RESET 0xff +#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ + + +#define SMBUS_TIMEOUT (100*1000*10) + +#define I2C_TRANS_CMD 0x40 +#define CLOCK_SLAVE_ADDRESS 0x69 + +static void enable_smbus(void) +{ + device_t dev; + unsigned char c; + int i; + + /* Power management controller */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_8235), 0); + + if (dev == PCI_DEV_INVALID) { + die("SMBUS controller not found\n"); + } + + // set IO base address to SMBUS_IO_BASE + pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1); + + // Enable SMBus + pci_write_config8(dev, 0xd2, (0x4 << 1) | 1); + + /* make it work for I/O ... + */ + pci_write_config16(dev, 4, 1); + + /* FIX for half baud rate problem */ + /* let clocks and the like settle */ + /* as yet arbitrary count - 1000 is too little 5000 works */ + for(i = 0 ; i < 5000 ; i++) + outb(0x80,0x80); + + /* + * The VT1211 serial port needs 48 mhz clock, on power up it is getting + * only 24 mhz, there is some mysterious device on the smbus that can + * fix this...this code below does it. + * */ + outb(0xff, SMBUS_IO_BASE+SMBHSTSTAT); + outb(0x7f, SMBUS_IO_BASE+SMBHSTDAT0); + outb(0x83, SMBUS_IO_BASE+SMBHSTCMD); + outb(CLOCK_SLAVE_ADDRESS<<1 , SMBUS_IO_BASE+SMBXMITADD); + outb(8 | I2C_TRANS_CMD, SMBUS_IO_BASE+SMBHSTCTL); + + for (;;) { + c = inb(SMBUS_IO_BASE+SMBHSTSTAT); + if ((c & 1) == 0) + break; + } +} + + +static inline void smbus_delay(void) +{ + outb(0x80, 0x80); +} + +static int smbus_wait_until_ready(void) +{ + unsigned char c; + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + smbus_delay(); + c = inb(SMBUS_IO_BASE + SMBHSTSTAT); + while((c & 1) == 1) { + print_debug("c is "); + print_debug_hex8(c); + print_debug("\n"); + c = inb(SMBUS_IO_BASE + SMBHSTSTAT); + /* nop */ + } + + } while(--loops); + return loops?0:-1; +} + +void smbus_reset(void) +{ + outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); + outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); + outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); + outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); + + smbus_wait_until_ready(); + print_debug("After reset status "); + print_debug_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT)); + print_debug("\n"); +} + + + +static int smbus_wait_until_done(void) +{ + unsigned long loops; + unsigned char byte; + loops = SMBUS_TIMEOUT; + do { + smbus_delay(); + + byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); + if (byte & 1) + break; + + } while(--loops); + return loops?0:-1; +} + +static void smbus_print_error(unsigned char host_status_register) +{ + + print_err("smbus_error: "); + print_err_hex8(host_status_register); + print_err("\n"); + if (host_status_register & (1 << 4)) { + print_err("Interrup/SMI# was Failed Bus Transaction\n"); + } + if (host_status_register & (1 << 3)) { + print_err("Bus Error\n"); + } + if (host_status_register & (1 << 2)) { + print_err("Device Error\n"); + } + if (host_status_register & (1 << 1)) { + print_err("Interrupt/SMI# was Successful Completion\n"); + } + if (host_status_register & (1 << 0)) { + print_err("Host Busy\n"); + } +} + + +/* SMBus routines borrowed from VIA's Trident Driver */ +/* this works, so I am not going to touch it for now -- rgm */ +static unsigned char smbus_read_byte(unsigned char devAdr, + unsigned char bIndex) +{ + unsigned short i; + unsigned char bData; + unsigned char sts = 0; + + /* clear host status */ + outb(0xff, SMBUS_IO_BASE); + + /* check SMBUS ready */ + for ( i = 0; i < 0xFFFF; i++ ) + if ( (inb(SMBUS_IO_BASE) & 0x01) == 0 ) + break; + + /* set host command */ + outb(bIndex, SMBUS_IO_BASE+3); + + /* set slave address */ + outb((devAdr << 1) | 0x01, SMBUS_IO_BASE+4); + + /* start */ + outb(0x48, SMBUS_IO_BASE+2); + + /* SMBUS Wait Ready */ + for ( i = 0; i < 0xFFFF; i++ ) + if ( ((sts = (inb(SMBUS_IO_BASE) & 0x1f)) & 0x01) == 0 ) + break; + + if ((sts & ~3) != 0) { + smbus_print_error(sts); + return 0; + } + bData=inb(SMBUS_IO_BASE+5); + + return bData; + +} + +/* for reference, here is the fancier version which we will use at some + * point + */ +# if 0 +int smbus_read_byte(unsigned device, unsigned address, unsigned char *result) +{ + unsigned char host_status_register; + unsigned char byte; + + reset(); + + smbus_wait_until_ready(); + + /* setup transaction */ + /* disable interrupts */ + outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); + /* set the command/address... */ + outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); + /* set up for a byte data read */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), + SMBUS_IO_BASE + SMBHSTCTL); + + /* clear any lingering errors, so the transaction will run */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + + /* clear the data byte...*/ + outb(0, SMBUS_IO_BASE + SMBHSTDAT0); + + /* start the command */ + outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), + SMBUS_IO_BASE + SMBHSTCTL); + + /* poll for transaction completion */ + smbus_wait_until_done(); + + host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); + + /* Ignore the In Use Status... */ + host_status_register &= ~(1 << 6); + + /* read results of transaction */ + byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); + smbus_print_error(byte); + + *result = byte; + return host_status_register != 0x02; +} + + +#endif + diff --git a/src/southbridge/via/vt8235/ide.c b/src/southbridge/via/vt8235/ide.c new file mode 100644 index 0000000000..961f860fed --- /dev/null +++ b/src/southbridge/via/vt8235/ide.c @@ -0,0 +1,113 @@ +#include +#include +#include +#include +#include +#include "chip.h" + +static void ide_init(struct device *dev) +{ + struct southbridge_via_vt8235_config *conf = dev->chip_info; + unsigned char enables; + + printk(BIOS_INFO, "Enabling VIA IDE.\n"); + + /*if (!conf->enable_native_ide) { */ + /* + * Run the IDE controller in 'compatiblity mode - i.e. don't + * use PCI interrupts. Using PCI ints confuses linux for some + * reason. + */ + printk(BIOS_INFO, "%s: enabling compatibility IDE addresses\n", + __func__); + enables = pci_read_config8(dev, 0x42); + printk(BIOS_DEBUG, "enables in reg 0x42 0x%x\n", enables); + enables &= ~0xc0; // compatability mode + pci_write_config8(dev, 0x42, enables); + enables = pci_read_config8(dev, 0x42); + printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n", + enables); + /* } */ + + enables = pci_read_config8(dev, 0x40); + printk(BIOS_DEBUG, "enables in reg 0x40 0x%x\n", enables); + enables |= 3; + pci_write_config8(dev, 0x40, enables); + enables = pci_read_config8(dev, 0x40); + printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables); + + // Enable prefetch buffers + enables = pci_read_config8(dev, 0x41); + enables |= 0xf0; + pci_write_config8(dev, 0x41, enables); + + // Lower thresholds (cause award does it) + enables = pci_read_config8(dev, 0x43); + enables &= ~0x0f; + enables |= 0x05; + pci_write_config8(dev, 0x43, enables); + + // PIO read prefetch counter (cause award does it) + pci_write_config8(dev, 0x44, 0x18); + + // Use memory read multiple + pci_write_config8(dev, 0x45, 0x1c); + + // address decoding. + // we want "flexible", i.e. 1f0-1f7 etc. or native PCI + // kevinh@ispiri.com - the standard linux drivers seem ass slow when + // used in native mode - I've changed back to classic + enables = pci_read_config8(dev, 0x9); + printk(BIOS_DEBUG, "enables in reg 0x9 0x%x\n", enables); + // by the book, set the low-order nibble to 0xa. + if (conf->enable_native_ide) { + enables &= ~0xf; + // cf/cg silicon needs an 'f' here. + enables |= 0xf; + } else { + enables &= ~0x5; + } + + pci_write_config8(dev, 0x9, enables); + enables = pci_read_config8(dev, 0x9); + printk(BIOS_DEBUG, "enables in reg 0x9 read back as 0x%x\n", enables); + + // standard bios sets master bit. + enables = pci_read_config8(dev, 0x4); + printk(BIOS_DEBUG, "command in reg 0x4 0x%x\n", enables); + enables |= 7; + + // No need for stepping - kevinh@ispiri.com + enables &= ~0x80; + + pci_write_config8(dev, 0x4, enables); + enables = pci_read_config8(dev, 0x4); + printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables); + + if (!conf->enable_native_ide) { + // Use compatability mode - per award bios + pci_write_config32(dev, 0x10, 0x0); + pci_write_config32(dev, 0x14, 0x0); + pci_write_config32(dev, 0x18, 0x0); + pci_write_config32(dev, 0x1c, 0x0); + + // Force interrupts to use compat mode - just like Award bios + pci_write_config8(dev, 0x3d, 0x0); + pci_write_config8(dev, 0x3c, 0xff); + } +} + +static struct device_operations ide_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver northbridge_driver __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_82C586_1, +}; diff --git a/src/southbridge/via/vt8235/lpc.c b/src/southbridge/via/vt8235/lpc.c new file mode 100644 index 0000000000..b355ad0d88 --- /dev/null +++ b/src/southbridge/via/vt8235/lpc.c @@ -0,0 +1,261 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +/* The epia-m is really short on interrupts available, so PCI interupts A & D are ganged togther and so are B & C. + This is how the Award bios sets it up too. + epia can be more generous as it does not need to reserve interrupts for cardbus devices, but if changed then + make sure that ACPI dsdt is changed to suit. + + IRQ 0 = timer + IRQ 1 = keyboard + IRQ 2 = cascade + IRQ 3 = COM 2 + IRQ 4 = COM 1 + IRQ 5 = available for PCI interrupts + IRQ 6 = floppy or availbale for PCI if floppy controller disabled + IRQ 7 = LPT or available if LPT port disabled + IRQ 8 = rtc + IRQ 9 = available for PCI interrupts + IRQ 10 = cardbus slot or available for PCI if no cardbus (ie epia) + IRQ 11 = cardbus slot or available for PCI if no cardbus (ie epia) + IRQ 12 = PS2 mouse (hardwired to 12) + IRQ 13 = legacy FPU interrupt + IRQ 14 = IDE controller 1 + IRQ 15 = IDE controller 2 + +*/ +static const unsigned char pciIrqs[4] = { 5 , 9 , 9, 5 }; + +static const unsigned char usbPins[4] = { 'A','B','C','D'}; +static const unsigned char enetPins[4] = { 'A','B','C','D'}; +static const unsigned char slotPins[4] = { 'B','C','D','A'}; +static const unsigned char firewirePins[4] = { 'B','C','D','A'}; +static const unsigned char vt8235Pins[4] = { 'A','B','C','D'}; +static const unsigned char vgaPins[4] = { 'A','B','C','D'}; +static const unsigned char cbPins[4] = { 'A','B','C','D'}; +static const unsigned char riserPins[4] = { 'A','B','C','D'}; + + +static unsigned char *pin_to_irq(const unsigned char *pin) +{ + static unsigned char Irqs[4]; + int i; + for (i = 0 ; i < 4 ; i++) + Irqs[i] = pciIrqs[ pin[i] - 'A' ]; + + return Irqs; +} + +static void pci_routing_fixup(struct device *dev) +{ + printk(BIOS_INFO, "%s: dev is %p\n", __func__, dev); + + /* set up PCI IRQ routing */ + pci_write_config8(dev, 0x55, pciIrqs[0] << 4); + pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4) ); + pci_write_config8(dev, 0x57, pciIrqs[3] << 4); + + + // firewire built into southbridge + printk(BIOS_INFO, "setting firewire\n"); + pci_assign_irqs(0, 0x0d, pin_to_irq(firewirePins)); + + // Standard usb components + printk(BIOS_INFO, "setting usb\n"); + pci_assign_irqs(0, 0x10, pin_to_irq(usbPins)); + + // VT8235 + sound hardware + printk(BIOS_INFO, "setting vt8235\n"); + pci_assign_irqs(0, 0x11, pin_to_irq(vt8235Pins)); + + // Ethernet built into southbridge + printk(BIOS_INFO, "setting ethernet\n"); + pci_assign_irqs(0, 0x12, pin_to_irq(enetPins)); + + // VGA + printk(BIOS_INFO, "setting vga\n"); + pci_assign_irqs(1, 0x00, pin_to_irq(vgaPins)); + + // PCI slot + printk(BIOS_INFO, "setting pci slot\n"); + pci_assign_irqs(0, 0x14, pin_to_irq(slotPins)); + + // Cardbus slot + printk(BIOS_INFO, "setting cardbus slot\n"); + pci_assign_irqs(0, 0x0a, pin_to_irq(cbPins)); + + // Via 2 slot riser card 2nd slot + printk(BIOS_INFO, "setting riser slot\n"); + pci_assign_irqs(0, 0x13, pin_to_irq(riserPins)); + + printk(BIOS_SPEW, "%s: DONE\n", __func__); +} + +/* + * Set up the power management capabilities directly into ACPI mode. This + * avoids having to handle any System Management Interrupts (SMI's) which I + * can't figure out how to do !!!! + */ + +static void setup_pm(device_t dev) +{ + // Set gen config 0 + pci_write_config8(dev, 0x80, 0x20); + + // Set ACPI base address to IO 0x400 + pci_write_config16(dev, 0x88, 0x0401); + + // set ACPI irq to 5 + pci_write_config8(dev, 0x82, 0x45); + + // primary interupt channel + pci_write_config16(dev, 0x84, 0x30f2); + + // throttle / stop clock control + pci_write_config8(dev, 0x8d, 0x18); + + pci_write_config8(dev, 0x93, 0x88); + pci_write_config8(dev, 0x94, 0xb0); + pci_write_config8(dev, 0x95, 0xc0); + pci_write_config8(dev, 0x98, 0); + pci_write_config8(dev, 0x99, 0xea); + pci_write_config8(dev, 0xe4, 0x14); + pci_write_config8(dev, 0xe5, 0x08); + + + // Enable ACPI access (and setup like award) + pci_write_config8(dev, 0x81, 0x84); + + outw(0xffff, 0x400); + outw(0xffff, 0x420); + outw(0xffff, 0x428); + outl(0xffffffff, 0x430); + + outw(0x0, 0x424); + outw(0x0, 0x42a); + outw(0x1, 0x42c); + outl(0x0, 0x434); + outl(0x01, 0x438); + outb(0x0, 0x442); + outl(0xffff7fff, 0x448); + outw(0x001, 0x404); +} + +static void vt8235_init(struct device *dev) +{ + unsigned char enables; + + printk(BIOS_DEBUG, "vt8235 init\n"); + + // enable the internal I/O decode + enables = pci_read_config8(dev, 0x6C); + enables |= 0x80; + pci_write_config8(dev, 0x6C, enables); + + // Map 4MB of FLASH into the address space + pci_write_config8(dev, 0x41, 0x7f); + + // Set bit 6 of 0x40, because Award does it (IO recovery time) + // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI + // interrupts can be properly marked as level triggered. + enables = pci_read_config8(dev, 0x40); + enables |= 0x45; + pci_write_config8(dev, 0x40, enables); + + // Set 0x42 to 0xf0 to match Award bios + enables = pci_read_config8(dev, 0x42); + enables |= 0xf0; + pci_write_config8(dev, 0x42, enables); + + /* Set 0x58 to 0x03 to match Award */ + pci_write_config8(dev, 0x58, 0x03); + + /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */ + enables = pci_read_config8(dev, 0x4f); + enables |= 0x08; + pci_write_config8(dev, 0x4f, enables); + + // Set bit 3 of 0x4a, to match award (dummy pci request) + enables = pci_read_config8(dev, 0x4a); + enables |= 0x08; + pci_write_config8(dev, 0x4a, enables); + + // Set bit 3 of 0x4f to match award (use INIT# as cpu reset) + enables = pci_read_config8(dev, 0x4f); + enables |= 0x08; + pci_write_config8(dev, 0x4f, enables); + + // Set 0x58 to 0x03 to match Award + pci_write_config8(dev, 0x58, 0x03); + + + /* enable serial irq */ + pci_write_config8(dev, 0x52, 0x9); + + /* dma */ + pci_write_config8(dev, 0x53, 0x00); + + // Power management setup + setup_pm(dev); + + /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */ + pci_write_config8(dev, 0x40, 0x54); + + // Start the rtc + rtc_init(0); +} + +/* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this + device has a resource to set - so set a dummy one */ +static void vt8235_read_resources(device_t dev) +{ + struct resource *res; + + pci_dev_read_resources(dev); + + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x1000UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = IO_APIC_ADDR; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void vt8235_set_resources(device_t dev) +{ + //struct resource *resource; + //resource = find_resource(dev,1); + //resource->flags |= IORESOURCE_STORED; + pci_dev_set_resources(dev); +} + +static void southbridge_init(struct device *dev) +{ + vt8235_init(dev); + pci_routing_fixup(dev); +} + +static struct device_operations vt8235_lpc_ops = { + .read_resources = vt8235_read_resources, + .set_resources = vt8235_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = southbridge_init, + .scan_bus = scan_static_bus, +}; + +static const struct pci_driver lpc_driver __pci_driver = { + .ops = &vt8235_lpc_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_8235, +}; diff --git a/src/southbridge/via/vt8235/nic.c b/src/southbridge/via/vt8235/nic.c new file mode 100644 index 0000000000..71f169c055 --- /dev/null +++ b/src/southbridge/via/vt8235/nic.c @@ -0,0 +1,36 @@ +#include +#include +#include +#include +#include + +/* + * Enable the ethernet device and turn off stepping (because it is integrated + * inside the southbridge) + */ +static void nic_init(struct device *dev) +{ + uint8_t byte; + + printk(BIOS_DEBUG, "Configuring VIA Rhine LAN\n"); + + /* We don't need stepping - though the device supports it */ + byte = pci_read_config8(dev, PCI_COMMAND); + byte &= ~PCI_COMMAND_WAIT; + pci_write_config8(dev, PCI_COMMAND, byte); +} + +static struct device_operations nic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = nic_init, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver northbridge_driver __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_8233_7, +}; diff --git a/src/southbridge/via/vt8235/usb.c b/src/southbridge/via/vt8235/usb.c new file mode 100644 index 0000000000..c712136c72 --- /dev/null +++ b/src/southbridge/via/vt8235/usb.c @@ -0,0 +1,44 @@ +#include +#include +#include +#include +#include + +/* really nothing to do here, both usb 1.1 & 2.0 are normal PCI devices and so get resources allocated + properly. They are part of the southbridge and are enabled in the chip enable function for the southbridge */ + +static void usb_init(struct device *dev) +{ + printk(BIOS_DEBUG, "Configuring VIA USB 1.1\n"); + + /* pci_write_config8(dev, 0x04, 0x07); */ + + /* + * To disable; though do we need to do this? + pci_write_config8(dev1, 0x3c, 0x00); + pci_write_config8(dev1, 0x04, 0x00); + + Also, on the root dev, for enable: + regval = pci_read_config8(dev0, 0x50); + regval &= ~(0x36); + pci_write_config8(dev0, 0x50, regval); + + (regval |= 0x36; for disable) + */ +} + +static struct device_operations usb_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb_init, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver northbridge_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_82C586_2, +}; + diff --git a/src/southbridge/via/vt8235/vt8235_early_serial.c b/src/southbridge/via/vt8235/vt8235_early_serial.c deleted file mode 100644 index 11f98fae39..0000000000 --- a/src/southbridge/via/vt8235/vt8235_early_serial.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Enable the serial evices on the VIA - */ - - -/* The base address is 0x15c, 0x2e, depending on config bytes */ - -#define SIO_BASE 0x3f0 -#define SIO_DATA SIO_BASE+1 - -static void vt8235_writepnpaddr(uint8_t val) -{ - outb(val, 0x2e); - outb(val, 0xeb); -} - -static void vt8235_writepnpdata(uint8_t val) -{ - outb(val, 0x2f); - outb(val, 0xeb); -} - - -static void vt8235_writesiobyte(uint16_t reg, uint8_t val) -{ - outb(val, reg); -} - -static void vt8235_writesioword(uint16_t reg, uint16_t val) -{ - outw(val, reg); -} - - -/* regs we use: 85, and the southbridge devfn is defined by the - mainboard - */ - -static void enable_vt8235_serial(void) -{ - // turn on pnp - vt8235_writepnpaddr(0x87); - vt8235_writepnpaddr(0x87); - // now go ahead and set up com1. - // set address - vt8235_writepnpaddr(0x7); - vt8235_writepnpdata(0x2); - // enable serial out - vt8235_writepnpaddr(0x30); - vt8235_writepnpdata(0x1); - // serial port 1 base address (FEh) - vt8235_writepnpaddr(0x60); - vt8235_writepnpdata(0xfe); - // serial port 1 IRQ (04h) - vt8235_writepnpaddr(0x70); - vt8235_writepnpdata(0x4); - // serial port 1 control - vt8235_writepnpaddr(0xf0); - vt8235_writepnpdata(0x2); - // turn of pnp - vt8235_writepnpaddr(0xaa); - - // set up reg to set baud rate. - vt8235_writesiobyte(0x3fb, 0x80); - // Set 115 kb - vt8235_writesioword(0x3f8, 1); - // Set 9.6 kb - // WRITESIOWORD(0x3f8, 12) - // now set no parity, one stop, 8 bits - vt8235_writesiobyte(0x3fb, 3); - // now turn on RTS, DRT - vt8235_writesiobyte(0x3fc, 3); - // Enable interrupts - vt8235_writesiobyte(0x3f9, 0xf); - // should be done. Dump a char for fun. - vt8235_writesiobyte(0x3f8, 48); -} diff --git a/src/southbridge/via/vt8235/vt8235_early_smbus.c b/src/southbridge/via/vt8235/vt8235_early_smbus.c deleted file mode 100644 index d091099fdb..0000000000 --- a/src/southbridge/via/vt8235/vt8235_early_smbus.c +++ /dev/null @@ -1,249 +0,0 @@ -#define SMBUS_IO_BASE 0xf00 - -#define SMBHSTSTAT 0x0 -#define SMBSLVSTAT 0x1 -#define SMBHSTCTL 0x2 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBBLKDAT 0x7 -#define SMBSLVCTL 0x8 -#define SMBTRNSADD 0x9 -#define SMBSLVDATA 0xa -#define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf - -/* Define register settings */ -#define HOST_RESET 0xff -#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ - - -#define SMBUS_TIMEOUT (100*1000*10) - -#define I2C_TRANS_CMD 0x40 -#define CLOCK_SLAVE_ADDRESS 0x69 - -static void enable_smbus(void) -{ - device_t dev; - unsigned char c; - int i; - - /* Power management controller */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_8235), 0); - - if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\n"); - } - - // set IO base address to SMBUS_IO_BASE - pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1); - - // Enable SMBus - pci_write_config8(dev, 0xd2, (0x4 << 1) | 1); - - /* make it work for I/O ... - */ - pci_write_config16(dev, 4, 1); - - /* FIX for half baud rate problem */ - /* let clocks and the like settle */ - /* as yet arbitrary count - 1000 is too little 5000 works */ - for(i = 0 ; i < 5000 ; i++) - outb(0x80,0x80); - - /* - * The VT1211 serial port needs 48 mhz clock, on power up it is getting - * only 24 mhz, there is some mysterious device on the smbus that can - * fix this...this code below does it. - * */ - outb(0xff, SMBUS_IO_BASE+SMBHSTSTAT); - outb(0x7f, SMBUS_IO_BASE+SMBHSTDAT0); - outb(0x83, SMBUS_IO_BASE+SMBHSTCMD); - outb(CLOCK_SLAVE_ADDRESS<<1 , SMBUS_IO_BASE+SMBXMITADD); - outb(8 | I2C_TRANS_CMD, SMBUS_IO_BASE+SMBHSTCTL); - - for (;;) { - c = inb(SMBUS_IO_BASE+SMBHSTSTAT); - if ((c & 1) == 0) - break; - } -} - - -static inline void smbus_delay(void) -{ - outb(0x80, 0x80); -} - -static int smbus_wait_until_ready(void) -{ - unsigned char c; - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - smbus_delay(); - c = inb(SMBUS_IO_BASE + SMBHSTSTAT); - while((c & 1) == 1) { - print_debug("c is "); - print_debug_hex8(c); - print_debug("\n"); - c = inb(SMBUS_IO_BASE + SMBHSTSTAT); - /* nop */ - } - - } while(--loops); - return loops?0:-1; -} - -void smbus_reset(void) -{ - outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); - outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); - outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); - outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); - - smbus_wait_until_ready(); - print_debug("After reset status "); - print_debug_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT)); - print_debug("\n"); -} - - - -static int smbus_wait_until_done(void) -{ - unsigned long loops; - unsigned char byte; - loops = SMBUS_TIMEOUT; - do { - smbus_delay(); - - byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); - if (byte & 1) - break; - - } while(--loops); - return loops?0:-1; -} - -static void smbus_print_error(unsigned char host_status_register) -{ - - print_err("smbus_error: "); - print_err_hex8(host_status_register); - print_err("\n"); - if (host_status_register & (1 << 4)) { - print_err("Interrup/SMI# was Failed Bus Transaction\n"); - } - if (host_status_register & (1 << 3)) { - print_err("Bus Error\n"); - } - if (host_status_register & (1 << 2)) { - print_err("Device Error\n"); - } - if (host_status_register & (1 << 1)) { - print_err("Interrupt/SMI# was Successful Completion\n"); - } - if (host_status_register & (1 << 0)) { - print_err("Host Busy\n"); - } -} - - -/* SMBus routines borrowed from VIA's Trident Driver */ -/* this works, so I am not going to touch it for now -- rgm */ -static unsigned char smbus_read_byte(unsigned char devAdr, - unsigned char bIndex) -{ - unsigned short i; - unsigned char bData; - unsigned char sts = 0; - - /* clear host status */ - outb(0xff, SMBUS_IO_BASE); - - /* check SMBUS ready */ - for ( i = 0; i < 0xFFFF; i++ ) - if ( (inb(SMBUS_IO_BASE) & 0x01) == 0 ) - break; - - /* set host command */ - outb(bIndex, SMBUS_IO_BASE+3); - - /* set slave address */ - outb((devAdr << 1) | 0x01, SMBUS_IO_BASE+4); - - /* start */ - outb(0x48, SMBUS_IO_BASE+2); - - /* SMBUS Wait Ready */ - for ( i = 0; i < 0xFFFF; i++ ) - if ( ((sts = (inb(SMBUS_IO_BASE) & 0x1f)) & 0x01) == 0 ) - break; - - if ((sts & ~3) != 0) { - smbus_print_error(sts); - return 0; - } - bData=inb(SMBUS_IO_BASE+5); - - return bData; - -} - -/* for reference, here is the fancier version which we will use at some - * point - */ -# if 0 -int smbus_read_byte(unsigned device, unsigned address, unsigned char *result) -{ - unsigned char host_status_register; - unsigned char byte; - - reset(); - - smbus_wait_until_ready(); - - /* setup transaction */ - /* disable interrupts */ - outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL); - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD); - /* set the command/address... */ - outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); - /* set up for a byte data read */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), - SMBUS_IO_BASE + SMBHSTCTL); - - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - - /* clear the data byte...*/ - outb(0, SMBUS_IO_BASE + SMBHSTDAT0); - - /* start the command */ - outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), - SMBUS_IO_BASE + SMBHSTCTL); - - /* poll for transaction completion */ - smbus_wait_until_done(); - - host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT); - - /* Ignore the In Use Status... */ - host_status_register &= ~(1 << 6); - - /* read results of transaction */ - byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); - smbus_print_error(byte); - - *result = byte; - return host_status_register != 0x02; -} - - -#endif - diff --git a/src/southbridge/via/vt8235/vt8235_ide.c b/src/southbridge/via/vt8235/vt8235_ide.c deleted file mode 100644 index 961f860fed..0000000000 --- a/src/southbridge/via/vt8235/vt8235_ide.c +++ /dev/null @@ -1,113 +0,0 @@ -#include -#include -#include -#include -#include -#include "chip.h" - -static void ide_init(struct device *dev) -{ - struct southbridge_via_vt8235_config *conf = dev->chip_info; - unsigned char enables; - - printk(BIOS_INFO, "Enabling VIA IDE.\n"); - - /*if (!conf->enable_native_ide) { */ - /* - * Run the IDE controller in 'compatiblity mode - i.e. don't - * use PCI interrupts. Using PCI ints confuses linux for some - * reason. - */ - printk(BIOS_INFO, "%s: enabling compatibility IDE addresses\n", - __func__); - enables = pci_read_config8(dev, 0x42); - printk(BIOS_DEBUG, "enables in reg 0x42 0x%x\n", enables); - enables &= ~0xc0; // compatability mode - pci_write_config8(dev, 0x42, enables); - enables = pci_read_config8(dev, 0x42); - printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n", - enables); - /* } */ - - enables = pci_read_config8(dev, 0x40); - printk(BIOS_DEBUG, "enables in reg 0x40 0x%x\n", enables); - enables |= 3; - pci_write_config8(dev, 0x40, enables); - enables = pci_read_config8(dev, 0x40); - printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables); - - // Enable prefetch buffers - enables = pci_read_config8(dev, 0x41); - enables |= 0xf0; - pci_write_config8(dev, 0x41, enables); - - // Lower thresholds (cause award does it) - enables = pci_read_config8(dev, 0x43); - enables &= ~0x0f; - enables |= 0x05; - pci_write_config8(dev, 0x43, enables); - - // PIO read prefetch counter (cause award does it) - pci_write_config8(dev, 0x44, 0x18); - - // Use memory read multiple - pci_write_config8(dev, 0x45, 0x1c); - - // address decoding. - // we want "flexible", i.e. 1f0-1f7 etc. or native PCI - // kevinh@ispiri.com - the standard linux drivers seem ass slow when - // used in native mode - I've changed back to classic - enables = pci_read_config8(dev, 0x9); - printk(BIOS_DEBUG, "enables in reg 0x9 0x%x\n", enables); - // by the book, set the low-order nibble to 0xa. - if (conf->enable_native_ide) { - enables &= ~0xf; - // cf/cg silicon needs an 'f' here. - enables |= 0xf; - } else { - enables &= ~0x5; - } - - pci_write_config8(dev, 0x9, enables); - enables = pci_read_config8(dev, 0x9); - printk(BIOS_DEBUG, "enables in reg 0x9 read back as 0x%x\n", enables); - - // standard bios sets master bit. - enables = pci_read_config8(dev, 0x4); - printk(BIOS_DEBUG, "command in reg 0x4 0x%x\n", enables); - enables |= 7; - - // No need for stepping - kevinh@ispiri.com - enables &= ~0x80; - - pci_write_config8(dev, 0x4, enables); - enables = pci_read_config8(dev, 0x4); - printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables); - - if (!conf->enable_native_ide) { - // Use compatability mode - per award bios - pci_write_config32(dev, 0x10, 0x0); - pci_write_config32(dev, 0x14, 0x0); - pci_write_config32(dev, 0x18, 0x0); - pci_write_config32(dev, 0x1c, 0x0); - - // Force interrupts to use compat mode - just like Award bios - pci_write_config8(dev, 0x3d, 0x0); - pci_write_config8(dev, 0x3c, 0xff); - } -} - -static struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .enable = 0, - .ops_pci = 0, -}; - -static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_82C586_1, -}; diff --git a/src/southbridge/via/vt8235/vt8235_lpc.c b/src/southbridge/via/vt8235/vt8235_lpc.c deleted file mode 100644 index b355ad0d88..0000000000 --- a/src/southbridge/via/vt8235/vt8235_lpc.c +++ /dev/null @@ -1,261 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include "chip.h" - -/* The epia-m is really short on interrupts available, so PCI interupts A & D are ganged togther and so are B & C. - This is how the Award bios sets it up too. - epia can be more generous as it does not need to reserve interrupts for cardbus devices, but if changed then - make sure that ACPI dsdt is changed to suit. - - IRQ 0 = timer - IRQ 1 = keyboard - IRQ 2 = cascade - IRQ 3 = COM 2 - IRQ 4 = COM 1 - IRQ 5 = available for PCI interrupts - IRQ 6 = floppy or availbale for PCI if floppy controller disabled - IRQ 7 = LPT or available if LPT port disabled - IRQ 8 = rtc - IRQ 9 = available for PCI interrupts - IRQ 10 = cardbus slot or available for PCI if no cardbus (ie epia) - IRQ 11 = cardbus slot or available for PCI if no cardbus (ie epia) - IRQ 12 = PS2 mouse (hardwired to 12) - IRQ 13 = legacy FPU interrupt - IRQ 14 = IDE controller 1 - IRQ 15 = IDE controller 2 - -*/ -static const unsigned char pciIrqs[4] = { 5 , 9 , 9, 5 }; - -static const unsigned char usbPins[4] = { 'A','B','C','D'}; -static const unsigned char enetPins[4] = { 'A','B','C','D'}; -static const unsigned char slotPins[4] = { 'B','C','D','A'}; -static const unsigned char firewirePins[4] = { 'B','C','D','A'}; -static const unsigned char vt8235Pins[4] = { 'A','B','C','D'}; -static const unsigned char vgaPins[4] = { 'A','B','C','D'}; -static const unsigned char cbPins[4] = { 'A','B','C','D'}; -static const unsigned char riserPins[4] = { 'A','B','C','D'}; - - -static unsigned char *pin_to_irq(const unsigned char *pin) -{ - static unsigned char Irqs[4]; - int i; - for (i = 0 ; i < 4 ; i++) - Irqs[i] = pciIrqs[ pin[i] - 'A' ]; - - return Irqs; -} - -static void pci_routing_fixup(struct device *dev) -{ - printk(BIOS_INFO, "%s: dev is %p\n", __func__, dev); - - /* set up PCI IRQ routing */ - pci_write_config8(dev, 0x55, pciIrqs[0] << 4); - pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4) ); - pci_write_config8(dev, 0x57, pciIrqs[3] << 4); - - - // firewire built into southbridge - printk(BIOS_INFO, "setting firewire\n"); - pci_assign_irqs(0, 0x0d, pin_to_irq(firewirePins)); - - // Standard usb components - printk(BIOS_INFO, "setting usb\n"); - pci_assign_irqs(0, 0x10, pin_to_irq(usbPins)); - - // VT8235 + sound hardware - printk(BIOS_INFO, "setting vt8235\n"); - pci_assign_irqs(0, 0x11, pin_to_irq(vt8235Pins)); - - // Ethernet built into southbridge - printk(BIOS_INFO, "setting ethernet\n"); - pci_assign_irqs(0, 0x12, pin_to_irq(enetPins)); - - // VGA - printk(BIOS_INFO, "setting vga\n"); - pci_assign_irqs(1, 0x00, pin_to_irq(vgaPins)); - - // PCI slot - printk(BIOS_INFO, "setting pci slot\n"); - pci_assign_irqs(0, 0x14, pin_to_irq(slotPins)); - - // Cardbus slot - printk(BIOS_INFO, "setting cardbus slot\n"); - pci_assign_irqs(0, 0x0a, pin_to_irq(cbPins)); - - // Via 2 slot riser card 2nd slot - printk(BIOS_INFO, "setting riser slot\n"); - pci_assign_irqs(0, 0x13, pin_to_irq(riserPins)); - - printk(BIOS_SPEW, "%s: DONE\n", __func__); -} - -/* - * Set up the power management capabilities directly into ACPI mode. This - * avoids having to handle any System Management Interrupts (SMI's) which I - * can't figure out how to do !!!! - */ - -static void setup_pm(device_t dev) -{ - // Set gen config 0 - pci_write_config8(dev, 0x80, 0x20); - - // Set ACPI base address to IO 0x400 - pci_write_config16(dev, 0x88, 0x0401); - - // set ACPI irq to 5 - pci_write_config8(dev, 0x82, 0x45); - - // primary interupt channel - pci_write_config16(dev, 0x84, 0x30f2); - - // throttle / stop clock control - pci_write_config8(dev, 0x8d, 0x18); - - pci_write_config8(dev, 0x93, 0x88); - pci_write_config8(dev, 0x94, 0xb0); - pci_write_config8(dev, 0x95, 0xc0); - pci_write_config8(dev, 0x98, 0); - pci_write_config8(dev, 0x99, 0xea); - pci_write_config8(dev, 0xe4, 0x14); - pci_write_config8(dev, 0xe5, 0x08); - - - // Enable ACPI access (and setup like award) - pci_write_config8(dev, 0x81, 0x84); - - outw(0xffff, 0x400); - outw(0xffff, 0x420); - outw(0xffff, 0x428); - outl(0xffffffff, 0x430); - - outw(0x0, 0x424); - outw(0x0, 0x42a); - outw(0x1, 0x42c); - outl(0x0, 0x434); - outl(0x01, 0x438); - outb(0x0, 0x442); - outl(0xffff7fff, 0x448); - outw(0x001, 0x404); -} - -static void vt8235_init(struct device *dev) -{ - unsigned char enables; - - printk(BIOS_DEBUG, "vt8235 init\n"); - - // enable the internal I/O decode - enables = pci_read_config8(dev, 0x6C); - enables |= 0x80; - pci_write_config8(dev, 0x6C, enables); - - // Map 4MB of FLASH into the address space - pci_write_config8(dev, 0x41, 0x7f); - - // Set bit 6 of 0x40, because Award does it (IO recovery time) - // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI - // interrupts can be properly marked as level triggered. - enables = pci_read_config8(dev, 0x40); - enables |= 0x45; - pci_write_config8(dev, 0x40, enables); - - // Set 0x42 to 0xf0 to match Award bios - enables = pci_read_config8(dev, 0x42); - enables |= 0xf0; - pci_write_config8(dev, 0x42, enables); - - /* Set 0x58 to 0x03 to match Award */ - pci_write_config8(dev, 0x58, 0x03); - - /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */ - enables = pci_read_config8(dev, 0x4f); - enables |= 0x08; - pci_write_config8(dev, 0x4f, enables); - - // Set bit 3 of 0x4a, to match award (dummy pci request) - enables = pci_read_config8(dev, 0x4a); - enables |= 0x08; - pci_write_config8(dev, 0x4a, enables); - - // Set bit 3 of 0x4f to match award (use INIT# as cpu reset) - enables = pci_read_config8(dev, 0x4f); - enables |= 0x08; - pci_write_config8(dev, 0x4f, enables); - - // Set 0x58 to 0x03 to match Award - pci_write_config8(dev, 0x58, 0x03); - - - /* enable serial irq */ - pci_write_config8(dev, 0x52, 0x9); - - /* dma */ - pci_write_config8(dev, 0x53, 0x00); - - // Power management setup - setup_pm(dev); - - /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */ - pci_write_config8(dev, 0x40, 0x54); - - // Start the rtc - rtc_init(0); -} - -/* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this - device has a resource to set - so set a dummy one */ -static void vt8235_read_resources(device_t dev) -{ - struct resource *res; - - pci_dev_read_resources(dev); - - res = new_resource(dev, 1); - res->base = 0x0UL; - res->size = 0x1000UL; - res->limit = 0xffffUL; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -static void vt8235_set_resources(device_t dev) -{ - //struct resource *resource; - //resource = find_resource(dev,1); - //resource->flags |= IORESOURCE_STORED; - pci_dev_set_resources(dev); -} - -static void southbridge_init(struct device *dev) -{ - vt8235_init(dev); - pci_routing_fixup(dev); -} - -static struct device_operations vt8235_lpc_ops = { - .read_resources = vt8235_read_resources, - .set_resources = vt8235_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = southbridge_init, - .scan_bus = scan_static_bus, -}; - -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &vt8235_lpc_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_8235, -}; diff --git a/src/southbridge/via/vt8235/vt8235_nic.c b/src/southbridge/via/vt8235/vt8235_nic.c deleted file mode 100644 index 71f169c055..0000000000 --- a/src/southbridge/via/vt8235/vt8235_nic.c +++ /dev/null @@ -1,36 +0,0 @@ -#include -#include -#include -#include -#include - -/* - * Enable the ethernet device and turn off stepping (because it is integrated - * inside the southbridge) - */ -static void nic_init(struct device *dev) -{ - uint8_t byte; - - printk(BIOS_DEBUG, "Configuring VIA Rhine LAN\n"); - - /* We don't need stepping - though the device supports it */ - byte = pci_read_config8(dev, PCI_COMMAND); - byte &= ~PCI_COMMAND_WAIT; - pci_write_config8(dev, PCI_COMMAND, byte); -} - -static struct device_operations nic_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = nic_init, - .enable = 0, - .ops_pci = 0, -}; - -static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_8233_7, -}; diff --git a/src/southbridge/via/vt8235/vt8235_usb.c b/src/southbridge/via/vt8235/vt8235_usb.c deleted file mode 100644 index c712136c72..0000000000 --- a/src/southbridge/via/vt8235/vt8235_usb.c +++ /dev/null @@ -1,44 +0,0 @@ -#include -#include -#include -#include -#include - -/* really nothing to do here, both usb 1.1 & 2.0 are normal PCI devices and so get resources allocated - properly. They are part of the southbridge and are enabled in the chip enable function for the southbridge */ - -static void usb_init(struct device *dev) -{ - printk(BIOS_DEBUG, "Configuring VIA USB 1.1\n"); - - /* pci_write_config8(dev, 0x04, 0x07); */ - - /* - * To disable; though do we need to do this? - pci_write_config8(dev1, 0x3c, 0x00); - pci_write_config8(dev1, 0x04, 0x00); - - Also, on the root dev, for enable: - regval = pci_read_config8(dev0, 0x50); - regval &= ~(0x36); - pci_write_config8(dev0, 0x50, regval); - - (regval |= 0x36; for disable) - */ -} - -static struct device_operations usb_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb_init, - .enable = 0, - .ops_pci = 0, -}; - -static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_82C586_2, -}; - diff --git a/src/southbridge/via/vt8237r/Makefile.inc b/src/southbridge/via/vt8237r/Makefile.inc index 04adb4b6d9..dd14a00fdc 100644 --- a/src/southbridge/via/vt8237r/Makefile.inc +++ b/src/southbridge/via/vt8237r/Makefile.inc @@ -18,10 +18,10 @@ ## driver-y += vt8237r.c -driver-y += vt8237_ctrl.c -driver-y += vt8237r_ide.c -driver-y += vt8237r_lpc.c -driver-y += vt8237r_sata.c -driver-y += vt8237r_usb.c -driver-$(CONFIG_PIRQ_ROUTE) += vt8237r_pirq.c -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += vt8237_fadt.c +driver-y += ctrl.c +driver-y += ide.c +driver-y += lpc.c +driver-y += sata.c +driver-y += usb.c +driver-$(CONFIG_PIRQ_ROUTE) += pirq.c +ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c diff --git a/src/southbridge/via/vt8237r/ctrl.c b/src/southbridge/via/vt8237r/ctrl.c new file mode 100644 index 0000000000..f3cc30ed88 --- /dev/null +++ b/src/southbridge/via/vt8237r/ctrl.c @@ -0,0 +1,289 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include "vt8237r.h" + +/* We support here K8M890/K8T890 and VT8237/S/A PCI1/Vlink */ + +static void vt8237_cfg(struct device *dev) +{ + u8 regm, regm3; + device_t devfun3; + + devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CE_3, 0); + if (!devfun3) + devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8M890CE_3, 0); + if (!devfun3) + devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CF_3, 0); + if (!devfun3) + die("Unknown NB"); + + /* CPU to PCI Flow Control 1 & 2, just fill in recommended. */ + pci_write_config8(dev, 0x70, 0xc2); + pci_write_config8(dev, 0x71, 0xc8); + + /* PCI Control */ + pci_write_config8(dev, 0x72, 0xee); + pci_write_config8(dev, 0x73, 0x01); + pci_write_config8(dev, 0x74, 0x3c); + pci_write_config8(dev, 0x75, 0x0f); + pci_write_config8(dev, 0x76, 0x50); + pci_write_config8(dev, 0x77, 0x48); + pci_write_config8(dev, 0x78, 0x01); + /* APIC on HT */ + /* Maybe Enable LDT APIC Mode bit3 set to 1 */ + pci_write_config8(dev, 0x7c, 0x77); + + /* WARNING: Need to copy some registers from NB (D0F3) to SB (D11F7). */ + + regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */ + pci_write_config8(dev, 0x57, regm); + + regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */ + pci_write_config8(dev, 0x61, regm); + + regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */ + pci_write_config8(dev, 0x62, regm); + + /* Shadow page F + memhole copy */ + regm = pci_read_config8(devfun3, 0x83); + pci_write_config8(dev, 0x63, regm); + + // FIXME is this really supposed to be regm3? + regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */ + pci_write_config8(dev, 0x64, regm); + + regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */ + pci_write_config8(dev, 0xe6, regm); +} + +/** + * Example of setup: Setup the V-Link for VT8237R, 8X mode. + * + * For K8T890CF VIA recommends what is in VIA column, AW is award 8X: + * + * REG DEF AW VIA-8X VIA-4X + * ----------------------------- + * NB V-Link Manual Driving Control strobe 0xb5 0x46 0x46 0x88 0x88 + * NB V-Link Manual Driving Control - Data 0xb6 0x46 0x46 0x88 0x88 + * NB V-Link Receiving Strobe Delay 0xb7 0x02 0x02 0x61 0x01 + * NB V-Link Compensation Control bit4,0 (b5,b6) 0xb4 0x10 0x10 0x11 0x11 + * SB V-Link Strobe Drive Control 0xb9 0x00 0xa5 0x98 0x98 + * SB V-Link Data drive Control???? 0xba 0x00 0xbb 0x77 0x77 + * SB V-Link Receive Strobe Delay???? 0xbb 0x04 0x11 0x11 0x11 + * SB V-Link Compensation Control bit0 (use b9) 0xb8 0x00 0x01 0x01 0x01 + * V-Link CKG Control 0xb0 0x05 0x05 0x06 0x03 + * V-Link CKG Control 0xb1 0x05 0x05 0x01 0x03 + */ + +/* we setup 533MB/s mode full duplex */ + +static void vt8237s_vlink_init(struct device *dev) +{ + u8 reg; + device_t devfun7; + + devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CE_7, 0); + if (!devfun7) + devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8M890CE_7, 0); + if (!devfun7) + devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CF_7, 0); + /* No pairing NB was found. */ + if (!devfun7) + return; + + /* + * This init code is valid only for the VT8237S! For different + * sounthbridges (e.g. VT8237A, VT8237S, VT8237R (without plus R) + * and VT8251) a different init code is required. + */ + + /* disable auto disconnect */ + reg = pci_read_config8(devfun7, 0x42); + reg &= ~0x4; + pci_write_config8(devfun7, 0x42, reg); + + /* NB part setup */ + pci_write_config8(devfun7, 0xb5, 0x66); + pci_write_config8(devfun7, 0xb6, 0x66); + pci_write_config8(devfun7, 0xb7, 0x64); + + reg = pci_read_config8(devfun7, 0xb4); + reg |= 0x1; + reg &= ~0x10; + pci_write_config8(devfun7, 0xb4, reg); + + pci_write_config8(devfun7, 0xb0, 0x6); + pci_write_config8(devfun7, 0xb1, 0x1); + + /* SB part setup */ + pci_write_config8(dev, 0xb7, 0x60); + pci_write_config8(dev, 0xb9, 0x88); + pci_write_config8(dev, 0xba, 0x88); + pci_write_config8(dev, 0xbb, 0x89); + + reg = pci_read_config8(dev, 0xbd); + reg |= 0x3; + reg &= ~0x4; + pci_write_config8(dev, 0xbd, reg); + + reg = pci_read_config8(dev, 0xbc); + reg &= ~0x7; + pci_write_config8(dev, 0xbc, reg); + + /* Program V-link 8X 8bit full duplex, parity enabled. */ + pci_write_config8(dev, 0x48, 0x23 | 0x80); + + /* enable auto disconnect, for STPGNT and HALT */ + reg = pci_read_config8(devfun7, 0x42); + reg |= 0x7; + pci_write_config8(devfun7, 0x42, reg); + +} + +static void vt8237a_vlink_init(struct device *dev) +{ + u8 reg; + device_t devfun7; + + devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CE_7, 0); + if (!devfun7) + devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8M890CE_7, 0); + if (!devfun7) + devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CF_7, 0); + /* No pairing NB was found. */ + if (!devfun7) + return; + + /* + * This init code is valid only for the VT8237A! For different + * sounthbridges (e.g. VT8237S, VT8237R and VT8251) a different + * init code is required. + * + * FIXME: This is based on vt8237r_vlink_init() in + * k8t890/k8t890_ctrl.c and modified to fit what the AMI + * BIOS on my M2V wrote to these registers (by looking + * at lspci -nxxx output). + * Works for me. + */ + + /* disable auto disconnect */ + reg = pci_read_config8(devfun7, 0x42); + reg &= ~0x4; + pci_write_config8(devfun7, 0x42, reg); + + /* NB part setup */ + pci_write_config8(devfun7, 0xb5, 0x88); + pci_write_config8(devfun7, 0xb6, 0x88); + pci_write_config8(devfun7, 0xb7, 0x61); + + reg = pci_read_config8(devfun7, 0xb4); + reg |= 0x11; + pci_write_config8(devfun7, 0xb4, reg); + + pci_write_config8(devfun7, 0xb0, 0x6); + pci_write_config8(devfun7, 0xb1, 0x1); + + /* SB part setup */ + pci_write_config8(dev, 0xb7, 0x50); + pci_write_config8(dev, 0xb9, 0x88); + pci_write_config8(dev, 0xba, 0x8a); + pci_write_config8(dev, 0xbb, 0x88); + + reg = pci_read_config8(dev, 0xbd); + reg |= 0x3; + reg &= ~0x4; + pci_write_config8(dev, 0xbd, reg); + + reg = pci_read_config8(dev, 0xbc); + reg &= ~0x7; + pci_write_config8(dev, 0xbc, reg); + + pci_write_config8(dev, 0x48, 0x23); + + /* enable auto disconnect, for STPGNT and HALT */ + reg = pci_read_config8(devfun7, 0x42); + reg |= 0x7; + pci_write_config8(devfun7, 0x42, reg); +} + +static void ctrl_enable(struct device *dev) +{ + /* Enable the 0:13 and 0:13.1. */ + /* FIXME */ + pci_write_config8(dev, 0x4f, 0x43); +} + +static void ctrl_init(struct device *dev) +{ + /* + * TODO: Fix some ordering issue for V-link set Rx77[6] and + * PCI1_Rx4F[0] should to 1. + * FIXME DO you need? + */ + + /* + * VT8237R specific configuration. Other SB are done in their own + * directories. TODO: Add A version. + */ + device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237S_LPC, 0); + if (devsb) { + vt8237s_vlink_init(dev); + } + + devsb = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237A_LPC, 0); + if (devsb) { + vt8237a_vlink_init(dev); + } + + /* Configure PCI1 and copy mirror registers from D0F3. */ + vt8237_cfg(dev); + dump_south(dev); +} + +static const struct device_operations ctrl_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ctrl_init, + .enable = ctrl_enable, + .ops_pci = 0, +}; + +static const struct pci_driver northbridge_driver_t __pci_driver = { + .ops = &ctrl_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT8237_VLINK, +}; diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c new file mode 100644 index 0000000000..a298e84676 --- /dev/null +++ b/src/southbridge/via/vt8237r/early_smbus.c @@ -0,0 +1,498 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Corey Osgood + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include "vt8237r.h" + +/** + * Print an error, should it occur. If no error, just exit. + * + * @param host_status The data returned on the host status register after + * a transaction is processed. + * @param loops The number of times a transaction was attempted. + */ +static void smbus_print_error(u8 host_status, int loops) +{ + /* Check if there actually was an error. */ + if ((host_status == 0x00 || host_status == 0x40 || + host_status == 0x42) && (loops < SMBUS_TIMEOUT)) + return; + + if (loops >= SMBUS_TIMEOUT) + print_err("SMBus timeout\n"); + if (host_status & (1 << 4)) + print_err("Interrupt/SMI# was Failed Bus Transaction\n"); + if (host_status & (1 << 3)) + print_err("Bus error\n"); + if (host_status & (1 << 2)) + print_err("Device error\n"); + if (host_status & (1 << 1)) + print_debug("Interrupt/SMI# completed successfully\n"); + if (host_status & (1 << 0)) + print_err("Host busy\n"); +} + +/** + * Wait for the SMBus to become ready to process the next transaction. + */ +static void smbus_wait_until_ready(void) +{ + int loops; + + PRINT_DEBUG("Waiting until SMBus ready\n"); + + /* Loop up to SMBUS_TIMEOUT times, waiting for bit 0 of the + * SMBus Host Status register to go to 0, indicating the operation + * was completed successfully. I don't remember why I did it this way, + * but I think it was because ROMCC was running low on registers */ + loops = 0; + while ((inb(SMBHSTSTAT) & 1) == 1 && loops < SMBUS_TIMEOUT) + ++loops; + + smbus_print_error(inb(SMBHSTSTAT), loops); +} + +/** + * Reset and take ownership of the SMBus. + */ +static void smbus_reset(void) +{ + outb(HOST_RESET, SMBHSTSTAT); + + /* Datasheet says we have to read it to take ownership of SMBus. */ + inb(SMBHSTSTAT); + + PRINT_DEBUG("After reset status: "); + PRINT_DEBUG_HEX16(inb(SMBHSTSTAT)); + PRINT_DEBUG("\n"); +} + +/** + * Read a byte from the SMBus. + * + * @param dimm The address location of the DIMM on the SMBus. + * @param offset The offset the data is located at. + */ +u8 smbus_read_byte(u8 dimm, u8 offset) +{ + u8 val; + + PRINT_DEBUG("DIMM "); + PRINT_DEBUG_HEX16(dimm); + PRINT_DEBUG(" OFFSET "); + PRINT_DEBUG_HEX16(offset); + PRINT_DEBUG("\n"); + + smbus_reset(); + + /* Clear host data port. */ + outb(0x00, SMBHSTDAT0); + SMBUS_DELAY(); + smbus_wait_until_ready(); + + /* Actual addr to reg format. */ + dimm = (dimm << 1); + dimm |= 1; + outb(dimm, SMBXMITADD); + outb(offset, SMBHSTCMD); + + /* Start transaction, byte data read. */ + outb(0x48, SMBHSTCTL); + SMBUS_DELAY(); + smbus_wait_until_ready(); + + val = inb(SMBHSTDAT0); + PRINT_DEBUG("Read: "); + PRINT_DEBUG_HEX16(val); + PRINT_DEBUG("\n"); + + /* Probably don't have to do this, but it can't hurt. */ + smbus_reset(); + + return val; +} + +#define PSONREADY_TIMEOUT 0x7fffffff + +static device_t get_vt8237_lpc(void) +{ + device_t dev; + + /* Power management controller */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); + if (dev != PCI_DEV_INVALID) + return dev; + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); + if (dev != PCI_DEV_INVALID) + return dev; + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237A_LPC), 0); + return dev; +} + +/** + * Enable the SMBus on VT8237R-based systems. + */ +void enable_smbus(void) +{ + device_t dev; + int loops; + + /* Power management controller */ + dev = get_vt8237_lpc(); + if (dev == PCI_DEV_INVALID) + die("Power management controller not found\n"); + + /* Make sure the RTC power well is up before touching smbus. */ + loops = 0; + while (!(pci_read_config8(dev, VT8237R_PSON) & (1<<6)) + && loops < PSONREADY_TIMEOUT) + ++loops; + + /* + * 7 = SMBus Clock from RTC 32.768KHz + * 5 = Internal PLL reset from susp + */ + pci_write_config8(dev, VT8237R_POWER_WELL, 0xa0); + + /* Enable SMBus. */ + pci_write_config16(dev, VT8237R_SMBUS_IO_BASE_REG, + VT8237R_SMBUS_IO_BASE | 0x1); + + /* SMBus Host Configuration, enable. */ + pci_write_config8(dev, VT8237R_SMBUS_HOST_CONF, 0x01); + + /* Make it work for I/O. */ + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); + + smbus_reset(); + + /* Reset the internal pointer. */ + inb(SMBHSTCTL); +} + +/** + * A fixup for some systems that need time for the SMBus to "warm up". This is + * needed on some VT823x based systems, where the SMBus spurts out bad data for + * a short time after power on. This has been seen on the VIA Epia series and + * Jetway J7F2-series. It reads the ID byte from SMBus, looking for + * known-good data from a slot/address. Exits on either good data or a timeout. + * + * TODO: This should probably go into some global file, but one would need to + * be created just for it. If some other chip needs/wants it, we can + * worry about it then. + * + * @param ctrl The memory controller and SMBus addresses. + */ +void smbus_fixup(const struct mem_controller *ctrl) +{ + int i, ram_slots, current_slot = 0; + u8 result = 0; + + ram_slots = ARRAY_SIZE(ctrl->channel0); + if (!ram_slots) { + print_err("smbus_fixup() thinks there are no RAM slots!\n"); + return; + } + + PRINT_DEBUG("Waiting for SMBus to warm up"); + + /* + * Bad SPD data should be either 0 or 0xff, but YMMV. So we look for + * the ID bytes of SDRAM, DDR, DDR2, and DDR3 (and anything in between). + * VT8237R has only been seen on DDR and DDR2 based systems, so far. + */ + for (i = 0; (i < SMBUS_TIMEOUT && ((result < SPD_MEMORY_TYPE_SDRAM) || + (result > SPD_MEMORY_TYPE_SDRAM_DDR3))); i++) { + + if (current_slot > ram_slots) + current_slot = 0; + + result = smbus_read_byte(ctrl->channel0[current_slot], + SPD_MEMORY_TYPE); + current_slot++; + PRINT_DEBUG("."); + } + + if (i >= SMBUS_TIMEOUT) + print_err("SMBus timed out while warming up\n"); + else + PRINT_DEBUG("Done\n"); +} + +/* FIXME: Better separate the NB and SB, will be done once it works. */ + +void vt8237_sb_enable_fid_vid(void) +{ + device_t dev, devctl; + u16 devid; + + /* Power management controller */ + dev = get_vt8237_lpc(); + if (dev == PCI_DEV_INVALID) + return; + + devid = pci_read_config16(dev, PCI_DEVICE_ID); + + /* generic setup */ + + /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ + pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); + + /* Enable ACPI accessm RTC signal gated with PSON. */ + pci_write_config8(dev, 0x81, 0x84); + + /* chipset-specific parts */ + + /* VLINK: FIXME: can we drop the devid check and just look for the VLINK device? */ + if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC || + devid == PCI_DEVICE_ID_VIA_VT8237A_LPC) { + devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237_VLINK), 0); + + if (devctl != PCI_DEV_INVALID) { + /* So the chip knows we are on AMD. */ + pci_write_config8(devctl, 0x7c, 0x7f); + } + } + + if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC) { + /* + * Allow SLP# signal to assert LDTSTOP_L. + * Will work for C3 and for FID/VID change. + */ + + outb(0xff, VT8237R_ACPI_IO_BASE + 0x50); + + /* Reduce further the STPCLK/LDTSTP signal to 5us. */ + pci_write_config8(dev, 0xec, 0x4); + + return; + } + + /* VT8237R and VT8237A */ + + /* + * Allow SLP# signal to assert LDTSTOP_L. + * Will work for C3 and for FID/VID change. + */ + outb(0x1, VT8237R_ACPI_IO_BASE + 0x11); +} + +void enable_rom_decode(void) +{ + device_t dev; + + /* Power management controller */ + dev = get_vt8237_lpc(); + if (dev == PCI_DEV_INVALID) + return; + + /* ROM decode last 1MB FFC00000 - FFFFFFFF. */ + pci_write_config8(dev, 0x41, 0x7f); +} + +#if CONFIG_HAVE_ACPI_RESUME == 1 +static int acpi_is_wakeup_early(void) { + device_t dev; + u16 tmp; + + print_debug("IN TEST WAKEUP\n"); + + /* Power management controller */ + dev = get_vt8237_lpc(); + if (dev == PCI_DEV_INVALID) + die("Power management controller not found\n"); + + /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ + pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); + + /* Enable ACPI accessm RTC signal gated with PSON. */ + pci_write_config8(dev, 0x81, 0x84); + + tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); + + print_debug_hex8(tmp); + return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; +} +#endif + +#if defined(__GNUC__) +void vt8237_early_spi_init(void) +{ + device_t dev; + volatile u16 *spireg; + u32 tmp; + + /* Bus Control and Power Management */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); + + if (dev == PCI_DEV_INVALID) + die("SB not found\n"); + + /* Put SPI base 20 d0 fe. */ + tmp = pci_read_config32(dev, 0xbc); + pci_write_config32(dev, 0xbc, + (VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000)); + + /* Set SPI clock to 33MHz. */ + spireg = (u16 *) (VT8237S_SPI_MEM_BASE + 0x6c); + (*spireg) &= 0xff00; +} +#endif + +/* This #if is special. ROMCC chokes on the (rom == NULL) comparison. + * Since the whole function is only called for one target and that target + * is compiled with GCC, hide the function from ROMCC and be happy. + */ +#if defined(__GNUC__) +/* + * Offset 0x58: + * 31:20 reserved + * 19:16 4 bit position in shadow EEPROM + * 15:0 data to write + * + * Offset 0x5c: + * 31:28 reserved + * 27 ERDBG - enable read from 0x5c + * 26 reserved + * 25 SEELD + * 24 SEEPR - write 1 when done updating, wait until SEELD is + * set to 1, sticky + * cleared by reset, if it is 1 writing is disabled + * 19:16 4 bit position in shadow EEPROM + * 15:0 data from shadow EEPROM + * + * After PCIRESET SEELD and SEEPR must be 1 and 1. + */ + +/* 1 = needs PCI reset, 0 don't reset, network initialized. */ + +/* FIXME: Maybe close the debug register after use? */ + +#define LAN_TIMEOUT 0x7FFFFFFF + +int vt8237_early_network_init(struct vt8237_network_rom *rom) +{ + struct vt8237_network_rom n; + int i, loops; + device_t dev; + u32 tmp; + u8 status; + u16 *rom_write; + unsigned int checksum; + + /* Network adapter */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_8233_7), 0); + if (dev == PCI_DEV_INVALID) { + print_err("Network is disabled, please enable\n"); + return 0; + } + + tmp = pci_read_config32(dev, 0x5c); + tmp |= 0x08000000; /* Enable ERDBG. */ + pci_write_config32(dev, 0x5c, tmp); + + status = ((pci_read_config32(dev, 0x5c) >> 24) & 0x3); + + /* Network controller OK, EEPROM loaded. */ + if (status == 3) + return 0; + + if (rom == NULL) { + print_err("No config data specified, using default MAC!\n"); + n.mac_address[0] = 0x0; + n.mac_address[1] = 0x0; + n.mac_address[2] = 0xde; + n.mac_address[3] = 0xad; + n.mac_address[4] = 0xbe; + n.mac_address[5] = 0xef; + n.phy_addr = 0x1; + n.res1 = 0x0; + n.sub_sid = 0x102; + n.sub_vid = 0x1106; + n.pid = 0x3065; + n.vid = 0x1106; + n.pmcc = 0x1f; + n.data_sel = 0x10; + n.pmu_data_reg = 0x0; + n.aux_curr = 0x0; + n.reserved = 0x0; + n.min_gnt = 0x3; + n.max_lat = 0x8; + n.bcr0 = 0x9; + n.bcr1 = 0xe; + n.cfg_a = 0x3; + n.cfg_b = 0x0; + n.cfg_c = 0x40; + n.cfg_d = 0x82; + n.checksum = 0x0; + rom = &n; + } + + rom_write = (u16 *) rom; + checksum = 0; + /* Write all data except checksum and second to last byte. */ + tmp &= 0xff000000; /* Leave reserved bits in. */ + for (i = 0; i < 15; i++) { + pci_write_config32(dev, 0x58, tmp | (i << 16) | rom_write[i]); + /* Lame code FIXME */ + checksum += rom_write[i] & 0xff; + /* checksum %= 256; */ + checksum += (rom_write[i] >> 8) & 0xff; + /* checksum %= 256; */ + } + + checksum += (rom_write[15] & 0xff); + checksum = ~(checksum & 0xff); + tmp |= (((checksum & 0xff) << 8) | rom_write[15]); + + /* Write last byte and checksum. */ + pci_write_config32(dev, 0x58, (15 << 16) | tmp); + + tmp = pci_read_config32(dev, 0x5c); + pci_write_config32(dev, 0x5c, tmp | 0x01000000); /* Toggle SEEPR. */ + + /* Yes, this is a mess, but it's the easiest way to do it. */ + /* XXX not so messy, but an explanation of the hack would have been better */ + loops = 0; + while ((((pci_read_config32(dev, 0x5c) >> 25) & 1) == 0) + && (loops < LAN_TIMEOUT)) { + ++loops; + } + + if (loops >= LAN_TIMEOUT) { + print_err("Timeout - LAN controller didn't accept config\n"); + return 0; + } + + /* We are done, config will be used after PCIRST#. */ + return 1; +} +#endif diff --git a/src/southbridge/via/vt8237r/fadt.c b/src/southbridge/via/vt8237r/fadt.c new file mode 100644 index 0000000000..6976f4d447 --- /dev/null +++ b/src/southbridge/via/vt8237r/fadt.c @@ -0,0 +1,173 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker + * Copyright (C) 2007, 2009 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include "vt8237r.h" + +/** + * Create the Fixed ACPI Description Tables (FADT) for any board with this SB. + */ +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + device_t dev; + int is_vt8237s = 0; + + /* Power management controller */ + dev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237S_LPC, 0); + + if (dev) + is_vt8237s = 1; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 244; + header->revision = 4; + memcpy(header->oem_id, "COREBO", 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, "CORE", 4); + header->asl_compiler_revision = 42; + + fadt->firmware_ctrl = (u32)facs; + fadt->dsdt = (u32)dsdt; + fadt->preferred_pm_profile = 0; + fadt->sci_int = 9; + fadt->smi_cmd = 0; + fadt->acpi_enable = 0; + fadt->acpi_disable = 0; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0x0; + + fadt->pm1a_evt_blk = VT8237R_ACPI_IO_BASE; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = VT8237R_ACPI_IO_BASE + 0x4; + fadt->pm1b_cnt_blk = 0x0; + /* once we support C2/C3 this could be set to 0x22 and chipset needs to be adjusted too */ + fadt->pm2_cnt_blk = 0x0; + fadt->pm_tmr_blk = VT8237R_ACPI_IO_BASE + 0x8; + fadt->gpe0_blk = VT8237R_ACPI_IO_BASE + 0x20; + if (is_vt8237s) { + fadt->gpe1_blk = VT8237R_ACPI_IO_BASE + 0x60; + fadt->gpe1_base = 0x10; + fadt->gpe1_blk_len = 4; + } else { + fadt->gpe1_blk = 0x0; + fadt->gpe1_base = 0; + fadt->gpe1_blk_len = 0; + } + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 0; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 4; + + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 90; + fadt->p_lvl3_lat = 900; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 0; + fadt->duty_width = 1; //?? + fadt->day_alrm = 0x7d; + fadt->mon_alrm = 0x7e; + fadt->century = 0x32; + /* We have legacy devices, 8042, VGA is ok to probe, MSI are not supported */ + fadt->iapc_boot_arch = 0xb; + /* check me */ + fadt->flags = 0xa5; + + fadt->reset_reg.space_id = 0; + fadt->reset_reg.bit_width = 0; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0x0; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 0; + fadt->x_firmware_ctl_l = (u32)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); +} diff --git a/src/southbridge/via/vt8237r/ide.c b/src/southbridge/via/vt8237r/ide.c new file mode 100644 index 0000000000..209437b729 --- /dev/null +++ b/src/southbridge/via/vt8237r/ide.c @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Based on other VIA SB code. */ + +#include +#include +#include +#include +#include "vt8237r.h" +#include "chip.h" + +/** + * Cable type detect function, weak so it can be overloaded in mainboard.c + */ +u32 __attribute__((weak)) vt8237_ide_80pin_detect(struct device *dev) +{ + struct southbridge_via_vt8237r_config *sb = + (struct southbridge_via_vt8237r_config *)dev->chip_info; + u32 res; + res = sb->ide0_80pin_cable ? VT8237R_IDE0_80PIN_CABLE : 0; + res |= sb->ide1_80pin_cable ? VT8237R_IDE1_80PIN_CABLE : 0; + return res; +} + +/** + * No native mode. Interrupts from unconnected HDDs might occur if + * IRQ14/15 is used for PCI. Therefore no native mode support. + */ +static void ide_init(struct device *dev) +{ + struct southbridge_via_vt8237r_config *sb = + (struct southbridge_via_vt8237r_config *)dev->chip_info; + + u8 enables; + u32 cablesel; + + printk(BIOS_INFO, "%s IDE interface %s\n", "Primary", + sb->ide0_enable ? "enabled" : "disabled"); + printk(BIOS_INFO, "%s IDE interface %s\n", "Secondary", + sb->ide1_enable ? "enabled" : "disabled"); + enables = pci_read_config8(dev, IDE_CS) & ~0x3; + enables |= (sb->ide0_enable << 1) | sb->ide1_enable; + pci_write_config8(dev, IDE_CS, enables); + enables = pci_read_config8(dev, IDE_CS); + printk(BIOS_DEBUG, "Enables in reg 0x40 read back as 0x%x\n", enables); + + /* Enable only compatibility mode. */ + enables = pci_read_config8(dev, 0x09); + enables &= 0xFA; + pci_write_config8(dev, 0x09, enables); + + enables = pci_read_config8(dev, IDE_CONF_II); + enables &= ~0xc0; + pci_write_config8(dev, IDE_CONF_II, enables); + enables = pci_read_config8(dev, IDE_CONF_II); + printk(BIOS_DEBUG, "Enables in reg 0x42 read back as 0x%x\n", enables); + + /* Enable prefetch buffers. */ + enables = pci_read_config8(dev, IDE_CONF_I); + enables |= 0xf0; + pci_write_config8(dev, IDE_CONF_I, enables); + + /* Flush FIFOs at half. */ + enables = pci_read_config8(dev, IDE_CONF_FIFO); + enables &= 0xf0; + enables |= (1 << 2) | (1 << 0); + pci_write_config8(dev, IDE_CONF_FIFO, enables); + + /* PIO read prefetch counter, Bus Master IDE Status Reg. Read Retry. */ + enables = pci_read_config8(dev, IDE_MISC_I); + enables &= 0xe2; + enables |= (1 << 4) | (1 << 3); + pci_write_config8(dev, IDE_MISC_I, enables); + + /* Use memory read multiple, Memory-Write-and-Invalidate. */ + enables = pci_read_config8(dev, IDE_MISC_II); + enables &= 0xEF; + enables |= (1 << 2) | (1 << 3); + pci_write_config8(dev, IDE_MISC_II, enables); + + /* Force interrupts to use compat mode. */ + pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0); + pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff); + + /* Cable guy... */ + cablesel = pci_read_config32(dev, IDE_UDMA); + cablesel &= ~VT8237R_IDE_CABLESEL_MASK; + cablesel |= vt8237_ide_80pin_detect(dev); + pci_write_config32(dev, IDE_UDMA, cablesel); + +#if CONFIG_EPIA_VT8237R_INIT + device_t lpc_dev; + + /* Set PATA Output Drive Strength */ + lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); + if (lpc_dev) + pci_write_config8(lpc_dev, 0x7C, 0x20); +#endif +} + +static const struct device_operations ide_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver northbridge_driver __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_82C586_1, +}; diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c new file mode 100644 index 0000000000..72b85b37d5 --- /dev/null +++ b/src/southbridge/via/vt8237r/lpc.c @@ -0,0 +1,624 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007, 2008 Rudolf Marek + * Copyright (C) 2009 Jon Harrison + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Inspiration from other VIA SB code. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "vt8237r.h" +#include "chip.h" + +static void southbridge_init_common(struct device *dev); + +#if CONFIG_EPIA_VT8237R_INIT + /* Interrupts for INT# A B C D */ +static const unsigned char pciIrqs[4] = { 10, 11, 12, 0}; + + /* Interrupt Assignments for Pins 1 2 3 4 */ +static const unsigned char sataPins[4] = { 'A','B','C','D'}; +static const unsigned char vgaPins[4] = { 'A','B','C','D'}; +static const unsigned char usbPins[4] = { 'A','B','C','D'}; +static const unsigned char enetPins[4] = { 'A','B','C','D'}; +static const unsigned char vt8237Pins[4] = { 'A','B','C','D'}; +static const unsigned char slotPins[4] = { 'C','D','A','B'}; +static const unsigned char riserPins[4] = { 'D','C','B','A'}; + +static unsigned char *pin_to_irq(const unsigned char *pin) +{ + static unsigned char Irqs[4]; + int i; + for (i = 0 ; i < 4 ; i++) + Irqs[i] = pciIrqs[ pin[i] - 'A' ]; + + return Irqs; +} +#endif + +/** Set up PCI IRQ routing, route everything through APIC. */ +static void pci_routing_fixup(struct device *dev) +{ +#if CONFIG_EPIA_VT8237R_INIT + device_t pdev; +#endif + + /* PCI PNP Interrupt Routing INTE/F - disable */ + pci_write_config8(dev, 0x44, 0x00); + + /* PCI PNP Interrupt Routing INTG/H - disable */ + pci_write_config8(dev, 0x45, 0x00); + + /* Gate Interrupts until RAM Writes are flushed */ + pci_write_config8(dev, 0x49, 0x20); + +#if CONFIG_EPIA_VT8237R_INIT + + /* Share INTE-INTH with INTA-INTD as per stock BIOS. */ + pci_write_config8(dev, 0x46, 0x00); + + /* setup PCI IRQ routing (For PCI Slot)*/ + pci_write_config8(dev, 0x55, pciIrqs[0] << 4); + pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4) ); + pci_write_config8(dev, 0x57, pciIrqs[3] << 4); + + /* PCI Routing Fixup */ + + //Setup MiniPCI Slot + pci_assign_irqs(0, 0x14, pin_to_irq(slotPins)); + + // Via 2 slot riser card 2nd slot + pci_assign_irqs(0, 0x13, pin_to_irq(riserPins)); + + //Setup USB + pci_assign_irqs(0, 0x10, pin_to_irq(usbPins)); + + //Setup VT8237R Sound + pci_assign_irqs(0, 0x11, pin_to_irq(vt8237Pins)); + + //Setup Ethernet + pci_assign_irqs(0, 0x12, pin_to_irq(enetPins)); + + //Setup VGA + pci_assign_irqs(1, 0x00, pin_to_irq(vgaPins)); + + /* APIC Routing Fixup */ + + // Setup SATA + pdev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT6420_SATA, 0); + pci_write_config8(pdev, PCI_INTERRUPT_PIN, 0x02); + pci_assign_irqs(0, 0x0f, pin_to_irq(sataPins)); + + + // Setup PATA Override + pdev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_82C586_1, 0); + pci_write_config8(pdev, PCI_INTERRUPT_PIN, 0x01); + pci_write_config8(pdev, PCI_INTERRUPT_LINE, 0xFF); + +#else + /* Route INTE-INTH through registers above, no map to INTA-INTD. */ + pci_write_config8(dev, 0x46, 0x10); + + /* PCI Interrupt Polarity */ + pci_write_config8(dev, 0x54, 0x00); + + /* PCI INTA# Routing */ + pci_write_config8(dev, 0x55, 0x00); + + /* PCI INTB#/C# Routing */ + pci_write_config8(dev, 0x56, 0x00); + + /* PCI INTD# Routing */ + pci_write_config8(dev, 0x57, 0x00); +#endif +} + + + +/** + * Set up the power management capabilities directly into ACPI mode. + * This avoids having to handle any System Management Interrupts (SMIs). + */ + +extern u8 acpi_slp_type; + + +static void setup_pm(device_t dev) +{ + u16 tmp; + /* Debounce LID and PWRBTN# Inputs for 16ms. */ + pci_write_config8(dev, 0x80, 0x20); + + /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ + pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); + + /* Set ACPI to 9, must set IRQ 9 override to level! Set PSON gating. */ + pci_write_config8(dev, 0x82, 0x40 | VT8237R_ACPI_IRQ); + +#if CONFIG_EPIA_VT8237R_INIT + /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */ + pci_write_config16(dev, 0x84, 0x3052); +#else + /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */ + pci_write_config16(dev, 0x84, 0x30b2); + +#endif + /* SMI output level to low, 7.5us throttle clock */ + pci_write_config8(dev, 0x8d, 0x18); + + /* GP Timer Control 1s */ + pci_write_config8(dev, 0x93, 0x88); + + /* + * 7 = SMBus clock from RTC 32.768KHz + * 5 = Internal PLL reset from susp disabled + * 2 = GPO2 is SUSA# + */ + pci_write_config8(dev, 0x94, 0xa0); + + /* + * 7 = stp to sust delay 1msec + * 6 = SUSST# Deasserted Before PWRGD for STD + * 5 = Keyboard/Mouse Swap + * 4 = PWRGOOD reset on VT8237A/S + * 3 = GPO26/GPO27 is GPO + * 2 = Disable Alert on Lan + * 1 = SUSCLK/GPO4 + * 0 = USB Wakeup + */ + +#if CONFIG_EPIA_VT8237R_INIT + pci_write_config8(dev, 0x95, 0xc2); +#else + pci_write_config8(dev, 0x95, 0xcc); +#endif + + /* Disable GP3 timer. */ + pci_write_config8(dev, 0x98, 0); + + /* Enable ACPI accessm RTC signal gated with PSON. */ + pci_write_config8(dev, 0x81, 0x84); + + /* Clear status events. */ + outw(0xffff, VT8237R_ACPI_IO_BASE + 0x00); + outw(0xffff, VT8237R_ACPI_IO_BASE + 0x20); + outw(0xffff, VT8237R_ACPI_IO_BASE + 0x28); + outl(0xffffffff, VT8237R_ACPI_IO_BASE + 0x30); + + /* Disable SCI on GPIO. */ + outw(0x0, VT8237R_ACPI_IO_BASE + 0x22); + + /* Disable SMI on GPIO. */ + outw(0x0, VT8237R_ACPI_IO_BASE + 0x24); + + /* Disable all global enable SMIs. */ + outw(0x0, VT8237R_ACPI_IO_BASE + 0x2a); + + /* All SMI off, both IDE buses ON, PSON rising edge. */ + outw(0x0, VT8237R_ACPI_IO_BASE + 0x2c); + + /* Primary activity SMI disable. */ + outl(0x0, VT8237R_ACPI_IO_BASE + 0x34); + + /* GP timer reload on none. */ + outl(0x0, VT8237R_ACPI_IO_BASE + 0x38); + + /* Disable extended IO traps. */ + outb(0x0, VT8237R_ACPI_IO_BASE + 0x42); + + /* SCI is generated for RTC/pwrBtn/slpBtn. */ + tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); +#if CONFIG_HAVE_ACPI_RESUME == 1 + acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; + printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type); +#endif + /* clear sleep */ + tmp &= ~(7 << 10); + tmp |= 1; + outw(tmp, VT8237R_ACPI_IO_BASE + 0x04); +} + +static void vt8237r_init(struct device *dev) +{ + u8 enables; + +#if CONFIG_EPIA_VT8237R_INIT + printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n"); + /* + * TODO: Looks like stock BIOS can do this but causes a hang + * Enable SATA LED, disable special CPU Frequency Change - + * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs. + * Setup to match EPIA default + * PCS0# on Pin U1 + */ + enables = pci_read_config8(dev, 0xe5); + enables |= 0x23; + pci_write_config8(dev, 0xe5, enables); + + /* + * Enable Flash Write Access. + * Note EPIA-N Does not use REQ5 or PCISTP#(Hang) + */ + enables = pci_read_config8(dev, 0xe4); + enables |= 0x2B; + pci_write_config8(dev, 0xe4, enables); + + /* Enables Extra RTC Ports */ + enables = pci_read_config8(dev, 0x4E); + enables |= 0x80; + pci_write_config8(dev, 0x4E, enables); + +#else + printk(BIOS_SPEW, "Entering vt8237r_init.\n"); + /* + * Enable SATA LED, disable special CPU Frequency Change - + * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs. + */ + pci_write_config8(dev, 0xe5, 0x09); + + /* REQ5 as PCI request input - should be together with INTE-INTH. */ + pci_write_config8(dev, 0xe4, 0x4); +#endif + + /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ + enables = pci_read_config8(dev, 0x4f); + enables |= 0x08; + pci_write_config8(dev, 0x4f, enables); + +#if CONFIG_EPIA_VT8237R_INIT + /* + * Set Read Pass Write Control Enable + */ + pci_write_config8(dev, 0x48, 0x0c); +#else + /* + * Set Read Pass Write Control Enable + * (force A2 from APIC FSB to low). + */ + pci_write_config8(dev, 0x48, 0x8c); +#endif + + southbridge_init_common(dev); + +#if !CONFIG_EPIA_VT8237R_INIT + /* FIXME: Intel needs more bit set for C2/C3. */ + + /* + * Allow SLP# signal to assert LDTSTOP_L. + * Will work for C3 and for FID/VID change. + */ + outb(0x1, VT8237R_ACPI_IO_BASE + 0x11); +#endif + + printk(BIOS_SPEW, "Leaving %s.\n", __func__); +} + +static void vt8237a_init(struct device *dev) +{ + /* + * FIXME: This is based on vt8237s_init() and the values the AMI + * BIOS on my M2V wrote to these registers (by loking + * at lspci -nxxx output). + * Works for me. + */ + u32 tmp; + + /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ + tmp = pci_read_config8(dev, 0x4f); + tmp |= 0x08; + pci_write_config8(dev, 0x4f, tmp); + + /* + * bit2: REQ5 as PCI request input - should be together with INTE-INTH. + * bit5: usb power control lines as gpio + */ + pci_write_config8(dev, 0xe4, 0x24); + /* + * Enable APIC wakeup from INTH + * Enable SATA LED, disable special CPU Frequency Change - + * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs. + */ + pci_write_config8(dev, 0xe5, 0x69); + + /* Reduce further the STPCLK/LDTSTP signal to 5us. */ + pci_write_config8(dev, 0xec, 0x4); + + /* Host Bus Power Management Control, maybe not needed */ + pci_write_config8(dev, 0x8c, 0x5); + + /* Enable HPET at VT8237R_HPET_ADDR. */ + pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80)); + + southbridge_init_common(dev); + + /* Share INTE-INTH with INTA-INTD for simplicity */ + pci_write_config8(dev, 0x46, 0x00); + + /* FIXME: Intel needs more bit set for C2/C3. */ + + /* + * Allow SLP# signal to assert LDTSTOP_L. + * Will work for C3 and for FID/VID change. + */ + outb(0x1, VT8237R_ACPI_IO_BASE + 0x11); + + dump_south(dev); +} + +static void vt8237s_init(struct device *dev) +{ + u32 tmp; + + /* Put SPI base VT8237S_SPI_MEM_BASE. */ + tmp = pci_read_config32(dev, 0xbc); + pci_write_config32(dev, 0xbc, + (VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000)); + + /* + * REQ5 as PCI request input - should be together with INTE-INTH. + */ + pci_write_config8(dev, 0xe4, 0x04); + + /* Reduce further the STPCLK/LDTSTP signal to 5us. */ + pci_write_config8(dev, 0xec, 0x4); + + /* Host Bus Power Management Control, maybe not needed */ + pci_write_config8(dev, 0x8c, 0x5); + + /* Enable HPET at VT8237R_HPET_ADDR., does not work correctly on R. */ + pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80)); + + southbridge_init_common(dev); + + /* FIXME: Intel needs more bit set for C2/C3. */ + + /* + * Allow SLP# signal to assert LDTSTOP_L. + * Will work for C3 and for FID/VID change. FIXME FIXME, pre rev A2. + */ + outb(0xff, VT8237R_ACPI_IO_BASE + 0x50); + + dump_south(dev); +} + +static void vt8237_common_init(struct device *dev) +{ + u8 enables, byte; + + /* Enable addr/data stepping. */ + byte = pci_read_config8(dev, PCI_COMMAND); + byte |= PCI_COMMAND_WAIT; + pci_write_config8(dev, PCI_COMMAND, byte); + +/* EPIA-N(L) Uses CN400 for BIOS Access */ +#if !CONFIG_EPIA_VT8237R_INIT + /* Enable the internal I/O decode. */ + enables = pci_read_config8(dev, 0x6C); + enables |= 0x80; + pci_write_config8(dev, 0x6C, enables); + + /* + * ROM decode + * bit range + * 7 000E0000h-000EFFFFh + * 6 FFF00000h-FFF7FFFFh + * 5 FFE80000h-FFEFFFFFh + * 4 FFE00000h-FFE7FFFFh + * 3 FFD80000h-FFDFFFFFh + * 2 FFD00000h-FFD7FFFFh + * 1 FFC80000h-FFCFFFFFh + * 0 FFC00000h-FFC7FFFFh + * So 0x7f here sets ROM decode to FFC00000-FFFFFFFF or 4Mbyte. + */ + pci_write_config8(dev, 0x41, 0x7f); +#endif + + /* + * Set bit 6 of 0x40 (I/O recovery time). + * IMPORTANT FIX - EISA = ECLR reg at 0x4d0! Decoding must be on so + * that PCI interrupts can be properly marked as level triggered. + */ + enables = pci_read_config8(dev, 0x40); + enables |= 0x44; + pci_write_config8(dev, 0x40, enables); + + /* Line buffer control */ + enables = pci_read_config8(dev, 0x42); + enables |= 0xf8; + pci_write_config8(dev, 0x42, enables); + + /* Delay transaction control */ + pci_write_config8(dev, 0x43, 0xb); + +#if CONFIG_EPIA_VT8237R_INIT + /* I/O recovery time, default IDE routing */ + pci_write_config8(dev, 0x4c, 0x04); + + /* ROM memory cycles go to LPC. */ + pci_write_config8(dev, 0x59, 0x80); + + /* + * Bit | Meaning + * ------------- + * 3 | Bypass APIC De-Assert Message (1=Enable) + * 1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI" + * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch + * 0 | Dynamic Clock Gating Main Switch (1=Enable) + */ + pci_write_config8(dev, 0x5b, 0x9); + + /* Set 0x58 to 0x42 APIC On and RTC Write Protect.*/ + pci_write_config8(dev, 0x58, 0x42); + + /* Enable serial IRQ, 6PCI clocks. */ + pci_write_config8(dev, 0x52, 0x9); +#else + /* I/O recovery time, default IDE routing */ + pci_write_config8(dev, 0x4c, 0x44); + + /* ROM memory cycles go to LPC. */ + pci_write_config8(dev, 0x59, 0x80); + + /* + * Bit | Meaning + * ------------- + * 3 | Bypass APIC De-Assert Message (1=Enable) + * 1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI" + * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch + * 0 | Dynamic Clock Gating Main Switch (1=Enable) + */ + pci_write_config8(dev, 0x5b, 0xb); + + /* Set 0x58 to 0x43 APIC and RTC. */ + pci_write_config8(dev, 0x58, 0x43); + + /* Enable serial IRQ, 6PCI clocks. */ + pci_write_config8(dev, 0x52, 0x9); + +#endif + + /* Power management setup */ + setup_pm(dev); + + /* Start the RTC. */ + rtc_init(0); +} + +static void vt8237r_read_resources(device_t dev) +{ + struct resource *res; + + pci_dev_read_resources(dev); + + /* Fixed ACPI Base IO Base*/ + res = new_resource(dev, 0x88); + res->base = VT8237R_ACPI_IO_BASE; + res->size = 128; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* Fixed EISA ECLR I/O Regs */ + res = new_resource(dev, 3); + res->base = 0x4d0; + res->size = 2; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* Fixed System Management Bus I/O Resource */ + res = new_resource(dev, 0xD0); + res->base = VT8237R_SMBUS_IO_BASE; + res->size = 16; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* Fixed APIC resource */ + res = new_resource(dev, 0x44); + res->base = IO_APIC_ADDR; + res->size = 256; + res->limit = 0xffffffffUL; + res->align = 8; + res->gran = 8; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* Fixed flashrom resource */ + res = new_resource(dev, 4); + res->base = 0xff000000UL; + res->size = 0x01000000UL; /* 16MB */ + res->limit = 0xffffffffUL; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x1000UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void init_keyboard(struct device *dev) +{ + u8 regval = pci_read_config8(dev, 0x51); + if (regval & 0x1) + pc_keyboard_init(0); +} + +static void southbridge_init_common(struct device *dev) +{ + vt8237_common_init(dev); + pci_routing_fixup(dev); + setup_ioapic(IO_APIC_ADDR, VT8237R_APIC_ID); + setup_i8259(); + init_keyboard(dev); +} + +static const struct device_operations vt8237r_lpc_ops_s = { + .read_resources = vt8237r_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = vt8237s_init, + .scan_bus = scan_static_bus, +}; + +static const struct device_operations vt8237r_lpc_ops_r = { + .read_resources = vt8237r_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = vt8237r_init, + .scan_bus = scan_static_bus, +}; + +static const struct device_operations vt8237r_lpc_ops_a = { + .read_resources = vt8237r_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = vt8237a_init, + .scan_bus = scan_static_bus, +}; + +static const struct pci_driver lpc_driver_r __pci_driver = { + .ops = &vt8237r_lpc_ops_r, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT8237R_LPC, +}; + +static const struct pci_driver lpc_driver_a __pci_driver = { + .ops = &vt8237r_lpc_ops_a, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT8237A_LPC, +}; + +static const struct pci_driver lpc_driver_s __pci_driver = { + .ops = &vt8237r_lpc_ops_s, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT8237S_LPC, +}; diff --git a/src/southbridge/via/vt8237r/nic.c b/src/southbridge/via/vt8237r/nic.c new file mode 100644 index 0000000000..6771895916 --- /dev/null +++ b/src/southbridge/via/vt8237r/nic.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007, 2008 Rudolf Marek + * Copyright (C) 2009 Jon Harrison + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "vt8237r.h" + + +static void vt8237_eth_read_resources(struct device *dev) +{ +#if CONFIG_EPIA_VT8237R_INIT + struct resource *res; + + /* Fix the I/O Resources of the USB2.0 Interface */ + res = new_resource(dev, PCI_BASE_ADDRESS_0); + res->base = 0xF6001000ULL; + res->size = 256; + res->align = 12; + res->gran = 8; + res->limit = res->base + res->size - 1; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_ASSIGNED; +#else + pci_dev_read_resources(dev); +#endif + return; +} + + +static const struct device_operations vt8237_eth_ops = { + .read_resources = vt8237_eth_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver vt8237r_driver_eth __pci_driver = { + .ops = &vt8237_eth_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_8233_7, +}; diff --git a/src/southbridge/via/vt8237r/pirq.c b/src/southbridge/via/vt8237r/pirq.c new file mode 100644 index 0000000000..9915da4835 --- /dev/null +++ b/src/southbridge/via/vt8237r/pirq.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Nikolay Petukhov + * Copyright (C) 2010 Tobias Diedrich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include + +#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_GENERATE_PIRQ_TABLE==1) +void pirq_assign_irqs(const unsigned char route[4]) +{ + device_t pdev; + + pdev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); + if (!pdev) + pdev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237S_LPC, 0); + if (!pdev) + pdev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237A_LPC, 0); + if (!pdev) + return; + + pci_write_config8(pdev, 0x55, route[0] << 4); + pci_write_config8(pdev, 0x56, (route[2] << 4) | route[1]); + pci_write_config8(pdev, 0x57, route[3] << 4); + + /* Enable INT[E-H] mapped to INT[A-D] for simplicity */ + pci_write_config8(pdev, 0x46, 0x00); +} +#endif diff --git a/src/southbridge/via/vt8237r/sata.c b/src/southbridge/via/vt8237r/sata.c new file mode 100644 index 0000000000..777d605a6b --- /dev/null +++ b/src/southbridge/via/vt8237r/sata.c @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007, 2008 Rudolf Marek + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include + +#define SATA_MISC_CTRL 0x45 + +static void sata_i_init(struct device *dev) +{ + u8 reg; + + printk(BIOS_DEBUG, "Configuring VIA SATA controller\n"); + + /* Class IDE Disk */ + reg = pci_read_config8(dev, SATA_MISC_CTRL); + reg &= 0x7f; /* Sub Class Write Protect off */ + pci_write_config8(dev, SATA_MISC_CTRL, reg); + + /* Change the device class to SATA from RAID. */ + pci_write_config8(dev, PCI_CLASS_DEVICE, 0x1); + reg |= 0x80; /* Sub Class Write Protect on */ + pci_write_config8(dev, SATA_MISC_CTRL, reg); + + return; +} + +static void sata_ii_init(struct device *dev) +{ + u8 reg; + + sata_i_init(dev); + + /* + * Analog black magic, you may or may not need to adjust 0x60-0x6f, + * depends on PCB. + */ + + /* + * Analog PHY - gen1 + * CDR bandwidth [6:5] = 3 + * Squelch Window Select [4:3] = 1 + * CDR Charge Pump [2:0] = 1 + */ + + pci_write_config8(dev, 0x64, 0x49); + + /* Adjust driver current source value to 9. */ + reg = pci_read_config8(dev, 0x65); + reg &= 0xf0; + reg |= 0x9; + pci_write_config8(dev, 0x65, reg); + + /* Set all manual termination 50ohm bits [2:0] and enable [4]. */ + reg = pci_read_config8(dev, 0x6a); + reg |= 0xf; + pci_write_config8(dev, 0x6a, reg); + + /* + * Analog PHY - gen2 + * CDR bandwidth [5:4] = 2 + * Pre / De-emphasis Level [7:6] controls bits [3:2], rest in 0x6e + * CDR Charge Pump [2:0] = 1 + */ + + reg = pci_read_config8(dev, 0x6f); + reg &= 0x08; + reg |= 0x61; + pci_write_config8(dev, 0x6f, reg); + + /* Check if staggered spinup is supported. */ + reg = pci_read_config8(dev, 0x83); + if ((reg & 0x8) == 0) { + /* Start OOB sequence on both drives. */ + reg |= 0x30; + pci_write_config8(dev, 0x83, reg); + } +} + +static const struct device_operations sata_i_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sata_i_init, + .enable = 0, + .ops_pci = 0, +}; + +static const struct device_operations sata_ii_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sata_ii_init, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver northbridge_driver_ii __pci_driver = { + .ops = &sata_ii_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT8237_SATA, +}; + +static const struct pci_driver northbridge_driver_i_a __pci_driver = { + .ops = &sata_i_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT8237A_SATA, +}; + +static const struct pci_driver northbridge_driver_i __pci_driver = { + .ops = &sata_i_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT6420_SATA, +}; diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c new file mode 100644 index 0000000000..6e8d9e5dd0 --- /dev/null +++ b/src/southbridge/via/vt8237r/usb.c @@ -0,0 +1,165 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007, 2008 Rudolf Marek + * Copyright (C) 2009 Jon Harrison + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "vt8237r.h" + +#if CONFIG_EPIA_VT8237R_INIT +u32 usb_io_addr[4] = {0xcc00, 0xd000, 0xd400, 0xd800}; +#endif + +static void usb_i_init(struct device *dev) +{ +#if CONFIG_EPIA_VT8237R_INIT + u8 reg8; + + printk(BIOS_DEBUG, "Entering %s\n", __func__); + + reg8 = pci_read_config8(dev, 0x04); + + printk(BIOS_SPEW, "%s Read %02X from PCI Command Reg\n", dev_path(dev), reg8); + + reg8 = reg8 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config8(dev, 0x04, reg8); + + printk(BIOS_SPEW, "%s Wrote %02X to PCI Command Reg\n", dev_path(dev), reg8); + + /* Set Cache Line Size and Latency Timer */ + pci_write_config8(dev, 0x0c, 0x08); + pci_write_config8(dev, 0x0d, 0x20); + + /* Enable Sub Device ID Back Door and set Generic */ + reg8 = pci_read_config8(dev, 0x42); + reg8 |= 0x10; + pci_write_config8(dev, 0x42, reg8); + pci_write_config16(dev, 0x2e, 0xAA07); + reg8 &= ~0x10; + pci_write_config8(dev, 0x42, reg8); + + + pci_write_config8(dev, 0x41, 0x12); + + pci_write_config8(dev, 0x49, 0x0B); + + /* Clear PCI Status */ + pci_write_config16(dev, 0x06, 0x7A10); +#endif + return; +} + +static void vt8237_usb_i_read_resources(struct device *dev) +{ +#if CONFIG_EPIA_VT8237R_INIT + struct resource *res; + u8 function = (u8) dev->path.pci.devfn & 0x7; + + printk(BIOS_SPEW, "VT8237R Fixing USB 1.1 fn %d I/O resource = 0x%04X\n", function, usb_io_addr[function]); + + /* Fix the I/O Resources of the USB1.1 Interfaces */ + /* Auto PCI probe seems to size the resources */ + /* Incorrectly */ + res = new_resource(dev, PCI_BASE_ADDRESS_4); + res->base = usb_io_addr[function]; + res->size = 256; + res->limit = 0xffffUL; + res->align = 10; + res->gran = 8; + res->flags = IORESOURCE_IO | IORESOURCE_FIXED | + IORESOURCE_ASSIGNED; +#else + pci_dev_read_resources(dev); +#endif + return; +} + +static void usb_ii_init(struct device *dev) +{ +#if CONFIG_EPIA_VT8237R_INIT + u8 reg8; + + printk(BIOS_DEBUG, "Entering %s\n", __func__); + + /* Set memory Write and Invalidate */ + reg8 = pci_read_config8(dev, 0x04); + reg8 |= 0x10; + pci_write_config8(dev, 0x04, reg8); + + /* Set Cache line Size and Latency Timer */ + pci_write_config8(dev, 0x0c, 0x08); + pci_write_config8(dev, 0x0d, 0x20); + + /* Clear PCI Status */ + pci_write_config16(dev, 0x06, 0x7A10); +#endif + +} + +static void vt8237_usb_ii_read_resources(struct device *dev) +{ +#if CONFIG_EPIA_VT8237R_INIT + struct resource *res; + + /* Fix the I/O Resources of the USB2.0 Interface */ + res = new_resource(dev, PCI_BASE_ADDRESS_0); + res->base = 0xF6000000ULL; + res->size = 256; + res->align = 12; + res->gran = 8; + res->limit = res->base + res->size - 1; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_ASSIGNED; +#else + pci_dev_read_resources(dev); +#endif + return; +} + +static const struct device_operations usb_i_ops = { + .read_resources = vt8237_usb_i_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb_i_init, + .enable = 0, + .ops_pci = 0, +}; + +static const struct device_operations usb_ii_ops = { + .read_resources = vt8237_usb_ii_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb_ii_init, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver vt8237r_driver_usbii __pci_driver = { + .ops = &usb_ii_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT8237R_EHCI, +}; + +static const struct pci_driver vt8237r_driver_usbi __pci_driver = { + .ops = &usb_i_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT8237R_UHCI, +}; diff --git a/src/southbridge/via/vt8237r/vt8237_ctrl.c b/src/southbridge/via/vt8237r/vt8237_ctrl.c deleted file mode 100644 index f3cc30ed88..0000000000 --- a/src/southbridge/via/vt8237r/vt8237_ctrl.c +++ /dev/null @@ -1,289 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Rudolf Marek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include "vt8237r.h" - -/* We support here K8M890/K8T890 and VT8237/S/A PCI1/Vlink */ - -static void vt8237_cfg(struct device *dev) -{ - u8 regm, regm3; - device_t devfun3; - - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_3, 0); - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M890CE_3, 0); - if (!devfun3) - devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CF_3, 0); - if (!devfun3) - die("Unknown NB"); - - /* CPU to PCI Flow Control 1 & 2, just fill in recommended. */ - pci_write_config8(dev, 0x70, 0xc2); - pci_write_config8(dev, 0x71, 0xc8); - - /* PCI Control */ - pci_write_config8(dev, 0x72, 0xee); - pci_write_config8(dev, 0x73, 0x01); - pci_write_config8(dev, 0x74, 0x3c); - pci_write_config8(dev, 0x75, 0x0f); - pci_write_config8(dev, 0x76, 0x50); - pci_write_config8(dev, 0x77, 0x48); - pci_write_config8(dev, 0x78, 0x01); - /* APIC on HT */ - /* Maybe Enable LDT APIC Mode bit3 set to 1 */ - pci_write_config8(dev, 0x7c, 0x77); - - /* WARNING: Need to copy some registers from NB (D0F3) to SB (D11F7). */ - - regm = pci_read_config8(devfun3, 0x88); /* Shadow mem CTRL */ - pci_write_config8(dev, 0x57, regm); - - regm = pci_read_config8(devfun3, 0x80); /* Shadow page C */ - pci_write_config8(dev, 0x61, regm); - - regm = pci_read_config8(devfun3, 0x81); /* Shadow page D */ - pci_write_config8(dev, 0x62, regm); - - /* Shadow page F + memhole copy */ - regm = pci_read_config8(devfun3, 0x83); - pci_write_config8(dev, 0x63, regm); - - // FIXME is this really supposed to be regm3? - regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */ - pci_write_config8(dev, 0x64, regm); - - regm = pci_read_config8(devfun3, 0x86); /* SMM and APIC decoding */ - pci_write_config8(dev, 0xe6, regm); -} - -/** - * Example of setup: Setup the V-Link for VT8237R, 8X mode. - * - * For K8T890CF VIA recommends what is in VIA column, AW is award 8X: - * - * REG DEF AW VIA-8X VIA-4X - * ----------------------------- - * NB V-Link Manual Driving Control strobe 0xb5 0x46 0x46 0x88 0x88 - * NB V-Link Manual Driving Control - Data 0xb6 0x46 0x46 0x88 0x88 - * NB V-Link Receiving Strobe Delay 0xb7 0x02 0x02 0x61 0x01 - * NB V-Link Compensation Control bit4,0 (b5,b6) 0xb4 0x10 0x10 0x11 0x11 - * SB V-Link Strobe Drive Control 0xb9 0x00 0xa5 0x98 0x98 - * SB V-Link Data drive Control???? 0xba 0x00 0xbb 0x77 0x77 - * SB V-Link Receive Strobe Delay???? 0xbb 0x04 0x11 0x11 0x11 - * SB V-Link Compensation Control bit0 (use b9) 0xb8 0x00 0x01 0x01 0x01 - * V-Link CKG Control 0xb0 0x05 0x05 0x06 0x03 - * V-Link CKG Control 0xb1 0x05 0x05 0x01 0x03 - */ - -/* we setup 533MB/s mode full duplex */ - -static void vt8237s_vlink_init(struct device *dev) -{ - u8 reg; - device_t devfun7; - - devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_7, 0); - if (!devfun7) - devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M890CE_7, 0); - if (!devfun7) - devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CF_7, 0); - /* No pairing NB was found. */ - if (!devfun7) - return; - - /* - * This init code is valid only for the VT8237S! For different - * sounthbridges (e.g. VT8237A, VT8237S, VT8237R (without plus R) - * and VT8251) a different init code is required. - */ - - /* disable auto disconnect */ - reg = pci_read_config8(devfun7, 0x42); - reg &= ~0x4; - pci_write_config8(devfun7, 0x42, reg); - - /* NB part setup */ - pci_write_config8(devfun7, 0xb5, 0x66); - pci_write_config8(devfun7, 0xb6, 0x66); - pci_write_config8(devfun7, 0xb7, 0x64); - - reg = pci_read_config8(devfun7, 0xb4); - reg |= 0x1; - reg &= ~0x10; - pci_write_config8(devfun7, 0xb4, reg); - - pci_write_config8(devfun7, 0xb0, 0x6); - pci_write_config8(devfun7, 0xb1, 0x1); - - /* SB part setup */ - pci_write_config8(dev, 0xb7, 0x60); - pci_write_config8(dev, 0xb9, 0x88); - pci_write_config8(dev, 0xba, 0x88); - pci_write_config8(dev, 0xbb, 0x89); - - reg = pci_read_config8(dev, 0xbd); - reg |= 0x3; - reg &= ~0x4; - pci_write_config8(dev, 0xbd, reg); - - reg = pci_read_config8(dev, 0xbc); - reg &= ~0x7; - pci_write_config8(dev, 0xbc, reg); - - /* Program V-link 8X 8bit full duplex, parity enabled. */ - pci_write_config8(dev, 0x48, 0x23 | 0x80); - - /* enable auto disconnect, for STPGNT and HALT */ - reg = pci_read_config8(devfun7, 0x42); - reg |= 0x7; - pci_write_config8(devfun7, 0x42, reg); - -} - -static void vt8237a_vlink_init(struct device *dev) -{ - u8 reg; - device_t devfun7; - - devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_7, 0); - if (!devfun7) - devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M890CE_7, 0); - if (!devfun7) - devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CF_7, 0); - /* No pairing NB was found. */ - if (!devfun7) - return; - - /* - * This init code is valid only for the VT8237A! For different - * sounthbridges (e.g. VT8237S, VT8237R and VT8251) a different - * init code is required. - * - * FIXME: This is based on vt8237r_vlink_init() in - * k8t890/k8t890_ctrl.c and modified to fit what the AMI - * BIOS on my M2V wrote to these registers (by looking - * at lspci -nxxx output). - * Works for me. - */ - - /* disable auto disconnect */ - reg = pci_read_config8(devfun7, 0x42); - reg &= ~0x4; - pci_write_config8(devfun7, 0x42, reg); - - /* NB part setup */ - pci_write_config8(devfun7, 0xb5, 0x88); - pci_write_config8(devfun7, 0xb6, 0x88); - pci_write_config8(devfun7, 0xb7, 0x61); - - reg = pci_read_config8(devfun7, 0xb4); - reg |= 0x11; - pci_write_config8(devfun7, 0xb4, reg); - - pci_write_config8(devfun7, 0xb0, 0x6); - pci_write_config8(devfun7, 0xb1, 0x1); - - /* SB part setup */ - pci_write_config8(dev, 0xb7, 0x50); - pci_write_config8(dev, 0xb9, 0x88); - pci_write_config8(dev, 0xba, 0x8a); - pci_write_config8(dev, 0xbb, 0x88); - - reg = pci_read_config8(dev, 0xbd); - reg |= 0x3; - reg &= ~0x4; - pci_write_config8(dev, 0xbd, reg); - - reg = pci_read_config8(dev, 0xbc); - reg &= ~0x7; - pci_write_config8(dev, 0xbc, reg); - - pci_write_config8(dev, 0x48, 0x23); - - /* enable auto disconnect, for STPGNT and HALT */ - reg = pci_read_config8(devfun7, 0x42); - reg |= 0x7; - pci_write_config8(devfun7, 0x42, reg); -} - -static void ctrl_enable(struct device *dev) -{ - /* Enable the 0:13 and 0:13.1. */ - /* FIXME */ - pci_write_config8(dev, 0x4f, 0x43); -} - -static void ctrl_init(struct device *dev) -{ - /* - * TODO: Fix some ordering issue for V-link set Rx77[6] and - * PCI1_Rx4F[0] should to 1. - * FIXME DO you need? - */ - - /* - * VT8237R specific configuration. Other SB are done in their own - * directories. TODO: Add A version. - */ - device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237S_LPC, 0); - if (devsb) { - vt8237s_vlink_init(dev); - } - - devsb = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237A_LPC, 0); - if (devsb) { - vt8237a_vlink_init(dev); - } - - /* Configure PCI1 and copy mirror registers from D0F3. */ - vt8237_cfg(dev); - dump_south(dev); -} - -static const struct device_operations ctrl_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ctrl_init, - .enable = ctrl_enable, - .ops_pci = 0, -}; - -static const struct pci_driver northbridge_driver_t __pci_driver = { - .ops = &ctrl_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT8237_VLINK, -}; diff --git a/src/southbridge/via/vt8237r/vt8237_fadt.c b/src/southbridge/via/vt8237r/vt8237_fadt.c deleted file mode 100644 index 6976f4d447..0000000000 --- a/src/southbridge/via/vt8237r/vt8237_fadt.c +++ /dev/null @@ -1,173 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Nick Barker - * Copyright (C) 2007, 2009 Rudolf Marek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include -#include "vt8237r.h" - -/** - * Create the Fixed ACPI Description Tables (FADT) for any board with this SB. - */ -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - device_t dev; - int is_vt8237s = 0; - - /* Power management controller */ - dev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237S_LPC, 0); - - if (dev) - is_vt8237s = 1; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = 244; - header->revision = 4; - memcpy(header->oem_id, "COREBO", 6); - memcpy(header->oem_table_id, "COREBOOT", 8); - memcpy(header->asl_compiler_id, "CORE", 4); - header->asl_compiler_revision = 42; - - fadt->firmware_ctrl = (u32)facs; - fadt->dsdt = (u32)dsdt; - fadt->preferred_pm_profile = 0; - fadt->sci_int = 9; - fadt->smi_cmd = 0; - fadt->acpi_enable = 0; - fadt->acpi_disable = 0; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0x0; - - fadt->pm1a_evt_blk = VT8237R_ACPI_IO_BASE; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = VT8237R_ACPI_IO_BASE + 0x4; - fadt->pm1b_cnt_blk = 0x0; - /* once we support C2/C3 this could be set to 0x22 and chipset needs to be adjusted too */ - fadt->pm2_cnt_blk = 0x0; - fadt->pm_tmr_blk = VT8237R_ACPI_IO_BASE + 0x8; - fadt->gpe0_blk = VT8237R_ACPI_IO_BASE + 0x20; - if (is_vt8237s) { - fadt->gpe1_blk = VT8237R_ACPI_IO_BASE + 0x60; - fadt->gpe1_base = 0x10; - fadt->gpe1_blk_len = 4; - } else { - fadt->gpe1_blk = 0x0; - fadt->gpe1_base = 0; - fadt->gpe1_blk_len = 0; - } - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 0; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 4; - - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 90; - fadt->p_lvl3_lat = 900; - fadt->flush_size = 0; - fadt->flush_stride = 0; - fadt->duty_offset = 0; - fadt->duty_width = 1; //?? - fadt->day_alrm = 0x7d; - fadt->mon_alrm = 0x7e; - fadt->century = 0x32; - /* We have legacy devices, 8042, VGA is ok to probe, MSI are not supported */ - fadt->iapc_boot_arch = 0xb; - /* check me */ - fadt->flags = 0xa5; - - fadt->reset_reg.space_id = 0; - fadt->reset_reg.bit_width = 0; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0x0; - fadt->reset_reg.addrh = 0x0; - - fadt->reset_value = 0; - fadt->x_firmware_ctl_l = (u32)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); -} diff --git a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c deleted file mode 100644 index a298e84676..0000000000 --- a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c +++ /dev/null @@ -1,498 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood - * Copyright (C) 2007 Rudolf Marek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include "vt8237r.h" - -/** - * Print an error, should it occur. If no error, just exit. - * - * @param host_status The data returned on the host status register after - * a transaction is processed. - * @param loops The number of times a transaction was attempted. - */ -static void smbus_print_error(u8 host_status, int loops) -{ - /* Check if there actually was an error. */ - if ((host_status == 0x00 || host_status == 0x40 || - host_status == 0x42) && (loops < SMBUS_TIMEOUT)) - return; - - if (loops >= SMBUS_TIMEOUT) - print_err("SMBus timeout\n"); - if (host_status & (1 << 4)) - print_err("Interrupt/SMI# was Failed Bus Transaction\n"); - if (host_status & (1 << 3)) - print_err("Bus error\n"); - if (host_status & (1 << 2)) - print_err("Device error\n"); - if (host_status & (1 << 1)) - print_debug("Interrupt/SMI# completed successfully\n"); - if (host_status & (1 << 0)) - print_err("Host busy\n"); -} - -/** - * Wait for the SMBus to become ready to process the next transaction. - */ -static void smbus_wait_until_ready(void) -{ - int loops; - - PRINT_DEBUG("Waiting until SMBus ready\n"); - - /* Loop up to SMBUS_TIMEOUT times, waiting for bit 0 of the - * SMBus Host Status register to go to 0, indicating the operation - * was completed successfully. I don't remember why I did it this way, - * but I think it was because ROMCC was running low on registers */ - loops = 0; - while ((inb(SMBHSTSTAT) & 1) == 1 && loops < SMBUS_TIMEOUT) - ++loops; - - smbus_print_error(inb(SMBHSTSTAT), loops); -} - -/** - * Reset and take ownership of the SMBus. - */ -static void smbus_reset(void) -{ - outb(HOST_RESET, SMBHSTSTAT); - - /* Datasheet says we have to read it to take ownership of SMBus. */ - inb(SMBHSTSTAT); - - PRINT_DEBUG("After reset status: "); - PRINT_DEBUG_HEX16(inb(SMBHSTSTAT)); - PRINT_DEBUG("\n"); -} - -/** - * Read a byte from the SMBus. - * - * @param dimm The address location of the DIMM on the SMBus. - * @param offset The offset the data is located at. - */ -u8 smbus_read_byte(u8 dimm, u8 offset) -{ - u8 val; - - PRINT_DEBUG("DIMM "); - PRINT_DEBUG_HEX16(dimm); - PRINT_DEBUG(" OFFSET "); - PRINT_DEBUG_HEX16(offset); - PRINT_DEBUG("\n"); - - smbus_reset(); - - /* Clear host data port. */ - outb(0x00, SMBHSTDAT0); - SMBUS_DELAY(); - smbus_wait_until_ready(); - - /* Actual addr to reg format. */ - dimm = (dimm << 1); - dimm |= 1; - outb(dimm, SMBXMITADD); - outb(offset, SMBHSTCMD); - - /* Start transaction, byte data read. */ - outb(0x48, SMBHSTCTL); - SMBUS_DELAY(); - smbus_wait_until_ready(); - - val = inb(SMBHSTDAT0); - PRINT_DEBUG("Read: "); - PRINT_DEBUG_HEX16(val); - PRINT_DEBUG("\n"); - - /* Probably don't have to do this, but it can't hurt. */ - smbus_reset(); - - return val; -} - -#define PSONREADY_TIMEOUT 0x7fffffff - -static device_t get_vt8237_lpc(void) -{ - device_t dev; - - /* Power management controller */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); - if (dev != PCI_DEV_INVALID) - return dev; - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); - if (dev != PCI_DEV_INVALID) - return dev; - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237A_LPC), 0); - return dev; -} - -/** - * Enable the SMBus on VT8237R-based systems. - */ -void enable_smbus(void) -{ - device_t dev; - int loops; - - /* Power management controller */ - dev = get_vt8237_lpc(); - if (dev == PCI_DEV_INVALID) - die("Power management controller not found\n"); - - /* Make sure the RTC power well is up before touching smbus. */ - loops = 0; - while (!(pci_read_config8(dev, VT8237R_PSON) & (1<<6)) - && loops < PSONREADY_TIMEOUT) - ++loops; - - /* - * 7 = SMBus Clock from RTC 32.768KHz - * 5 = Internal PLL reset from susp - */ - pci_write_config8(dev, VT8237R_POWER_WELL, 0xa0); - - /* Enable SMBus. */ - pci_write_config16(dev, VT8237R_SMBUS_IO_BASE_REG, - VT8237R_SMBUS_IO_BASE | 0x1); - - /* SMBus Host Configuration, enable. */ - pci_write_config8(dev, VT8237R_SMBUS_HOST_CONF, 0x01); - - /* Make it work for I/O. */ - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - - smbus_reset(); - - /* Reset the internal pointer. */ - inb(SMBHSTCTL); -} - -/** - * A fixup for some systems that need time for the SMBus to "warm up". This is - * needed on some VT823x based systems, where the SMBus spurts out bad data for - * a short time after power on. This has been seen on the VIA Epia series and - * Jetway J7F2-series. It reads the ID byte from SMBus, looking for - * known-good data from a slot/address. Exits on either good data or a timeout. - * - * TODO: This should probably go into some global file, but one would need to - * be created just for it. If some other chip needs/wants it, we can - * worry about it then. - * - * @param ctrl The memory controller and SMBus addresses. - */ -void smbus_fixup(const struct mem_controller *ctrl) -{ - int i, ram_slots, current_slot = 0; - u8 result = 0; - - ram_slots = ARRAY_SIZE(ctrl->channel0); - if (!ram_slots) { - print_err("smbus_fixup() thinks there are no RAM slots!\n"); - return; - } - - PRINT_DEBUG("Waiting for SMBus to warm up"); - - /* - * Bad SPD data should be either 0 or 0xff, but YMMV. So we look for - * the ID bytes of SDRAM, DDR, DDR2, and DDR3 (and anything in between). - * VT8237R has only been seen on DDR and DDR2 based systems, so far. - */ - for (i = 0; (i < SMBUS_TIMEOUT && ((result < SPD_MEMORY_TYPE_SDRAM) || - (result > SPD_MEMORY_TYPE_SDRAM_DDR3))); i++) { - - if (current_slot > ram_slots) - current_slot = 0; - - result = smbus_read_byte(ctrl->channel0[current_slot], - SPD_MEMORY_TYPE); - current_slot++; - PRINT_DEBUG("."); - } - - if (i >= SMBUS_TIMEOUT) - print_err("SMBus timed out while warming up\n"); - else - PRINT_DEBUG("Done\n"); -} - -/* FIXME: Better separate the NB and SB, will be done once it works. */ - -void vt8237_sb_enable_fid_vid(void) -{ - device_t dev, devctl; - u16 devid; - - /* Power management controller */ - dev = get_vt8237_lpc(); - if (dev == PCI_DEV_INVALID) - return; - - devid = pci_read_config16(dev, PCI_DEVICE_ID); - - /* generic setup */ - - /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ - pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); - - /* Enable ACPI accessm RTC signal gated with PSON. */ - pci_write_config8(dev, 0x81, 0x84); - - /* chipset-specific parts */ - - /* VLINK: FIXME: can we drop the devid check and just look for the VLINK device? */ - if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC || - devid == PCI_DEVICE_ID_VIA_VT8237A_LPC) { - devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237_VLINK), 0); - - if (devctl != PCI_DEV_INVALID) { - /* So the chip knows we are on AMD. */ - pci_write_config8(devctl, 0x7c, 0x7f); - } - } - - if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC) { - /* - * Allow SLP# signal to assert LDTSTOP_L. - * Will work for C3 and for FID/VID change. - */ - - outb(0xff, VT8237R_ACPI_IO_BASE + 0x50); - - /* Reduce further the STPCLK/LDTSTP signal to 5us. */ - pci_write_config8(dev, 0xec, 0x4); - - return; - } - - /* VT8237R and VT8237A */ - - /* - * Allow SLP# signal to assert LDTSTOP_L. - * Will work for C3 and for FID/VID change. - */ - outb(0x1, VT8237R_ACPI_IO_BASE + 0x11); -} - -void enable_rom_decode(void) -{ - device_t dev; - - /* Power management controller */ - dev = get_vt8237_lpc(); - if (dev == PCI_DEV_INVALID) - return; - - /* ROM decode last 1MB FFC00000 - FFFFFFFF. */ - pci_write_config8(dev, 0x41, 0x7f); -} - -#if CONFIG_HAVE_ACPI_RESUME == 1 -static int acpi_is_wakeup_early(void) { - device_t dev; - u16 tmp; - - print_debug("IN TEST WAKEUP\n"); - - /* Power management controller */ - dev = get_vt8237_lpc(); - if (dev == PCI_DEV_INVALID) - die("Power management controller not found\n"); - - /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ - pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); - - /* Enable ACPI accessm RTC signal gated with PSON. */ - pci_write_config8(dev, 0x81, 0x84); - - tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); - - print_debug_hex8(tmp); - return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; -} -#endif - -#if defined(__GNUC__) -void vt8237_early_spi_init(void) -{ - device_t dev; - volatile u16 *spireg; - u32 tmp; - - /* Bus Control and Power Management */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); - - if (dev == PCI_DEV_INVALID) - die("SB not found\n"); - - /* Put SPI base 20 d0 fe. */ - tmp = pci_read_config32(dev, 0xbc); - pci_write_config32(dev, 0xbc, - (VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000)); - - /* Set SPI clock to 33MHz. */ - spireg = (u16 *) (VT8237S_SPI_MEM_BASE + 0x6c); - (*spireg) &= 0xff00; -} -#endif - -/* This #if is special. ROMCC chokes on the (rom == NULL) comparison. - * Since the whole function is only called for one target and that target - * is compiled with GCC, hide the function from ROMCC and be happy. - */ -#if defined(__GNUC__) -/* - * Offset 0x58: - * 31:20 reserved - * 19:16 4 bit position in shadow EEPROM - * 15:0 data to write - * - * Offset 0x5c: - * 31:28 reserved - * 27 ERDBG - enable read from 0x5c - * 26 reserved - * 25 SEELD - * 24 SEEPR - write 1 when done updating, wait until SEELD is - * set to 1, sticky - * cleared by reset, if it is 1 writing is disabled - * 19:16 4 bit position in shadow EEPROM - * 15:0 data from shadow EEPROM - * - * After PCIRESET SEELD and SEEPR must be 1 and 1. - */ - -/* 1 = needs PCI reset, 0 don't reset, network initialized. */ - -/* FIXME: Maybe close the debug register after use? */ - -#define LAN_TIMEOUT 0x7FFFFFFF - -int vt8237_early_network_init(struct vt8237_network_rom *rom) -{ - struct vt8237_network_rom n; - int i, loops; - device_t dev; - u32 tmp; - u8 status; - u16 *rom_write; - unsigned int checksum; - - /* Network adapter */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_8233_7), 0); - if (dev == PCI_DEV_INVALID) { - print_err("Network is disabled, please enable\n"); - return 0; - } - - tmp = pci_read_config32(dev, 0x5c); - tmp |= 0x08000000; /* Enable ERDBG. */ - pci_write_config32(dev, 0x5c, tmp); - - status = ((pci_read_config32(dev, 0x5c) >> 24) & 0x3); - - /* Network controller OK, EEPROM loaded. */ - if (status == 3) - return 0; - - if (rom == NULL) { - print_err("No config data specified, using default MAC!\n"); - n.mac_address[0] = 0x0; - n.mac_address[1] = 0x0; - n.mac_address[2] = 0xde; - n.mac_address[3] = 0xad; - n.mac_address[4] = 0xbe; - n.mac_address[5] = 0xef; - n.phy_addr = 0x1; - n.res1 = 0x0; - n.sub_sid = 0x102; - n.sub_vid = 0x1106; - n.pid = 0x3065; - n.vid = 0x1106; - n.pmcc = 0x1f; - n.data_sel = 0x10; - n.pmu_data_reg = 0x0; - n.aux_curr = 0x0; - n.reserved = 0x0; - n.min_gnt = 0x3; - n.max_lat = 0x8; - n.bcr0 = 0x9; - n.bcr1 = 0xe; - n.cfg_a = 0x3; - n.cfg_b = 0x0; - n.cfg_c = 0x40; - n.cfg_d = 0x82; - n.checksum = 0x0; - rom = &n; - } - - rom_write = (u16 *) rom; - checksum = 0; - /* Write all data except checksum and second to last byte. */ - tmp &= 0xff000000; /* Leave reserved bits in. */ - for (i = 0; i < 15; i++) { - pci_write_config32(dev, 0x58, tmp | (i << 16) | rom_write[i]); - /* Lame code FIXME */ - checksum += rom_write[i] & 0xff; - /* checksum %= 256; */ - checksum += (rom_write[i] >> 8) & 0xff; - /* checksum %= 256; */ - } - - checksum += (rom_write[15] & 0xff); - checksum = ~(checksum & 0xff); - tmp |= (((checksum & 0xff) << 8) | rom_write[15]); - - /* Write last byte and checksum. */ - pci_write_config32(dev, 0x58, (15 << 16) | tmp); - - tmp = pci_read_config32(dev, 0x5c); - pci_write_config32(dev, 0x5c, tmp | 0x01000000); /* Toggle SEEPR. */ - - /* Yes, this is a mess, but it's the easiest way to do it. */ - /* XXX not so messy, but an explanation of the hack would have been better */ - loops = 0; - while ((((pci_read_config32(dev, 0x5c) >> 25) & 1) == 0) - && (loops < LAN_TIMEOUT)) { - ++loops; - } - - if (loops >= LAN_TIMEOUT) { - print_err("Timeout - LAN controller didn't accept config\n"); - return 0; - } - - /* We are done, config will be used after PCIRST#. */ - return 1; -} -#endif diff --git a/src/southbridge/via/vt8237r/vt8237r_ide.c b/src/southbridge/via/vt8237r/vt8237r_ide.c deleted file mode 100644 index 209437b729..0000000000 --- a/src/southbridge/via/vt8237r/vt8237r_ide.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Rudolf Marek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Based on other VIA SB code. */ - -#include -#include -#include -#include -#include "vt8237r.h" -#include "chip.h" - -/** - * Cable type detect function, weak so it can be overloaded in mainboard.c - */ -u32 __attribute__((weak)) vt8237_ide_80pin_detect(struct device *dev) -{ - struct southbridge_via_vt8237r_config *sb = - (struct southbridge_via_vt8237r_config *)dev->chip_info; - u32 res; - res = sb->ide0_80pin_cable ? VT8237R_IDE0_80PIN_CABLE : 0; - res |= sb->ide1_80pin_cable ? VT8237R_IDE1_80PIN_CABLE : 0; - return res; -} - -/** - * No native mode. Interrupts from unconnected HDDs might occur if - * IRQ14/15 is used for PCI. Therefore no native mode support. - */ -static void ide_init(struct device *dev) -{ - struct southbridge_via_vt8237r_config *sb = - (struct southbridge_via_vt8237r_config *)dev->chip_info; - - u8 enables; - u32 cablesel; - - printk(BIOS_INFO, "%s IDE interface %s\n", "Primary", - sb->ide0_enable ? "enabled" : "disabled"); - printk(BIOS_INFO, "%s IDE interface %s\n", "Secondary", - sb->ide1_enable ? "enabled" : "disabled"); - enables = pci_read_config8(dev, IDE_CS) & ~0x3; - enables |= (sb->ide0_enable << 1) | sb->ide1_enable; - pci_write_config8(dev, IDE_CS, enables); - enables = pci_read_config8(dev, IDE_CS); - printk(BIOS_DEBUG, "Enables in reg 0x40 read back as 0x%x\n", enables); - - /* Enable only compatibility mode. */ - enables = pci_read_config8(dev, 0x09); - enables &= 0xFA; - pci_write_config8(dev, 0x09, enables); - - enables = pci_read_config8(dev, IDE_CONF_II); - enables &= ~0xc0; - pci_write_config8(dev, IDE_CONF_II, enables); - enables = pci_read_config8(dev, IDE_CONF_II); - printk(BIOS_DEBUG, "Enables in reg 0x42 read back as 0x%x\n", enables); - - /* Enable prefetch buffers. */ - enables = pci_read_config8(dev, IDE_CONF_I); - enables |= 0xf0; - pci_write_config8(dev, IDE_CONF_I, enables); - - /* Flush FIFOs at half. */ - enables = pci_read_config8(dev, IDE_CONF_FIFO); - enables &= 0xf0; - enables |= (1 << 2) | (1 << 0); - pci_write_config8(dev, IDE_CONF_FIFO, enables); - - /* PIO read prefetch counter, Bus Master IDE Status Reg. Read Retry. */ - enables = pci_read_config8(dev, IDE_MISC_I); - enables &= 0xe2; - enables |= (1 << 4) | (1 << 3); - pci_write_config8(dev, IDE_MISC_I, enables); - - /* Use memory read multiple, Memory-Write-and-Invalidate. */ - enables = pci_read_config8(dev, IDE_MISC_II); - enables &= 0xEF; - enables |= (1 << 2) | (1 << 3); - pci_write_config8(dev, IDE_MISC_II, enables); - - /* Force interrupts to use compat mode. */ - pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0); - pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff); - - /* Cable guy... */ - cablesel = pci_read_config32(dev, IDE_UDMA); - cablesel &= ~VT8237R_IDE_CABLESEL_MASK; - cablesel |= vt8237_ide_80pin_detect(dev); - pci_write_config32(dev, IDE_UDMA, cablesel); - -#if CONFIG_EPIA_VT8237R_INIT - device_t lpc_dev; - - /* Set PATA Output Drive Strength */ - lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); - if (lpc_dev) - pci_write_config8(lpc_dev, 0x7C, 0x20); -#endif -} - -static const struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .enable = 0, - .ops_pci = 0, -}; - -static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_82C586_1, -}; diff --git a/src/southbridge/via/vt8237r/vt8237r_lpc.c b/src/southbridge/via/vt8237r/vt8237r_lpc.c deleted file mode 100644 index 72b85b37d5..0000000000 --- a/src/southbridge/via/vt8237r/vt8237r_lpc.c +++ /dev/null @@ -1,624 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007, 2008 Rudolf Marek - * Copyright (C) 2009 Jon Harrison - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Inspiration from other VIA SB code. */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "vt8237r.h" -#include "chip.h" - -static void southbridge_init_common(struct device *dev); - -#if CONFIG_EPIA_VT8237R_INIT - /* Interrupts for INT# A B C D */ -static const unsigned char pciIrqs[4] = { 10, 11, 12, 0}; - - /* Interrupt Assignments for Pins 1 2 3 4 */ -static const unsigned char sataPins[4] = { 'A','B','C','D'}; -static const unsigned char vgaPins[4] = { 'A','B','C','D'}; -static const unsigned char usbPins[4] = { 'A','B','C','D'}; -static const unsigned char enetPins[4] = { 'A','B','C','D'}; -static const unsigned char vt8237Pins[4] = { 'A','B','C','D'}; -static const unsigned char slotPins[4] = { 'C','D','A','B'}; -static const unsigned char riserPins[4] = { 'D','C','B','A'}; - -static unsigned char *pin_to_irq(const unsigned char *pin) -{ - static unsigned char Irqs[4]; - int i; - for (i = 0 ; i < 4 ; i++) - Irqs[i] = pciIrqs[ pin[i] - 'A' ]; - - return Irqs; -} -#endif - -/** Set up PCI IRQ routing, route everything through APIC. */ -static void pci_routing_fixup(struct device *dev) -{ -#if CONFIG_EPIA_VT8237R_INIT - device_t pdev; -#endif - - /* PCI PNP Interrupt Routing INTE/F - disable */ - pci_write_config8(dev, 0x44, 0x00); - - /* PCI PNP Interrupt Routing INTG/H - disable */ - pci_write_config8(dev, 0x45, 0x00); - - /* Gate Interrupts until RAM Writes are flushed */ - pci_write_config8(dev, 0x49, 0x20); - -#if CONFIG_EPIA_VT8237R_INIT - - /* Share INTE-INTH with INTA-INTD as per stock BIOS. */ - pci_write_config8(dev, 0x46, 0x00); - - /* setup PCI IRQ routing (For PCI Slot)*/ - pci_write_config8(dev, 0x55, pciIrqs[0] << 4); - pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4) ); - pci_write_config8(dev, 0x57, pciIrqs[3] << 4); - - /* PCI Routing Fixup */ - - //Setup MiniPCI Slot - pci_assign_irqs(0, 0x14, pin_to_irq(slotPins)); - - // Via 2 slot riser card 2nd slot - pci_assign_irqs(0, 0x13, pin_to_irq(riserPins)); - - //Setup USB - pci_assign_irqs(0, 0x10, pin_to_irq(usbPins)); - - //Setup VT8237R Sound - pci_assign_irqs(0, 0x11, pin_to_irq(vt8237Pins)); - - //Setup Ethernet - pci_assign_irqs(0, 0x12, pin_to_irq(enetPins)); - - //Setup VGA - pci_assign_irqs(1, 0x00, pin_to_irq(vgaPins)); - - /* APIC Routing Fixup */ - - // Setup SATA - pdev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT6420_SATA, 0); - pci_write_config8(pdev, PCI_INTERRUPT_PIN, 0x02); - pci_assign_irqs(0, 0x0f, pin_to_irq(sataPins)); - - - // Setup PATA Override - pdev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_82C586_1, 0); - pci_write_config8(pdev, PCI_INTERRUPT_PIN, 0x01); - pci_write_config8(pdev, PCI_INTERRUPT_LINE, 0xFF); - -#else - /* Route INTE-INTH through registers above, no map to INTA-INTD. */ - pci_write_config8(dev, 0x46, 0x10); - - /* PCI Interrupt Polarity */ - pci_write_config8(dev, 0x54, 0x00); - - /* PCI INTA# Routing */ - pci_write_config8(dev, 0x55, 0x00); - - /* PCI INTB#/C# Routing */ - pci_write_config8(dev, 0x56, 0x00); - - /* PCI INTD# Routing */ - pci_write_config8(dev, 0x57, 0x00); -#endif -} - - - -/** - * Set up the power management capabilities directly into ACPI mode. - * This avoids having to handle any System Management Interrupts (SMIs). - */ - -extern u8 acpi_slp_type; - - -static void setup_pm(device_t dev) -{ - u16 tmp; - /* Debounce LID and PWRBTN# Inputs for 16ms. */ - pci_write_config8(dev, 0x80, 0x20); - - /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ - pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); - - /* Set ACPI to 9, must set IRQ 9 override to level! Set PSON gating. */ - pci_write_config8(dev, 0x82, 0x40 | VT8237R_ACPI_IRQ); - -#if CONFIG_EPIA_VT8237R_INIT - /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */ - pci_write_config16(dev, 0x84, 0x3052); -#else - /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */ - pci_write_config16(dev, 0x84, 0x30b2); - -#endif - /* SMI output level to low, 7.5us throttle clock */ - pci_write_config8(dev, 0x8d, 0x18); - - /* GP Timer Control 1s */ - pci_write_config8(dev, 0x93, 0x88); - - /* - * 7 = SMBus clock from RTC 32.768KHz - * 5 = Internal PLL reset from susp disabled - * 2 = GPO2 is SUSA# - */ - pci_write_config8(dev, 0x94, 0xa0); - - /* - * 7 = stp to sust delay 1msec - * 6 = SUSST# Deasserted Before PWRGD for STD - * 5 = Keyboard/Mouse Swap - * 4 = PWRGOOD reset on VT8237A/S - * 3 = GPO26/GPO27 is GPO - * 2 = Disable Alert on Lan - * 1 = SUSCLK/GPO4 - * 0 = USB Wakeup - */ - -#if CONFIG_EPIA_VT8237R_INIT - pci_write_config8(dev, 0x95, 0xc2); -#else - pci_write_config8(dev, 0x95, 0xcc); -#endif - - /* Disable GP3 timer. */ - pci_write_config8(dev, 0x98, 0); - - /* Enable ACPI accessm RTC signal gated with PSON. */ - pci_write_config8(dev, 0x81, 0x84); - - /* Clear status events. */ - outw(0xffff, VT8237R_ACPI_IO_BASE + 0x00); - outw(0xffff, VT8237R_ACPI_IO_BASE + 0x20); - outw(0xffff, VT8237R_ACPI_IO_BASE + 0x28); - outl(0xffffffff, VT8237R_ACPI_IO_BASE + 0x30); - - /* Disable SCI on GPIO. */ - outw(0x0, VT8237R_ACPI_IO_BASE + 0x22); - - /* Disable SMI on GPIO. */ - outw(0x0, VT8237R_ACPI_IO_BASE + 0x24); - - /* Disable all global enable SMIs. */ - outw(0x0, VT8237R_ACPI_IO_BASE + 0x2a); - - /* All SMI off, both IDE buses ON, PSON rising edge. */ - outw(0x0, VT8237R_ACPI_IO_BASE + 0x2c); - - /* Primary activity SMI disable. */ - outl(0x0, VT8237R_ACPI_IO_BASE + 0x34); - - /* GP timer reload on none. */ - outl(0x0, VT8237R_ACPI_IO_BASE + 0x38); - - /* Disable extended IO traps. */ - outb(0x0, VT8237R_ACPI_IO_BASE + 0x42); - - /* SCI is generated for RTC/pwrBtn/slpBtn. */ - tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); -#if CONFIG_HAVE_ACPI_RESUME == 1 - acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; - printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type); -#endif - /* clear sleep */ - tmp &= ~(7 << 10); - tmp |= 1; - outw(tmp, VT8237R_ACPI_IO_BASE + 0x04); -} - -static void vt8237r_init(struct device *dev) -{ - u8 enables; - -#if CONFIG_EPIA_VT8237R_INIT - printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n"); - /* - * TODO: Looks like stock BIOS can do this but causes a hang - * Enable SATA LED, disable special CPU Frequency Change - - * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs. - * Setup to match EPIA default - * PCS0# on Pin U1 - */ - enables = pci_read_config8(dev, 0xe5); - enables |= 0x23; - pci_write_config8(dev, 0xe5, enables); - - /* - * Enable Flash Write Access. - * Note EPIA-N Does not use REQ5 or PCISTP#(Hang) - */ - enables = pci_read_config8(dev, 0xe4); - enables |= 0x2B; - pci_write_config8(dev, 0xe4, enables); - - /* Enables Extra RTC Ports */ - enables = pci_read_config8(dev, 0x4E); - enables |= 0x80; - pci_write_config8(dev, 0x4E, enables); - -#else - printk(BIOS_SPEW, "Entering vt8237r_init.\n"); - /* - * Enable SATA LED, disable special CPU Frequency Change - - * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs. - */ - pci_write_config8(dev, 0xe5, 0x09); - - /* REQ5 as PCI request input - should be together with INTE-INTH. */ - pci_write_config8(dev, 0xe4, 0x4); -#endif - - /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ - enables = pci_read_config8(dev, 0x4f); - enables |= 0x08; - pci_write_config8(dev, 0x4f, enables); - -#if CONFIG_EPIA_VT8237R_INIT - /* - * Set Read Pass Write Control Enable - */ - pci_write_config8(dev, 0x48, 0x0c); -#else - /* - * Set Read Pass Write Control Enable - * (force A2 from APIC FSB to low). - */ - pci_write_config8(dev, 0x48, 0x8c); -#endif - - southbridge_init_common(dev); - -#if !CONFIG_EPIA_VT8237R_INIT - /* FIXME: Intel needs more bit set for C2/C3. */ - - /* - * Allow SLP# signal to assert LDTSTOP_L. - * Will work for C3 and for FID/VID change. - */ - outb(0x1, VT8237R_ACPI_IO_BASE + 0x11); -#endif - - printk(BIOS_SPEW, "Leaving %s.\n", __func__); -} - -static void vt8237a_init(struct device *dev) -{ - /* - * FIXME: This is based on vt8237s_init() and the values the AMI - * BIOS on my M2V wrote to these registers (by loking - * at lspci -nxxx output). - * Works for me. - */ - u32 tmp; - - /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ - tmp = pci_read_config8(dev, 0x4f); - tmp |= 0x08; - pci_write_config8(dev, 0x4f, tmp); - - /* - * bit2: REQ5 as PCI request input - should be together with INTE-INTH. - * bit5: usb power control lines as gpio - */ - pci_write_config8(dev, 0xe4, 0x24); - /* - * Enable APIC wakeup from INTH - * Enable SATA LED, disable special CPU Frequency Change - - * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs. - */ - pci_write_config8(dev, 0xe5, 0x69); - - /* Reduce further the STPCLK/LDTSTP signal to 5us. */ - pci_write_config8(dev, 0xec, 0x4); - - /* Host Bus Power Management Control, maybe not needed */ - pci_write_config8(dev, 0x8c, 0x5); - - /* Enable HPET at VT8237R_HPET_ADDR. */ - pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80)); - - southbridge_init_common(dev); - - /* Share INTE-INTH with INTA-INTD for simplicity */ - pci_write_config8(dev, 0x46, 0x00); - - /* FIXME: Intel needs more bit set for C2/C3. */ - - /* - * Allow SLP# signal to assert LDTSTOP_L. - * Will work for C3 and for FID/VID change. - */ - outb(0x1, VT8237R_ACPI_IO_BASE + 0x11); - - dump_south(dev); -} - -static void vt8237s_init(struct device *dev) -{ - u32 tmp; - - /* Put SPI base VT8237S_SPI_MEM_BASE. */ - tmp = pci_read_config32(dev, 0xbc); - pci_write_config32(dev, 0xbc, - (VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000)); - - /* - * REQ5 as PCI request input - should be together with INTE-INTH. - */ - pci_write_config8(dev, 0xe4, 0x04); - - /* Reduce further the STPCLK/LDTSTP signal to 5us. */ - pci_write_config8(dev, 0xec, 0x4); - - /* Host Bus Power Management Control, maybe not needed */ - pci_write_config8(dev, 0x8c, 0x5); - - /* Enable HPET at VT8237R_HPET_ADDR., does not work correctly on R. */ - pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80)); - - southbridge_init_common(dev); - - /* FIXME: Intel needs more bit set for C2/C3. */ - - /* - * Allow SLP# signal to assert LDTSTOP_L. - * Will work for C3 and for FID/VID change. FIXME FIXME, pre rev A2. - */ - outb(0xff, VT8237R_ACPI_IO_BASE + 0x50); - - dump_south(dev); -} - -static void vt8237_common_init(struct device *dev) -{ - u8 enables, byte; - - /* Enable addr/data stepping. */ - byte = pci_read_config8(dev, PCI_COMMAND); - byte |= PCI_COMMAND_WAIT; - pci_write_config8(dev, PCI_COMMAND, byte); - -/* EPIA-N(L) Uses CN400 for BIOS Access */ -#if !CONFIG_EPIA_VT8237R_INIT - /* Enable the internal I/O decode. */ - enables = pci_read_config8(dev, 0x6C); - enables |= 0x80; - pci_write_config8(dev, 0x6C, enables); - - /* - * ROM decode - * bit range - * 7 000E0000h-000EFFFFh - * 6 FFF00000h-FFF7FFFFh - * 5 FFE80000h-FFEFFFFFh - * 4 FFE00000h-FFE7FFFFh - * 3 FFD80000h-FFDFFFFFh - * 2 FFD00000h-FFD7FFFFh - * 1 FFC80000h-FFCFFFFFh - * 0 FFC00000h-FFC7FFFFh - * So 0x7f here sets ROM decode to FFC00000-FFFFFFFF or 4Mbyte. - */ - pci_write_config8(dev, 0x41, 0x7f); -#endif - - /* - * Set bit 6 of 0x40 (I/O recovery time). - * IMPORTANT FIX - EISA = ECLR reg at 0x4d0! Decoding must be on so - * that PCI interrupts can be properly marked as level triggered. - */ - enables = pci_read_config8(dev, 0x40); - enables |= 0x44; - pci_write_config8(dev, 0x40, enables); - - /* Line buffer control */ - enables = pci_read_config8(dev, 0x42); - enables |= 0xf8; - pci_write_config8(dev, 0x42, enables); - - /* Delay transaction control */ - pci_write_config8(dev, 0x43, 0xb); - -#if CONFIG_EPIA_VT8237R_INIT - /* I/O recovery time, default IDE routing */ - pci_write_config8(dev, 0x4c, 0x04); - - /* ROM memory cycles go to LPC. */ - pci_write_config8(dev, 0x59, 0x80); - - /* - * Bit | Meaning - * ------------- - * 3 | Bypass APIC De-Assert Message (1=Enable) - * 1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI" - * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch - * 0 | Dynamic Clock Gating Main Switch (1=Enable) - */ - pci_write_config8(dev, 0x5b, 0x9); - - /* Set 0x58 to 0x42 APIC On and RTC Write Protect.*/ - pci_write_config8(dev, 0x58, 0x42); - - /* Enable serial IRQ, 6PCI clocks. */ - pci_write_config8(dev, 0x52, 0x9); -#else - /* I/O recovery time, default IDE routing */ - pci_write_config8(dev, 0x4c, 0x44); - - /* ROM memory cycles go to LPC. */ - pci_write_config8(dev, 0x59, 0x80); - - /* - * Bit | Meaning - * ------------- - * 3 | Bypass APIC De-Assert Message (1=Enable) - * 1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI" - * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch - * 0 | Dynamic Clock Gating Main Switch (1=Enable) - */ - pci_write_config8(dev, 0x5b, 0xb); - - /* Set 0x58 to 0x43 APIC and RTC. */ - pci_write_config8(dev, 0x58, 0x43); - - /* Enable serial IRQ, 6PCI clocks. */ - pci_write_config8(dev, 0x52, 0x9); - -#endif - - /* Power management setup */ - setup_pm(dev); - - /* Start the RTC. */ - rtc_init(0); -} - -static void vt8237r_read_resources(device_t dev) -{ - struct resource *res; - - pci_dev_read_resources(dev); - - /* Fixed ACPI Base IO Base*/ - res = new_resource(dev, 0x88); - res->base = VT8237R_ACPI_IO_BASE; - res->size = 128; - res->limit = 0xffffUL; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Fixed EISA ECLR I/O Regs */ - res = new_resource(dev, 3); - res->base = 0x4d0; - res->size = 2; - res->limit = 0xffffUL; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Fixed System Management Bus I/O Resource */ - res = new_resource(dev, 0xD0); - res->base = VT8237R_SMBUS_IO_BASE; - res->size = 16; - res->limit = 0xffffUL; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Fixed APIC resource */ - res = new_resource(dev, 0x44); - res->base = IO_APIC_ADDR; - res->size = 256; - res->limit = 0xffffffffUL; - res->align = 8; - res->gran = 8; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Fixed flashrom resource */ - res = new_resource(dev, 4); - res->base = 0xff000000UL; - res->size = 0x01000000UL; /* 16MB */ - res->limit = 0xffffffffUL; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - res = new_resource(dev, 1); - res->base = 0x0UL; - res->size = 0x1000UL; - res->limit = 0xffffUL; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -static void init_keyboard(struct device *dev) -{ - u8 regval = pci_read_config8(dev, 0x51); - if (regval & 0x1) - pc_keyboard_init(0); -} - -static void southbridge_init_common(struct device *dev) -{ - vt8237_common_init(dev); - pci_routing_fixup(dev); - setup_ioapic(IO_APIC_ADDR, VT8237R_APIC_ID); - setup_i8259(); - init_keyboard(dev); -} - -static const struct device_operations vt8237r_lpc_ops_s = { - .read_resources = vt8237r_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = vt8237s_init, - .scan_bus = scan_static_bus, -}; - -static const struct device_operations vt8237r_lpc_ops_r = { - .read_resources = vt8237r_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = vt8237r_init, - .scan_bus = scan_static_bus, -}; - -static const struct device_operations vt8237r_lpc_ops_a = { - .read_resources = vt8237r_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = vt8237a_init, - .scan_bus = scan_static_bus, -}; - -static const struct pci_driver lpc_driver_r __pci_driver = { - .ops = &vt8237r_lpc_ops_r, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT8237R_LPC, -}; - -static const struct pci_driver lpc_driver_a __pci_driver = { - .ops = &vt8237r_lpc_ops_a, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT8237A_LPC, -}; - -static const struct pci_driver lpc_driver_s __pci_driver = { - .ops = &vt8237r_lpc_ops_s, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT8237S_LPC, -}; diff --git a/src/southbridge/via/vt8237r/vt8237r_nic.c b/src/southbridge/via/vt8237r/vt8237r_nic.c deleted file mode 100644 index 6771895916..0000000000 --- a/src/southbridge/via/vt8237r/vt8237r_nic.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007, 2008 Rudolf Marek - * Copyright (C) 2009 Jon Harrison - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include "vt8237r.h" - - -static void vt8237_eth_read_resources(struct device *dev) -{ -#if CONFIG_EPIA_VT8237R_INIT - struct resource *res; - - /* Fix the I/O Resources of the USB2.0 Interface */ - res = new_resource(dev, PCI_BASE_ADDRESS_0); - res->base = 0xF6001000ULL; - res->size = 256; - res->align = 12; - res->gran = 8; - res->limit = res->base + res->size - 1; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_ASSIGNED; -#else - pci_dev_read_resources(dev); -#endif - return; -} - - -static const struct device_operations vt8237_eth_ops = { - .read_resources = vt8237_eth_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .enable = 0, - .ops_pci = 0, -}; - -static const struct pci_driver vt8237r_driver_eth __pci_driver = { - .ops = &vt8237_eth_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_8233_7, -}; diff --git a/src/southbridge/via/vt8237r/vt8237r_pirq.c b/src/southbridge/via/vt8237r/vt8237r_pirq.c deleted file mode 100644 index 9915da4835..0000000000 --- a/src/southbridge/via/vt8237r/vt8237r_pirq.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Nikolay Petukhov - * Copyright (C) 2010 Tobias Diedrich - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include - -#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_GENERATE_PIRQ_TABLE==1) -void pirq_assign_irqs(const unsigned char route[4]) -{ - device_t pdev; - - pdev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); - if (!pdev) - pdev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237S_LPC, 0); - if (!pdev) - pdev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237A_LPC, 0); - if (!pdev) - return; - - pci_write_config8(pdev, 0x55, route[0] << 4); - pci_write_config8(pdev, 0x56, (route[2] << 4) | route[1]); - pci_write_config8(pdev, 0x57, route[3] << 4); - - /* Enable INT[E-H] mapped to INT[A-D] for simplicity */ - pci_write_config8(pdev, 0x46, 0x00); -} -#endif diff --git a/src/southbridge/via/vt8237r/vt8237r_sata.c b/src/southbridge/via/vt8237r/vt8237r_sata.c deleted file mode 100644 index 777d605a6b..0000000000 --- a/src/southbridge/via/vt8237r/vt8237r_sata.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007, 2008 Rudolf Marek - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include - -#define SATA_MISC_CTRL 0x45 - -static void sata_i_init(struct device *dev) -{ - u8 reg; - - printk(BIOS_DEBUG, "Configuring VIA SATA controller\n"); - - /* Class IDE Disk */ - reg = pci_read_config8(dev, SATA_MISC_CTRL); - reg &= 0x7f; /* Sub Class Write Protect off */ - pci_write_config8(dev, SATA_MISC_CTRL, reg); - - /* Change the device class to SATA from RAID. */ - pci_write_config8(dev, PCI_CLASS_DEVICE, 0x1); - reg |= 0x80; /* Sub Class Write Protect on */ - pci_write_config8(dev, SATA_MISC_CTRL, reg); - - return; -} - -static void sata_ii_init(struct device *dev) -{ - u8 reg; - - sata_i_init(dev); - - /* - * Analog black magic, you may or may not need to adjust 0x60-0x6f, - * depends on PCB. - */ - - /* - * Analog PHY - gen1 - * CDR bandwidth [6:5] = 3 - * Squelch Window Select [4:3] = 1 - * CDR Charge Pump [2:0] = 1 - */ - - pci_write_config8(dev, 0x64, 0x49); - - /* Adjust driver current source value to 9. */ - reg = pci_read_config8(dev, 0x65); - reg &= 0xf0; - reg |= 0x9; - pci_write_config8(dev, 0x65, reg); - - /* Set all manual termination 50ohm bits [2:0] and enable [4]. */ - reg = pci_read_config8(dev, 0x6a); - reg |= 0xf; - pci_write_config8(dev, 0x6a, reg); - - /* - * Analog PHY - gen2 - * CDR bandwidth [5:4] = 2 - * Pre / De-emphasis Level [7:6] controls bits [3:2], rest in 0x6e - * CDR Charge Pump [2:0] = 1 - */ - - reg = pci_read_config8(dev, 0x6f); - reg &= 0x08; - reg |= 0x61; - pci_write_config8(dev, 0x6f, reg); - - /* Check if staggered spinup is supported. */ - reg = pci_read_config8(dev, 0x83); - if ((reg & 0x8) == 0) { - /* Start OOB sequence on both drives. */ - reg |= 0x30; - pci_write_config8(dev, 0x83, reg); - } -} - -static const struct device_operations sata_i_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sata_i_init, - .enable = 0, - .ops_pci = 0, -}; - -static const struct device_operations sata_ii_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sata_ii_init, - .enable = 0, - .ops_pci = 0, -}; - -static const struct pci_driver northbridge_driver_ii __pci_driver = { - .ops = &sata_ii_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT8237_SATA, -}; - -static const struct pci_driver northbridge_driver_i_a __pci_driver = { - .ops = &sata_i_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT8237A_SATA, -}; - -static const struct pci_driver northbridge_driver_i __pci_driver = { - .ops = &sata_i_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT6420_SATA, -}; diff --git a/src/southbridge/via/vt8237r/vt8237r_usb.c b/src/southbridge/via/vt8237r/vt8237r_usb.c deleted file mode 100644 index 6e8d9e5dd0..0000000000 --- a/src/southbridge/via/vt8237r/vt8237r_usb.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007, 2008 Rudolf Marek - * Copyright (C) 2009 Jon Harrison - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include -#include -#include -#include "vt8237r.h" - -#if CONFIG_EPIA_VT8237R_INIT -u32 usb_io_addr[4] = {0xcc00, 0xd000, 0xd400, 0xd800}; -#endif - -static void usb_i_init(struct device *dev) -{ -#if CONFIG_EPIA_VT8237R_INIT - u8 reg8; - - printk(BIOS_DEBUG, "Entering %s\n", __func__); - - reg8 = pci_read_config8(dev, 0x04); - - printk(BIOS_SPEW, "%s Read %02X from PCI Command Reg\n", dev_path(dev), reg8); - - reg8 = reg8 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config8(dev, 0x04, reg8); - - printk(BIOS_SPEW, "%s Wrote %02X to PCI Command Reg\n", dev_path(dev), reg8); - - /* Set Cache Line Size and Latency Timer */ - pci_write_config8(dev, 0x0c, 0x08); - pci_write_config8(dev, 0x0d, 0x20); - - /* Enable Sub Device ID Back Door and set Generic */ - reg8 = pci_read_config8(dev, 0x42); - reg8 |= 0x10; - pci_write_config8(dev, 0x42, reg8); - pci_write_config16(dev, 0x2e, 0xAA07); - reg8 &= ~0x10; - pci_write_config8(dev, 0x42, reg8); - - - pci_write_config8(dev, 0x41, 0x12); - - pci_write_config8(dev, 0x49, 0x0B); - - /* Clear PCI Status */ - pci_write_config16(dev, 0x06, 0x7A10); -#endif - return; -} - -static void vt8237_usb_i_read_resources(struct device *dev) -{ -#if CONFIG_EPIA_VT8237R_INIT - struct resource *res; - u8 function = (u8) dev->path.pci.devfn & 0x7; - - printk(BIOS_SPEW, "VT8237R Fixing USB 1.1 fn %d I/O resource = 0x%04X\n", function, usb_io_addr[function]); - - /* Fix the I/O Resources of the USB1.1 Interfaces */ - /* Auto PCI probe seems to size the resources */ - /* Incorrectly */ - res = new_resource(dev, PCI_BASE_ADDRESS_4); - res->base = usb_io_addr[function]; - res->size = 256; - res->limit = 0xffffUL; - res->align = 10; - res->gran = 8; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | - IORESOURCE_ASSIGNED; -#else - pci_dev_read_resources(dev); -#endif - return; -} - -static void usb_ii_init(struct device *dev) -{ -#if CONFIG_EPIA_VT8237R_INIT - u8 reg8; - - printk(BIOS_DEBUG, "Entering %s\n", __func__); - - /* Set memory Write and Invalidate */ - reg8 = pci_read_config8(dev, 0x04); - reg8 |= 0x10; - pci_write_config8(dev, 0x04, reg8); - - /* Set Cache line Size and Latency Timer */ - pci_write_config8(dev, 0x0c, 0x08); - pci_write_config8(dev, 0x0d, 0x20); - - /* Clear PCI Status */ - pci_write_config16(dev, 0x06, 0x7A10); -#endif - -} - -static void vt8237_usb_ii_read_resources(struct device *dev) -{ -#if CONFIG_EPIA_VT8237R_INIT - struct resource *res; - - /* Fix the I/O Resources of the USB2.0 Interface */ - res = new_resource(dev, PCI_BASE_ADDRESS_0); - res->base = 0xF6000000ULL; - res->size = 256; - res->align = 12; - res->gran = 8; - res->limit = res->base + res->size - 1; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_ASSIGNED; -#else - pci_dev_read_resources(dev); -#endif - return; -} - -static const struct device_operations usb_i_ops = { - .read_resources = vt8237_usb_i_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb_i_init, - .enable = 0, - .ops_pci = 0, -}; - -static const struct device_operations usb_ii_ops = { - .read_resources = vt8237_usb_ii_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb_ii_init, - .enable = 0, - .ops_pci = 0, -}; - -static const struct pci_driver vt8237r_driver_usbii __pci_driver = { - .ops = &usb_ii_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT8237R_EHCI, -}; - -static const struct pci_driver vt8237r_driver_usbi __pci_driver = { - .ops = &usb_i_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_VT8237R_UHCI, -}; diff --git a/src/southbridge/via/vt82c686/early_serial.c b/src/southbridge/via/vt82c686/early_serial.c new file mode 100644 index 0000000000..70c68aaaf5 --- /dev/null +++ b/src/southbridge/via/vt82c686/early_serial.c @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006-2007 Uwe Hermann + * Copyright (C) 2007 Corey Osgood + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This has been ported to the VIA VT82C686(A/B) from the SMSC FDC37M60x + * by Corey Osgood. See vt82c686.h for more information. */ + +#include +#include +#include "vt82c686.h" + +#define SIO_INDEX 0x3f0 +#define SIO_DATA 0x3f1 + +/** + * Configure the chip by writing the byte 'value' into the register + * specified by 'index'. + * + * @param index The index of the register to modify. + * @param value The value to write into the register. + */ +static void vt82c686_sio_write(uint8_t index, uint8_t value) +{ + outb(index, SIO_INDEX); + outb(value, SIO_DATA); +} + +/** + * Enable the serial port(s) of the VT82C686(A/B) Super I/O chip. + * + * @param dev TODO + * @param iobase TODO + */ +static void vt82c686_enable_serial(device_t dev, unsigned iobase) +{ + uint8_t reg; + device_t sbdev; + + /* TODO: Use info from 'dev' and 'iobase'. */ + /* TODO: Only enable one serial port (depending on config) or both? */ + + /* (1) Enter configuration mode (set Function 0 Rx85[1] = 1). */ + + /* Find the southbridge. Die upon error. */ + sbdev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_82C686), 0); + // sbdev = PCI_DEV(0, 7, 0); + if (sbdev == PCI_DEV_INVALID) { + /* Serial output is not yet working at this point, but + * die() emits the POST code 0xff and halts the CPU, too. */ + die("Southbridge not found.\n"); + } + + /* Enable Super-I/O (bit 0) and Super-I/O Configuration (bit 1). */ + reg = pci_read_config8(sbdev, 0x85); + pci_write_config8(sbdev, 0x85, reg | 0x3); /* Set bits 0 and 1. */ + + /* (2) Configure the chip. */ + + /* Enable serial port 1 (set bit 2) and 2 (set bit 3). */ + vt82c686_sio_write(VT82C686_FS, 0xf); + + // vt82c686_sio_write(VT82C686_POWER, 0x00); /* No powerdown */ + // vt82c686_sio_write(VT82C686_SP_CTRL, 0x00); /* Normal operation */ + vt82c686_sio_write(VT82C686_SP1, 0xfe); /* SP1: 0x3f8 */ + vt82c686_sio_write(VT82C686_SP2, 0xbe); /* SP2: 0x2f8 */ + + /* Enable high speed on serial port 1 (set bit 6) and 2 (set bit 7). */ + vt82c686_sio_write(VT82C686_SP_CFG, 0xc0); + + /* (3) Exit configuration mode (set Function 0 Rx85[1] = 0). */ + reg = pci_read_config8(sbdev, 0x85); + pci_write_config8(sbdev, 0x85, reg & 0xfd); /* Clear bit 1. */ +} + diff --git a/src/southbridge/via/vt82c686/vt82c686_early_serial.c b/src/southbridge/via/vt82c686/vt82c686_early_serial.c deleted file mode 100644 index 70c68aaaf5..0000000000 --- a/src/southbridge/via/vt82c686/vt82c686_early_serial.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006-2007 Uwe Hermann - * Copyright (C) 2007 Corey Osgood - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This has been ported to the VIA VT82C686(A/B) from the SMSC FDC37M60x - * by Corey Osgood. See vt82c686.h for more information. */ - -#include -#include -#include "vt82c686.h" - -#define SIO_INDEX 0x3f0 -#define SIO_DATA 0x3f1 - -/** - * Configure the chip by writing the byte 'value' into the register - * specified by 'index'. - * - * @param index The index of the register to modify. - * @param value The value to write into the register. - */ -static void vt82c686_sio_write(uint8_t index, uint8_t value) -{ - outb(index, SIO_INDEX); - outb(value, SIO_DATA); -} - -/** - * Enable the serial port(s) of the VT82C686(A/B) Super I/O chip. - * - * @param dev TODO - * @param iobase TODO - */ -static void vt82c686_enable_serial(device_t dev, unsigned iobase) -{ - uint8_t reg; - device_t sbdev; - - /* TODO: Use info from 'dev' and 'iobase'. */ - /* TODO: Only enable one serial port (depending on config) or both? */ - - /* (1) Enter configuration mode (set Function 0 Rx85[1] = 1). */ - - /* Find the southbridge. Die upon error. */ - sbdev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_82C686), 0); - // sbdev = PCI_DEV(0, 7, 0); - if (sbdev == PCI_DEV_INVALID) { - /* Serial output is not yet working at this point, but - * die() emits the POST code 0xff and halts the CPU, too. */ - die("Southbridge not found.\n"); - } - - /* Enable Super-I/O (bit 0) and Super-I/O Configuration (bit 1). */ - reg = pci_read_config8(sbdev, 0x85); - pci_write_config8(sbdev, 0x85, reg | 0x3); /* Set bits 0 and 1. */ - - /* (2) Configure the chip. */ - - /* Enable serial port 1 (set bit 2) and 2 (set bit 3). */ - vt82c686_sio_write(VT82C686_FS, 0xf); - - // vt82c686_sio_write(VT82C686_POWER, 0x00); /* No powerdown */ - // vt82c686_sio_write(VT82C686_SP_CTRL, 0x00); /* Normal operation */ - vt82c686_sio_write(VT82C686_SP1, 0xfe); /* SP1: 0x3f8 */ - vt82c686_sio_write(VT82C686_SP2, 0xbe); /* SP2: 0x2f8 */ - - /* Enable high speed on serial port 1 (set bit 6) and 2 (set bit 7). */ - vt82c686_sio_write(VT82C686_SP_CFG, 0xc0); - - /* (3) Exit configuration mode (set Function 0 Rx85[1] = 0). */ - reg = pci_read_config8(sbdev, 0x85); - pci_write_config8(sbdev, 0x85, reg & 0xfd); /* Clear bit 1. */ -} - -- cgit v1.2.3