From 4979ffc5cb267c7b0a5ad84c8bb9729e6b5613b1 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Thu, 24 May 2018 00:26:26 +0300 Subject: Remove southbridges after K8 board removals MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ib6935c026e2302b037fc82be64163f10bf775751 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/26672 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/southbridge/via/vt8237r/lpc.c | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'src/southbridge/via/vt8237r/lpc.c') diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 46b1e237fd..998340f419 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -319,21 +319,11 @@ static void vt8237r_init(struct device *dev) */ pci_write_config8(dev, 0x48, 0x0c); #else - - #if IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800) || \ - IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD) - /* It seems that when we pair with the K8T800, we need to disable - * the A2 mask - */ - pci_write_config8(dev, 0x48, 0x0c); - #else /* * Set Read Pass Write Control Enable * (force A2 from APIC FSB to low). */ pci_write_config8(dev, 0x48, 0x8c); - #endif - #endif southbridge_init_common(dev); -- cgit v1.2.3