From c817926a6bd4195cff6b6a0d8fa35b8637cee1b8 Mon Sep 17 00:00:00 2001
From: "Ronald G. Minnich" <rminnich@gmail.com>
Date: Fri, 26 Sep 2003 04:45:52 +0000
Subject: via epia; also yh lu tyan.

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1138 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
---
 src/southbridge/via/vt8231/vt8231_early_smbus.c | 114 ++++++++++++++++++++++++
 1 file changed, 114 insertions(+)
 create mode 100644 src/southbridge/via/vt8231/vt8231_early_smbus.c

(limited to 'src/southbridge/via/vt8231/vt8231_early_smbus.c')

diff --git a/src/southbridge/via/vt8231/vt8231_early_smbus.c b/src/southbridge/via/vt8231/vt8231_early_smbus.c
new file mode 100644
index 0000000000..44672be310
--- /dev/null
+++ b/src/southbridge/via/vt8231/vt8231_early_smbus.c
@@ -0,0 +1,114 @@
+#define SMBUS_IO_BASE 0x5000
+
+#define SMBGSTATUS 0xe0
+#define SMBGCTL    0xe2
+#define SMBHSTADDR 0xe4
+#define SMBHSTDAT  0xe6
+#define SMBHSTCMD  0xe8
+#define SMBHSTFIFO 0xe9
+
+#define SMBUS_TIMEOUT (100*1000*10)
+
+static void enable_smbus(void)
+{
+  device_t dev;
+	/* Power management controller */
+	dev = pci_locate_device(PCI_ID(0x1106,0x8235), 0);
+
+	if (dev == PCI_DEV_INVALID) {
+		die("SMBUS controller not found\r\n");
+	}
+
+	// set IO base address to SMBUS_IO_BASE
+	pci_write_config32(dev, 0x90, SMBUS_IO_BASE|1);
+
+	// Enable SMBus 
+	pci_write_config8(dev, 0xd2, 0x01);
+
+
+	print_debug("SMBus controller enabled\r\n");
+}
+
+
+static inline void smbus_delay(void)
+{
+	outb(0x80, 0x80);
+}
+
+static int smbus_wait_until_ready(void)
+{
+	unsigned long loops;
+	loops = SMBUS_TIMEOUT;
+	do {
+		unsigned short val;
+		smbus_delay();
+		val = inw(SMBUS_IO_BASE + SMBGSTATUS);
+		if ((val & 0x800) == 0) {
+			break;
+		}
+	} while(--loops);
+	return loops?0:-1;
+}
+
+static int smbus_wait_until_done(void)
+{
+	unsigned long loops;
+	loops = SMBUS_TIMEOUT;
+	do {
+		unsigned short val;
+		smbus_delay();
+		
+		val = inw(SMBUS_IO_BASE + SMBGSTATUS);
+		if (((val & 0x8) == 0) | ((val & 0x437) != 0)) {
+			break;
+		}
+	} while(--loops);
+	return loops?0:-1;
+}
+
+static int smbus_read_byte(unsigned device, unsigned address)
+{
+	unsigned char global_control_register;
+	unsigned char global_status_register;
+	unsigned char byte;
+
+	if (smbus_wait_until_ready() < 0) {
+		return -1;
+	}
+	
+	/* setup transaction */
+	/* disable interrupts */
+	outw(inw(SMBUS_IO_BASE + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), SMBUS_IO_BASE + SMBGCTL);
+	/* set the device I'm talking too */
+	outw(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADDR);
+	/* set the command/address... */
+	outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
+	/* set up for a byte data read */
+	outw((inw(SMBUS_IO_BASE + SMBGCTL) & ~7) | (0x2), SMBUS_IO_BASE + SMBGCTL);
+
+	/* clear any lingering errors, so the transaction will run */
+	/* Do I need to write the bits to a 1 to clear an error? */
+	outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
+
+	/* clear the data word...*/
+	outw(0, SMBUS_IO_BASE + SMBHSTDAT);
+
+	/* start the command */
+	outw((inw(SMBUS_IO_BASE + SMBGCTL) | (1 << 3)), SMBUS_IO_BASE + SMBGCTL);
+
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done() < 0) {
+		return -1;
+	}
+
+	global_status_register = inw(SMBUS_IO_BASE + SMBGSTATUS);
+
+	/* read results of transaction */
+	byte = inw(SMBUS_IO_BASE + SMBHSTDAT) & 0xff;
+
+	if (global_status_register != (1 << 4)) {
+		return -1;
+	}
+	return byte;
+}
-- 
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