From 5692c5733633bfb8b23f1111de152eff0233b713 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 5 Oct 2010 13:40:31 +0000 Subject: - move EHCI_BAR_INDEX to ehci.h - it's constant as per EHCI spec 2.3.1 - move EHCI_BAR and EHCI_DEBUG_OFFSET to Kconfig to be set by USB debug port enabled southbridges - drop USB debug code includes from romstage.cs and use romstage-srcs in the build system instead Signed-off-by: Patrick Georgi Acked-by: Uwe Hermann git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/sis/sis966/Kconfig | 8 ++++++++ src/southbridge/sis/sis966/Makefile.inc | 1 + src/southbridge/sis/sis966/sis966.h | 1 + src/southbridge/sis/sis966/sis966_enable_usbdebug.c | 11 +++++------ 4 files changed, 15 insertions(+), 6 deletions(-) (limited to 'src/southbridge/sis') diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig index f84f1506fb..bbb5ee971b 100644 --- a/src/southbridge/sis/sis966/Kconfig +++ b/src/southbridge/sis/sis966/Kconfig @@ -6,3 +6,11 @@ config SOUTHBRIDGE_SIS_SIS966 config ID_SECTION_OFFSET hex default 0x80 if SOUTHBRIDGE_SIS_SIS966 + +config EHCI_BAR + hex + default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966 + +config EHCI_DEBUG_OFFSET + hex + default 0x98 if SOUTHBRIDGE_SIS_SIS966 diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc index c3f000c769..e51c81fa83 100644 --- a/src/southbridge/sis/sis966/Makefile.inc +++ b/src/southbridge/sis/sis966/Makefile.inc @@ -9,6 +9,7 @@ driver-y += sis966_sata.c driver-y += sis966_pcie.c driver-y += sis966_aza.c ramstage-y += sis966_reset.c +romstage-y += sis966_enable_usbdebug.c chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc chipset_bootblock_lds += $(src)/southbridge/sis/sis966/romstrap.lds diff --git a/src/southbridge/sis/sis966/sis966.h b/src/southbridge/sis/sis966/sis966.h index ee04a65878..324beef3c9 100644 --- a/src/southbridge/sis/sis966/sis966.h +++ b/src/southbridge/sis/sis966/sis966.h @@ -32,5 +32,6 @@ #include "chip.h" void sis966_enable(device_t dev); +void sis966_enable_usbdebug(unsigned int port); #endif /* SIS966_H */ diff --git a/src/southbridge/sis/sis966/sis966_enable_usbdebug.c b/src/southbridge/sis/sis966/sis966_enable_usbdebug.c index 64aa7be277..a82e941b3a 100644 --- a/src/southbridge/sis/sis966/sis966_enable_usbdebug.c +++ b/src/southbridge/sis/sis966/sis966_enable_usbdebug.c @@ -24,8 +24,11 @@ /* TODO: Check whether this actually works (might be copy-paste leftover). */ #include +#include +#include #include #include +#include "sis966.h" #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE #define SIS966_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE @@ -33,10 +36,6 @@ #define SIS966_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif -#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ -#define EHCI_BAR_INDEX 0x10 -#define EHCI_DEBUG_OFFSET 0x98 - void set_debug_port(unsigned int port) { u32 dword; @@ -49,7 +48,7 @@ void set_debug_port(unsigned int port) pci_write_config32(dev, 0x74, dword); } -static void sis966_enable_usbdebug(unsigned int port) +void sis966_enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */ @@ -57,7 +56,7 @@ static void sis966_enable_usbdebug(unsigned int port) set_debug_port(port); /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); -- cgit v1.2.3