From 218c26533dc5864dd33387e75476f7c8daf3570c Mon Sep 17 00:00:00 2001 From: Morgan Tsai Date: Fri, 2 Nov 2007 16:09:58 +0000 Subject: 1. vgabios removed, will go to extra repository 2. Rename sisnb.c to sis761.c 3. Delete many mis-definition for sis device in src/include/device/pci_ids.h 4. Trim trailing spaces for all files Signed-off-by: Morgan Tsai Acked-by: Jordan Crouse Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/sis/sis966/sis966_sata.c | 254 ++++++++++--------------------- 1 file changed, 77 insertions(+), 177 deletions(-) (limited to 'src/southbridge/sis/sis966/sis966_sata.c') diff --git a/src/southbridge/sis/sis966/sis966_sata.c b/src/southbridge/sis/sis966/sis966_sata.c index c6254da68c..8d831b975e 100644 --- a/src/southbridge/sis/sis966/sis966_sata.c +++ b/src/southbridge/sis/sis966/sis966_sata.c @@ -32,65 +32,64 @@ #include "sis966.h" #include -#if 1 uint8_t SiS_SiS1183_init[68][3]={ -{0x04, 0x00, 0x05}, -{0x09, 0x00, 0x05}, -{0x2C, 0x00, 0x39}, -{0x2D, 0x00, 0x10}, -{0x2E, 0x00, 0x83}, -{0x2F, 0x00, 0x11}, -{0x90, 0x00, 0x40}, -{0x91, 0x00, 0x00}, // set mode -{0x50, 0x00, 0xA2}, -{0x52, 0x00, 0xA2}, -{0x55, 0x00, 0x96}, -{0x52, 0x00, 0xA2}, -{0x55, 0xF7, 0x00}, -{0x56, 0x00, 0xC0}, +{0x04, 0x00, 0x05}, +{0x09, 0x00, 0x05}, +{0x2C, 0x00, 0x39}, +{0x2D, 0x00, 0x10}, +{0x2E, 0x00, 0x83}, +{0x2F, 0x00, 0x11}, +{0x90, 0x00, 0x40}, +{0x91, 0x00, 0x00}, // set mode +{0x50, 0x00, 0xA2}, +{0x52, 0x00, 0xA2}, +{0x55, 0x00, 0x96}, +{0x52, 0x00, 0xA2}, +{0x55, 0xF7, 0x00}, +{0x56, 0x00, 0xC0}, {0x57, 0x00, 0x14}, -{0x67, 0x00, 0x28}, -{0x81, 0x00, 0xB3}, -{0x82, 0x00, 0x72}, -{0x83, 0x00, 0x40}, -{0x85, 0x00, 0xB3}, -{0x86, 0x00, 0x72}, +{0x67, 0x00, 0x28}, +{0x81, 0x00, 0xB3}, +{0x82, 0x00, 0x72}, +{0x83, 0x00, 0x40}, +{0x85, 0x00, 0xB3}, +{0x86, 0x00, 0x72}, {0x87, 0x00, 0x40}, -{0x88, 0x00, 0xDE}, // after set mode -{0x89, 0x00, 0xB3}, -{0x8A, 0x00, 0x72}, -{0x8B, 0x00, 0x40}, -{0x8C, 0x00, 0xDE}, -{0x8D, 0x00, 0xB3}, -{0x8E, 0x00, 0x92}, -{0x8F, 0x00, 0x40}, -{0x93, 0x00, 0x00}, -{0x94, 0x00, 0x80}, -{0x95, 0x00, 0x08}, -{0x96, 0x00, 0x80}, +{0x88, 0x00, 0xDE}, // after set mode +{0x89, 0x00, 0xB3}, +{0x8A, 0x00, 0x72}, +{0x8B, 0x00, 0x40}, +{0x8C, 0x00, 0xDE}, +{0x8D, 0x00, 0xB3}, +{0x8E, 0x00, 0x92}, +{0x8F, 0x00, 0x40}, +{0x93, 0x00, 0x00}, +{0x94, 0x00, 0x80}, +{0x95, 0x00, 0x08}, +{0x96, 0x00, 0x80}, {0x97, 0x00, 0x08}, -{0x9C, 0x00, 0x80}, -{0x9D, 0x00, 0x08}, -{0x9E, 0x00, 0x80}, -{0x9F, 0x00, 0x08}, -{0xA0, 0x00, 0x15}, -{0xA1, 0x00, 0x15}, -{0xA2, 0x00, 0x15}, +{0x9C, 0x00, 0x80}, +{0x9D, 0x00, 0x08}, +{0x9E, 0x00, 0x80}, +{0x9F, 0x00, 0x08}, +{0xA0, 0x00, 0x15}, +{0xA1, 0x00, 0x15}, +{0xA2, 0x00, 0x15}, {0xA3, 0x00, 0x15}, -{0xD8, 0xFE, 0x01}, // Com reset +{0xD8, 0xFE, 0x01}, // Com reset {0xC8, 0xFE, 0x01}, {0xE8, 0xFE, 0x01}, {0xF8, 0xFE, 0x01}, -{0xD8, 0xFE, 0x00}, // Com reset +{0xD8, 0xFE, 0x00}, // Com reset {0xC8, 0xFE, 0x00}, {0xE8, 0xFE, 0x00}, {0xF8, 0xFE, 0x00}, -{0xC4, 0xFF, 0xFF}, // Clear status +{0xC4, 0xFF, 0xFF}, // Clear status {0xC5, 0xFF, 0xFF}, {0xC6, 0xFF, 0xFF}, {0xC7, 0xFF, 0xFF}, @@ -98,7 +97,7 @@ uint8_t SiS_SiS1183_init[68][3]={ {0xD5, 0xFF, 0xFF}, {0xD6, 0xFF, 0xFF}, {0xD7, 0xFF, 0xFF}, -{0xE4, 0xFF, 0xFF}, // Clear status +{0xE4, 0xFF, 0xFF}, // Clear status {0xE5, 0xFF, 0xFF}, {0xE6, 0xFF, 0xFF}, {0xE7, 0xFF, 0xFF}, @@ -110,126 +109,33 @@ uint8_t SiS_SiS1183_init[68][3]={ {0x00, 0x00, 0x00} //End of table }; - -#else -uint8_t SiS_SiS1183_init[5][3]={ - -{0xD8, 0xFE, 0x01}, // Com reset -{0xC8, 0xFE, 0x01}, -{0xE8, 0xFE, 0x01}, -{0xF8, 0xFE, 0x01}, - -{0x00, 0x00, 0x00} -}; //End of table - -uint8_t SiS_SiS1183_init2[21][3]={ -{0xD8, 0xFE, 0x00}, -{0xC8, 0xFE, 0x00}, -{0xE8, 0xFE, 0x00}, -{0xF8, 0xFE, 0x00}, - - -{0xC4, 0xFF, 0xFF}, // Clear status -{0xC5, 0xFF, 0xFF}, -{0xC6, 0xFF, 0xFF}, -{0xC7, 0xFF, 0xFF}, -{0xD4, 0xFF, 0xFF}, -{0xD5, 0xFF, 0xFF}, -{0xD6, 0xFF, 0xFF}, -{0xD7, 0xFF, 0xFF}, -{0xE4, 0xFF, 0xFF}, // Clear status -{0xE5, 0xFF, 0xFF}, -{0xE6, 0xFF, 0xFF}, -{0xE7, 0xFF, 0xFF}, -{0xF4, 0xFF, 0xFF}, -{0xF5, 0xFF, 0xFF}, -{0xF6, 0xFF, 0xFF}, -{0xF7, 0xFF, 0xFF}, - - -{0x00, 0x00, 0x00} //End of table -}; -#endif - - - static void sata_init(struct device *dev) { - uint32_t dword; + uint32_t dword; struct southbridge_sis_sis966_config *conf; - + struct resource *res; uint16_t base; uint8_t temp8; - + conf = dev->chip_info; -printk_debug("SATA(SiS1183)_init-------->\r\n"); + print_debug("SATA_INIT:---------->\n"); -#if 1 -//-------------- enable IDE (SiS5513) ------------------------- -{ - uint8_t temp8; - int i=0; +//-------------- enable IDE (SiS1183) ------------------------- +{ + uint8_t temp8; + int i=0; while(SiS_SiS1183_init[i][0] != 0) - { temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]); - temp8 &= SiS_SiS1183_init[i][1]; - temp8 |= SiS_SiS1183_init[i][2]; - pci_write_config8(dev, SiS_SiS1183_init[i][0], temp8); - i++; + { + temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]); + temp8 &= SiS_SiS1183_init[i][1]; + temp8 |= SiS_SiS1183_init[i][2]; + pci_write_config8(dev, SiS_SiS1183_init[i][0], temp8); + i++; }; } -/* -mdelay(5); -{ - uint8_t temp8; - int i=0; - while(SiS_SiS1183_init2[i][0] != 0) - { temp8 = pci_read_config8(dev, SiS_SiS1183_init2[i][0]); - temp8 &= SiS_SiS1183_init2[i][1]; - temp8 |= SiS_SiS1183_init2[i][2]; - pci_write_config8(dev, SiS_SiS1183_init2[i][0], temp8); - i++; - }; -} -*/ //----------------------------------------------------------- -#endif - - -#if 0 - - dword = pci_read_config32(dev, 0x50); - /* Ensure prefetch is disabled */ - dword &= ~((1 << 15) | (1 << 13)); - if(conf) { - if (conf->sata1_enable) { - /* Enable secondary SATA interface */ - dword |= (1<<0); - printk_debug("SATA S \t"); - } - if (conf->sata0_enable) { - /* Enable primary SATA interface */ - dword |= (1<<1); - printk_debug("SATA P \n"); - } - } else { - dword |= (1<<1) | (1<<0); - printk_debug("SATA P and S \n"); - } - - -#if 1 - dword &= ~(0x1f<<24); - dword |= (0x15<<24); -#endif - pci_write_config32(dev, 0x50, dword); - - dword = pci_read_config32(dev, 0xf8); - dword |= 2; - pci_write_config32(dev, 0xf8, dword); - -#endif { uint32_t i,j; @@ -239,33 +145,33 @@ for (i=0;i<10;i++){ temp32=0; temp32= pci_read_config32(dev, 0xC0); for ( j=0;j<0xFFFF;j++); - printk_debug("status= %x",temp32); + printk_debug("status= %x\n",temp32); if (((temp32&0xF) == 0x3) || ((temp32&0xF) == 0x0)) break; } -printk_debug("\n"); -} - -#if 0 -res = find_resource(dev, 0x10); -base =(uint16_t ) res->base; -printk_debug("BASE ADDR %x\n",base); -base&=0xFFFE; -printk_debug("SATA status %x\n",inb(base+7)); +} +#if DEBUG_SATA { -int i; -for(i=0;i<0xFF;i+=4) -{ - if((i%16)==0) - { - print_debug("\r\n");print_debug_hex8(i);print_debug(" ");} - print_debug_hex32(pci_read_config32(dev,i)); - print_debug(" "); - } + int i; + + print_debug("****** SATA PCI config ******"); + print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); + + for(i=0;i<0xff;i+=4){ + if((i%16)==0){ + print_debug("\r\n"); + print_debug_hex8(i); + print_debug(": "); + } + print_debug_hex32(pci_read_config32(dev,i)); + print_debug(" "); + } + print_debug("\r\n"); } #endif -printk_debug("sata_init <--------\r\n"); + + print_debug("SATA_INIT:<----------\n"); } @@ -293,9 +199,3 @@ static const struct pci_driver sata0_driver __pci_driver = { .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_SATA0, }; - -static const struct pci_driver sata1_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_SIS, - .device = PCI_DEVICE_ID_SIS_SIS966_SATA1, -}; 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