From dbec2d4090e40d1d8e1fd06e8d4180d3fa685d4d Mon Sep 17 00:00:00 2001 From: Eric Biederman Date: Thu, 21 Oct 2004 10:44:08 +0000 Subject: - Bump the LinuxBIOS major version - Rename chip_config chip_operations throughout the tree - Fix Config.lb on most of the Opteron Ports - Fix the amd 8000 chipset support for setting the subsystem vendor and device ids - Add detection of devices that are on the motherboard (i.e. In Config.lb) - Baby step in getting the resource limit handling correct, Ignore fixed resources - Only call enable_childrens_resources on devices we know will have children For some busses like i2c it is non-sense and we don't want it. - Set the resource limits for pnp devices resources. - Improve the resource size detection for pnp devices. - Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels - Added a header file to hold the prototype of isa_dma_init - Fixed most of the superio chips so the should work now, the via superio pci device is the exception. - The code compiles and runs so it is time for me to go to bed. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/ricoh/rl5c476/chip.h | 2 +- src/southbridge/ricoh/rl5c476/rl5c476.c | 60 ++++++++++----------------------- 2 files changed, 18 insertions(+), 44 deletions(-) (limited to 'src/southbridge/ricoh') diff --git a/src/southbridge/ricoh/rl5c476/chip.h b/src/southbridge/ricoh/rl5c476/chip.h index d951a8aec1..5d7a2e3ab6 100644 --- a/src/southbridge/ricoh/rl5c476/chip.h +++ b/src/southbridge/ricoh/rl5c476/chip.h @@ -1,7 +1,7 @@ #ifndef _SOUTHBRIDGE_RICOH_RL5C476 #define _SOUTHBRIDGE_RICOH_RL5C476 -extern struct chip_control southbridge_ricoh_rl5c476_control; +extern struct chip_operations southbridge_ricoh_rl5c476_control; struct southbridge_ricoh_rl5c476_config { int num; diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index 1eed3681c7..4240f96a40 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -77,22 +77,16 @@ dump_south(void) } -static void rl5c476_init(struct southbridge_rl5c476_config *conf) +static void rl5c476_init(device_t dev) { //unsigned char enables; - device_t dev; pc16reg_t *pc16; int i; - printk_debug("rl5c476 init\n"); +#error "FIXME implement carbus bridge support" +#error "FIXME this code is close to a but the conversion needs more work" /* cardbus controller function 1 for CF Socket */ - dev = dev_find_device(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, 0); - - if (!dev ){ - // probably an epia-m rather than mii - printk_debug("No rl5c476 found\n"); - return; - } + printk_debug("rl5c476 init\n"); /* setup pci header manually because 'pci_device.c' doesn't know how to handle * pci to cardbus bridges - (header type 2 I think) @@ -214,41 +208,21 @@ static void rl5c476_init(struct southbridge_rl5c476_config *conf) } -static void southbridge_init(struct chip *chip, enum chip_pass pass) -{ - - struct southbridge_rl5c476_config *conf = - (struct southbridge_rl5c476_config *)chip->chip_info; - - switch (pass) { - case CONF_PASS_PRE_PCI: - //rl5c476_pci_enable(conf); - break; - - case CONF_PASS_POST_PCI: - rl5c476_init(conf); - - break; - - case CONF_PASS_PRE_BOOT: - //dump_south(); - break; - - default: - /* nothing yet */ - break; - } -} +static struct device_operations ricoh_rl5c476_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .inti = rl5c476_init, + .scan_bus = pci_scan_bridge, +}; -static void enumerate(struct chip *chip) -{ - extern struct device_operations default_pci_ops_bus; - chip_enumerate(chip); - chip->dev->ops = &default_pci_ops_bus; -} +static struct pci_driver ricoh_rl5c476_driver __pci_driver = { + .ops = &ricoh_rl5c476_ops, + .vendor = PCI_VENDOR_ID_RICOH, + .device = PCI_DEVICE_ID_RICOH_RL5C476, +}; -struct chip_control southbridge_ricoh_rl5c476_control = { - .enumerate = enumerate, +struct chip_operations southbridge_ricoh_rl5c476_control = { .enable = southbridge_init, .name = "RICOH RL5C476" }; -- cgit v1.2.3