From 98d0d30f6b8237f888cd44b33292319e3c167a47 Mon Sep 17 00:00:00 2001 From: "arch import user (historical)" Date: Wed, 6 Jul 2005 17:13:46 +0000 Subject: Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-30 Creator: Yinghai Lu Nvidia Ck804 support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/nvidia/ck804/Config.lb | 14 + src/southbridge/nvidia/ck804/chip.h | 18 + src/southbridge/nvidia/ck804/ck804.c | 197 ++++++++++ src/southbridge/nvidia/ck804/ck804.h | 8 + src/southbridge/nvidia/ck804/ck804_ac97.c | 53 +++ src/southbridge/nvidia/ck804/ck804_early_setup.c | 345 +++++++++++++++++ .../nvidia/ck804/ck804_early_setup_ss.h | 206 +++++++++++ src/southbridge/nvidia/ck804/ck804_early_smbus.c | 34 ++ src/southbridge/nvidia/ck804/ck804_enable_rom.c | 19 + src/southbridge/nvidia/ck804/ck804_ht.c | 35 ++ src/southbridge/nvidia/ck804/ck804_ide.c | 78 ++++ src/southbridge/nvidia/ck804/ck804_lpc.c | 411 +++++++++++++++++++++ src/southbridge/nvidia/ck804/ck804_nic.c | 115 ++++++ src/southbridge/nvidia/ck804/ck804_pci.c | 64 ++++ src/southbridge/nvidia/ck804/ck804_pcie.c | 46 +++ src/southbridge/nvidia/ck804/ck804_reset.c | 40 ++ src/southbridge/nvidia/ck804/ck804_sata.c | 176 +++++++++ src/southbridge/nvidia/ck804/ck804_smbus.c | 102 +++++ src/southbridge/nvidia/ck804/ck804_smbus.h | 202 ++++++++++ src/southbridge/nvidia/ck804/ck804_usb.c | 36 ++ src/southbridge/nvidia/ck804/ck804_usb2.c | 44 +++ src/southbridge/nvidia/ck804/id.inc | 16 + src/southbridge/nvidia/ck804/id.lds | 6 + src/southbridge/nvidia/ck804/romstrap.inc | 42 +++ src/southbridge/nvidia/ck804/romstrap.lds | 6 + 25 files changed, 2313 insertions(+) create mode 100644 src/southbridge/nvidia/ck804/Config.lb create mode 100644 src/southbridge/nvidia/ck804/chip.h create mode 100644 src/southbridge/nvidia/ck804/ck804.c create mode 100644 src/southbridge/nvidia/ck804/ck804.h create mode 100644 src/southbridge/nvidia/ck804/ck804_ac97.c create mode 100644 src/southbridge/nvidia/ck804/ck804_early_setup.c create mode 100644 src/southbridge/nvidia/ck804/ck804_early_setup_ss.h create mode 100644 src/southbridge/nvidia/ck804/ck804_early_smbus.c create mode 100644 src/southbridge/nvidia/ck804/ck804_enable_rom.c create mode 100644 src/southbridge/nvidia/ck804/ck804_ht.c create mode 100644 src/southbridge/nvidia/ck804/ck804_ide.c create mode 100644 src/southbridge/nvidia/ck804/ck804_lpc.c create mode 100644 src/southbridge/nvidia/ck804/ck804_nic.c create mode 100644 src/southbridge/nvidia/ck804/ck804_pci.c create mode 100644 src/southbridge/nvidia/ck804/ck804_pcie.c create mode 100644 src/southbridge/nvidia/ck804/ck804_reset.c create mode 100644 src/southbridge/nvidia/ck804/ck804_sata.c create mode 100644 src/southbridge/nvidia/ck804/ck804_smbus.c create mode 100644 src/southbridge/nvidia/ck804/ck804_smbus.h create mode 100644 src/southbridge/nvidia/ck804/ck804_usb.c create mode 100644 src/southbridge/nvidia/ck804/ck804_usb2.c create mode 100644 src/southbridge/nvidia/ck804/id.inc create mode 100644 src/southbridge/nvidia/ck804/id.lds create mode 100644 src/southbridge/nvidia/ck804/romstrap.inc create mode 100644 src/southbridge/nvidia/ck804/romstrap.lds (limited to 'src/southbridge/nvidia') diff --git a/src/southbridge/nvidia/ck804/Config.lb b/src/southbridge/nvidia/ck804/Config.lb new file mode 100644 index 0000000000..a4562192ae --- /dev/null +++ b/src/southbridge/nvidia/ck804/Config.lb @@ -0,0 +1,14 @@ +config chip.h +driver ck804.o +driver ck804_usb.o +driver ck804_lpc.o +driver ck804_smbus.o +driver ck804_ide.o +driver ck804_sata.o +driver ck804_usb2.o +driver ck804_ac97.o +driver ck804_nic.o +driver ck804_pci.o +driver ck804_pcie.o +driver ck804_ht.o +object ck804_reset.o diff --git a/src/southbridge/nvidia/ck804/chip.h b/src/southbridge/nvidia/ck804/chip.h new file mode 100644 index 0000000000..a9b18fb021 --- /dev/null +++ b/src/southbridge/nvidia/ck804/chip.h @@ -0,0 +1,18 @@ +#ifndef CK804_CHIP_H +#define CK804_CHIP_H + +struct southbridge_nvidia_ck804_config +{ + unsigned int ide0_enable : 1; + unsigned int ide1_enable : 1; + unsigned int sata0_enable : 1; + unsigned int sata1_enable : 1; + unsigned long nic_rom_address; + unsigned long raid_rom_address; + unsigned int mac_eeprom_smbus; + unsigned int mac_eeprom_addr; +}; +struct chip_operations; +extern struct chip_operations southbridge_nvidia_ck804_ops; + +#endif /* CK804_CHIP_H */ diff --git a/src/southbridge/nvidia/ck804/ck804.c b/src/southbridge/nvidia/ck804/ck804.c new file mode 100644 index 0000000000..a4b77c3596 --- /dev/null +++ b/src/southbridge/nvidia/ck804/ck804.c @@ -0,0 +1,197 @@ +/* + * Copyright 2004 Tyan Computer + * by yhlu@tyan.com + */ + +#include + +#include + +#include +#include +#include +#include +#include "ck804.h" + +static uint32_t final_reg; + +static device_t find_lpc_dev( device_t dev, unsigned devfn) +{ + + device_t lpc_dev; + + lpc_dev = dev_find_slot(dev->bus->secondary, devfn); + + if ( !lpc_dev ) return lpc_dev; + + if ((lpc_dev->vendor != PCI_VENDOR_ID_NVIDIA) || ( + (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_LPC) && + (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_PRO) && + (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE)) ) { + uint32_t id; + id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); + if ( (id != (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_CK804_LPC << 16))) && + (id != (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_CK804_PRO << 16))) && + (id != (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_CK804_SLAVE << 16))) + ) { + lpc_dev = 0; + } + } + + return lpc_dev; +} + +void ck804_enable(device_t dev) +{ + device_t lpc_dev; + unsigned index = 0; + unsigned index2 = 0; + uint32_t reg_old, reg; + uint8_t byte; + unsigned deviceid; + unsigned vendorid; + + struct southbridge_nvidia_ck804_config *conf; + conf = dev->chip_info; + + unsigned devfn; + + if(dev->device==0x0000) { + vendorid = pci_read_config32(dev, PCI_VENDOR_ID); + deviceid = (vendorid>>16) & 0xffff; +// vendorid &= 0xffff; + } else { +// vendorid = dev->vendor; + deviceid = dev->device; + } + + devfn = (dev->path.u.pci.devfn) & ~7; + switch(deviceid) { + case PCI_DEVICE_ID_NVIDIA_CK804_SM: + index = 16; + break; + case PCI_DEVICE_ID_NVIDIA_CK804_USB: + devfn -= (1<<3); + index = 8; + break; + case PCI_DEVICE_ID_NVIDIA_CK804_USB2: + devfn -= (1<<3); + index = 20; + break; + case PCI_DEVICE_ID_NVIDIA_CK804_NIC: + devfn -= (9<<3); + index = 10; + dev->rom_address = conf->nic_rom_address; + break; + case PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE: + devfn -= (9<<3); + index = 10; + dev->rom_address = conf->nic_rom_address; + break; + case PCI_DEVICE_ID_NVIDIA_CK804_ACI: + devfn -= (3<<3); + index = 12; + break; + case PCI_DEVICE_ID_NVIDIA_CK804_MCI: + devfn -= (3<<3); + index = 13; + break; + case PCI_DEVICE_ID_NVIDIA_CK804_IDE: + devfn -= (5<<3); + index = 14; + dev->rom_address = conf->raid_rom_address; + break; + case PCI_DEVICE_ID_NVIDIA_CK804_SATA0: + devfn -= (6<<3); + index = 22; + break; + case PCI_DEVICE_ID_NVIDIA_CK804_SATA1: + devfn -= (7<<3); + index = 18; + break; + case PCI_DEVICE_ID_NVIDIA_CK804_PCI: + devfn -= (8<<3); + index = 15; + break; + case PCI_DEVICE_ID_NVIDIA_CK804_PCI_E: + devfn -= (0xa<<3); + index2 = 19; + break; + default: + index = 0; + } + + if(index2!=0) { + int i; + for(i=0;i<4;i++) { + lpc_dev = find_lpc_dev(dev, devfn - (i<<3)); + if(!lpc_dev) continue; + index2 -= i; + break; + } + + if ( lpc_dev ) { + reg_old = reg = pci_read_config32(lpc_dev, 0xe4); + + if (!dev->enabled) { + reg |= (1<enabled) { + final_reg |= (1 << index); + } + + if(index == 10 ) { + reg_old = pci_read_config32(lpc_dev, 0xe8); + if (final_reg != reg_old) { + pci_write_config32(lpc_dev, 0xe8, final_reg); + } + + } + +} + +struct chip_operations southbridge_nvidia_ck804_ops = { + CHIP_NAME("Nvidia ck804") + .enable_dev = ck804_enable, +}; diff --git a/src/southbridge/nvidia/ck804/ck804.h b/src/southbridge/nvidia/ck804/ck804.h new file mode 100644 index 0000000000..cad4e42d63 --- /dev/null +++ b/src/southbridge/nvidia/ck804/ck804.h @@ -0,0 +1,8 @@ +#ifndef CK804_H +#define CK804_H + +#include "chip.h" + +void ck804_enable(device_t dev); + +#endif /* CK804_H */ diff --git a/src/southbridge/nvidia/ck804/ck804_ac97.c b/src/southbridge/nvidia/ck804/ck804_ac97.c new file mode 100644 index 0000000000..36a7d3f17a --- /dev/null +++ b/src/southbridge/nvidia/ck804/ck804_ac97.c @@ -0,0 +1,53 @@ +/* + * Copyright 2004 Tyan Computer + * by yhlu@tyan.com + */ +#include +#include +#include +#include +#include +#include "ck804.h" + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +static struct device_operations ac97audio_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, +// .enable = ck804_enable, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static struct pci_driver ac97audio_driver __pci_driver = { + .ops = &ac97audio_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_ACI, +}; + + +static struct device_operations ac97modem_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, +// .enable = ck804_enable, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static struct pci_driver ac97modem_driver __pci_driver = { + .ops = &ac97modem_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_MCI, +}; diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup.c b/src/southbridge/nvidia/ck804/ck804_early_setup.c new file mode 100644 index 0000000000..0d300bbd21 --- /dev/null +++ b/src/southbridge/nvidia/ck804/ck804_early_setup.c @@ -0,0 +1,345 @@ +/* + * Copyright 2004 Tyan Computer + * by yhlu@tyan.com + */ +static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val) +{ + uint32_t dword, dword_old; + uint8_t link_type; + + dword = pci_read_config32(PCI_DEV(0,0x18+node,0), 0x98 + (linkn * 0x20)); + link_type = dword & 0xff; + + dword_old = dword = pci_read_config32(PCI_DEV(0,0x18+node,0), 0x90 + (linkn * 0x20) ); + + if ( (link_type & 0x7) == linkt ) { + dword = val; + } + + if (dword != dword_old) { + pci_write_config32(PCI_DEV(0,0x18+node,0), 0x90 + (linkn * 0x20), dword); + return 1; + } + + return 0; +} +static int set_ht_link_ck804(uint8_t ht_c_num) +{ + int reset_needed; + uint8_t i; + + reset_needed = 0; + + for (i = 0; i < ht_c_num; i++) { + uint32_t reg; + uint8_t nodeid, linkn; + uint8_t busn; + unsigned val; + + reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4); + if((reg & 3) != 3) continue; + + nodeid = ((reg & 0xf0)>>4); + linkn = ((reg & 0xf00)>>8); + busn = (reg & 0xff0000)>>16; + + reg = pci_read_config32( PCI_DEV(busn, 1, 0), PCI_VENDOR_ID); + if ( (reg & 0xffff) == 0x10de ) { + val = 0x01610169; + reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val); + } + } + + return reset_needed; +} + + +static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max) +{ + int i; + + unsigned val; + + val = inl(control); + val &= 0xfffffffe; + outl(val, control); + + outl(0, index); + + for(i = 0; i < max; i++) { + unsigned long reg; + reg = register_values[i]; + outl(reg, where); + } + val = inl(control); + val |= 1; + outl(val, control); + +} + +#define ANACTRL_IO_BASE 0x7000 +#define ANACTRL_REG_POS 0x68 + + +#define SYSCTRL_IO_BASE 0x6000 +#define SYSCTRL_REG_POS 0x64 + +/* + 16 1 1 2 :0 + 8 8 2 2 :1 + 8 8 4 :2 + 8 4 4 4 :3 + 16 4 :4 +*/ + +#ifndef CK804_PCI_E_X + #define CK804_PCI_E_X 4 +#endif + +#if CK804_NUM > 1 + #define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE+0x8000) + #define CK804B_SYSCTRL_IO_BASE (SYSCTRL_IO_BASE+0x8000) + + #ifndef CK804B_BUSN + #define CK804B_BUSN 0x80 + #endif + + #ifndef CK804B_PCI_E_X + #define CK804B_PCI_E_X 4 + #endif +#endif + +#ifndef CK804_USE_NIC + #define CK804_USE_NIC 0 +#endif + +#ifndef CK804_USE_ACI + #define CK804_USE_ACI 0 +#endif + +#define CK804_CHIP_REV 3 + +static void ck804_early_set_port(void) +{ + + static const unsigned int ctrl_devport_conf[] = { + PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, +#if CK804_NUM > 1 + PCI_ADDR(CK804B_BUSN, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), CK804B_ANACTRL_IO_BASE, +#endif + + PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, +#if CK804_NUM > 1 + PCI_ADDR(CK804B_BUSN, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), CK804B_SYSCTRL_IO_BASE, +#endif + }; + + setup_resource_map(ctrl_devport_conf, sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0])); + +} + +static void ck804_early_clear_port(void) +{ + + static const unsigned int ctrl_devport_conf_clear[] = { + PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, +#if CK804_NUM > 1 + PCI_ADDR(CK804B_BUSN, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, +#endif + + PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, +#if CK804_NUM > 1 + PCI_ADDR(CK804B_BUSN, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, +#endif + }; + + setup_resource_map(ctrl_devport_conf_clear, sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0])); + +} + +static void ck804_early_setup(void) +{ + + static const unsigned int ctrl_conf[] = { + + + + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xac), 0xffffff00, 0x00000000, + + +#if CK804_NUM > 1 + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00, +#endif + + + + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000, + + +#if CK804_NUM > 1 + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000, +#endif + + + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(0,CK804_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010, + +#if CK804_NUM > 1 + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002, + RES_PCI_IO,PCI_ADDR(CK804B_BUSN,CK804_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010, +#endif + + + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000, + +#if CK804_NUM > 1 + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000, +#endif + + + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100, + + + +#if CK804_NUM > 1 + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x20000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN,CK804_DEVN_BASE+1,0,0xe0), 0xfffffeff, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+1 , 0, 0xe8), 0xffffff00, 0x000000ff, +#endif + + + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, + + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff)|(0xff<<16)), (0x41<<16)|(0x32), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff<<16), (0xa0<<16), + +#if CK804_NUM > 1 + + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, + +#endif + + + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, +#if CK804_NUM > 1 + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, +#endif + + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10), +#if CK804_NUM > 1 + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10), +#endif + + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b, +#if CK804_NUM > 1 + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b, +#endif + + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000, + + RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804_PCI_E_X<<4)|(1<<8), +#if CK804_NUM > 1 + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804B_PCI_E_X<<4)|(1<<8), +#endif + + + + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 8, ~(0xff), ((0<<4)|(0<<2)|(0<<0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 9, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), +#if CK804_USE_NIC == 1 + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040, + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), +#endif + +#if CK804_USE_ACI == 1 + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x0d, ~(0xff), ((0<<4)|(2<<2)|(0<<0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x1a, ~(0xff), ((0<<4)|(2<<2)|(0<<0)), +#endif + +#if CK804_NUM > 1 + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2), +#endif + + +#if CK804_NUM > 1 + #if CK804_USE_NIC == 1 + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040, + RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), + RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), + RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), + #endif +#endif + + + +#ifdef CK804_MB_SETUP + CK804_MB_SETUP +#endif + + }; + + + + setup_resource_map_x(ctrl_conf, sizeof(ctrl_conf)/sizeof(ctrl_conf[0])); + + setup_ss_table(ANACTRL_IO_BASE+0x40, ANACTRL_IO_BASE+0x44, ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64); + setup_ss_table(ANACTRL_IO_BASE+0xb0, ANACTRL_IO_BASE+0xb4, ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64); + setup_ss_table(ANACTRL_IO_BASE+0xc0, ANACTRL_IO_BASE+0xc4, ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64); + +#if CK804_NUM > 1 + setup_ss_table(CK804B_ANACTRL_IO_BASE+0x40, CK804B_ANACTRL_IO_BASE+0x44, CK804B_ANACTRL_IO_BASE+0x48, pcie_ss_tbl,64); + setup_ss_table(CK804B_ANACTRL_IO_BASE+0xb0, CK804B_ANACTRL_IO_BASE+0xb4, CK804B_ANACTRL_IO_BASE+0xb8, sata_ss_tbl,64); + setup_ss_table(CK804B_ANACTRL_IO_BASE+0xc0, CK804B_ANACTRL_IO_BASE+0xc4, CK804B_ANACTRL_IO_BASE+0xc8, cpu_ss_tbl,64); +#endif + +#if 0 + dump_io_resources(ANACTRL_IO_BASE); + dump_io_resources(SYSCTRL_IO_BASE); +#endif + +} + +static int ck804_early_setup_x(void) +{ + ck804_early_set_port(); + ck804_early_setup(); + ck804_early_clear_port(); + return set_ht_link_ck804(4); +} diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h b/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h new file mode 100644 index 0000000000..0ab7939f3a --- /dev/null +++ b/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h @@ -0,0 +1,206 @@ +/* + * Copyright 2004 Tyan Computer + * by yhlu@tyan.com + */ + +static const unsigned int pcie_ss_tbl[] = { + 0x0C504103f, + 0x0C504103f, + 0x0C504103f, + 0x0C5042040, + 0x0C5042040, + 0x0C5042040, + 0x0C5043041, + 0x0C5043041, + 0x0C5043041, + 0x0C5043041, + 0x0C5044042, + 0x0C5044042, + 0x0C5044042, + 0x0C5045043, + 0x0C5045043, + 0x0C5045043, + 0x0C5045043, + 0x0C5045043, + 0x0C5046044, + 0x0C5046044, + 0x0C5046044, + 0x0C5046044, + 0x0C5047045, + 0x0C5047045, + 0x0C5047045, + 0x0C5047045, + 0x0C5047045, + 0x0C5048046, + 0x0C5048046, + 0x0C5048046, + 0x0C5048046, + 0x0C5049047, + 0x0C5049047, + 0x0C5049047, + 0x0C504a048, + 0x0C504a048, + 0x0C504b049, + 0x0C504b049, + 0x0C504a048, + 0x0C504a048, + 0x0C5049047, + 0x0C5049047, + 0x0C5048046, + 0x0C5048046, + 0x0C5048046, + 0x0C5047045, + 0x0C5047045, + 0x0C5047045, + 0x0C5047045, + 0x0C5047045, + 0x0C5046044, + 0x0C5046044, + 0x0C5046044, + 0x0C5046044, + 0x0C5045043, + 0x0C5045043, + 0x0C5045043, + 0x0C5044042, + 0x0C5044042, + 0x0C5044042, + 0x0C5043041, + 0x0C5043041, + 0x0C5042040, + 0x0C5042040, +}; +static const unsigned int sata_ss_tbl[] = { + 0x0c9044042, + 0x0c9044042, + 0x0c9044042, + 0x0c9045043, + 0x0c9045043, + 0x0c9045043, + 0x0c9045043, + 0x0c9045043, + 0x0c9046044, + 0x0c9046044, + 0x0c9046044, + 0x0c9046044, + 0x0c9047045, + 0x0c9047045, + 0x0c9047045, + 0x0c9047045, + 0x0c9047045, + 0x0c9048046, + 0x0c9048046, + 0x0c9048046, + 0x0c9048046, + 0x0c9049047, + 0x0c9049047, + 0x0c9049047, + 0x0c9049047, + 0x0c904a048, + 0x0c904a048, + 0x0c904a048, + 0x0c904a048, + 0x0c904b049, + 0x0c904b049, + 0x0c904b049, + 0x0c904b049, + 0x0c904b049, + 0x0c904b049, + 0x0c904a048, + 0x0c904a048, + 0x0c904a048, + 0x0c904a048, + 0x0c9049047, + 0x0c9049047, + 0x0c9049047, + 0x0c9049047, + 0x0c9048046, + 0x0c9048046, + 0x0c9048046, + 0x0c9048046, + 0x0c9047045, + 0x0c9047045, + 0x0c9047045, + 0x0c9047045, + 0x0c9047045, + 0x0c9046044, + 0x0c9046044, + 0x0c9046044, + 0x0c9046044, + 0x0c9045043, + 0x0c9045043, + 0x0c9045043, + 0x0c9045043, + 0x0c9045043, + 0x0c9044042, + 0x0c9044042, + 0x0c9044042, +}; + +static const unsigned int cpu_ss_tbl[] = { + 0x0C5038036, + 0x0C5038036, + 0x0C5038036, + 0x0C5037035, + 0x0C5037035, + 0x0C5037035, + 0x0C5037035, + 0x0C5036034, + 0x0C5036034, + 0x0C5036034, + 0x0C5036034, + 0x0C5036034, + 0x0C5035033, + 0x0C5035033, + 0x0C5035033, + 0x0C5035033, + 0x0C5035033, + 0x0C5035033, + 0x0C5034032, + 0x0C5034032, + 0x0C5034032, + 0x0C5034032, + 0x0C5034032, + 0x0C5034032, + 0x0C5035033, + 0x0C5035033, + 0x0C5035033, + 0x0C5035033, + 0x0C5035033, + 0x0C5036034, + 0x0C5036034, + 0x0C5036034, + 0x0C5036034, + 0x0C5036034, + 0x0C5037035, + 0x0C5037035, + 0x0C5037035, + 0x0C5037035, + 0x0C5038036, + 0x0C5038036, + 0x0C5038036, + 0x0C5038036, + 0x0C5039037, + 0x0C5039037, + 0x0C5039037, + 0x0C5039037, + 0x0C503a038, + 0x0C503a038, + 0x0C503a038, + 0x0C503a038, + 0x0C503b039, + 0x0C503b039, + 0x0C503b039, + 0x0C503b039, + 0x0C503b039, + 0x0C503a038, + 0x0C503a038, + 0x0C503a038, + 0x0C503a038, + 0x0C503a038, + 0x0C5039037, + 0x0C5039037, + 0x0C5039037, + 0x0C5039037, +}; + + diff --git a/src/southbridge/nvidia/ck804/ck804_early_smbus.c b/src/southbridge/nvidia/ck804/ck804_early_smbus.c new file mode 100644 index 0000000000..29f97d0ecf --- /dev/null +++ b/src/southbridge/nvidia/ck804/ck804_early_smbus.c @@ -0,0 +1,34 @@ +/* + * Copyright 2004 Tyan Computer + * by yhlu@tyan.com + */ + +#include "ck804_smbus.h" + +#define SMBUS_IO_BASE 0x1000 + +static void enable_smbus(void) +{ + device_t dev; + dev = pci_locate_device(PCI_ID(0x10de, 0x0052), 0); + if (dev == PCI_DEV_INVALID) { + die("SMBUS controller not found\r\n"); + } + + print_debug("SMBus controller enabled\r\n"); + /* set smbus iobase */ + pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); + /* Set smbus iospace enable */ + pci_write_config16(dev, 0x4, 0x01); + /* clear any lingering errors, so the transaction will run */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); +} + +static int smbus_read_byte(unsigned device, unsigned address) +{ + return do_smbus_read_byte(SMBUS_IO_BASE, device, address); +} +static int smbus_write_byte(unsigned device, unsigned address, unsigned char val) +{ + return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); +} diff --git a/src/southbridge/nvidia/ck804/ck804_enable_rom.c b/src/southbridge/nvidia/ck804/ck804_enable_rom.c new file mode 100644 index 0000000000..48ce689358 --- /dev/null +++ b/src/southbridge/nvidia/ck804/ck804_enable_rom.c @@ -0,0 +1,19 @@ +/* + * Copyright 2004 Tyan Computer + * by yhlu@tyan.com + */ + +static void ck804_enable_rom(void) +{ + unsigned char byte; + device_t addr; + + /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */ + /* Locate the ck804 LPC */ + addr = PCI_DEV(0, (CK804_DEVN_BASE+1), 0); + + /* Set the 4MB enable bit bit */ + byte = pci_read_config8(addr, 0x88); + byte |= 0x80; + pci_write_config8(addr, 0x88, byte); +} diff --git a/src/southbridge/nvidia/ck804/ck804_ht.c b/src/southbridge/nvidia/ck804/ck804_ht.c new file mode 100644 index 0000000000..d8a82a3e34 --- /dev/null +++ b/src/southbridge/nvidia/ck804/ck804_ht.c @@ -0,0 +1,35 @@ +/* + * Copyright 2004 Tyan Computer + * by yhlu@tyan.com + */ +#include +#include +#include +#include +#include +#include "ck804.h" + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +static struct device_operations ht_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static struct pci_driver ht_driver __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_HT, +}; + diff --git a/src/southbridge/nvidia/ck804/ck804_ide.c b/src/southbridge/nvidia/ck804/ck804_ide.c new file mode 100644 index 0000000000..f927f2a7cc --- /dev/null +++ b/src/southbridge/nvidia/ck804/ck804_ide.c @@ -0,0 +1,78 @@ +/* + * Copyright 2004 Tyan Computer + * by yhlu@tyan.com + */ + +#include +#include +#include +#include +#include +#include "ck804.h" + +static void ide_init(struct device *dev) +{ + struct southbridge_nvidia_ck804_config *conf; + /* Enable ide devices so the linux ide driver will work */ + uint32_t dword; + uint16_t word; + uint8_t byte; + conf = dev->chip_info; + + word = pci_read_config16(dev, 0x50); + /* Ensure prefetch is disabled */ + word &= ~((1 << 15) | (1 << 13)); + if (conf->ide1_enable) { + /* Enable secondary ide interface */ + word |= (1<<0); + printk_debug("IDE1 \t"); + } + if (conf->ide0_enable) { + /* Enable primary ide interface */ + word |= (1<<1); + printk_debug("IDE0\n"); + } + + word |= (1<<12); + word |= (1<<14); + + pci_write_config16(dev, 0x50, word); + + + byte = 0x20 ; // Latency: 64-->32 + pci_write_config8(dev, 0xd, byte); + + dword = pci_read_config32(dev, 0xf8); + dword |= 12; + pci_write_config32(dev, 0xf8, dword); +#if CONFIG_PCI_ROM_RUN == 1 + pci_dev_init(dev); +#endif + +} + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +static struct device_operations ide_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init, + .scan_bus = 0, +// .enable = ck804_enable, + .ops_pci = &lops_pci, +}; + +static struct pci_driver ide_driver __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_IDE, +}; + diff --git a/src/southbridge/nvidia/ck804/ck804_lpc.c b/src/southbridge/nvidia/ck804/ck804_lpc.c new file mode 100644 index 0000000000..ea37b241d5 --- /dev/null +++ b/src/southbridge/nvidia/ck804/ck804_lpc.c @@ -0,0 +1,411 @@ +/* + * (C) 2003 Linux Networx, SuSE Linux AG + * Copyright 2004 Tyan Computer + * by yhlu@tyan.com + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ck804.h" + +#define CK804_CHIP_REV 2 + +#define NMI_OFF 0 + +struct ioapicreg { + unsigned int reg; + unsigned int value_low, value_high; +}; + +static struct ioapicreg ioapicregvalues[] = { +#define ALL (0xff << 24) +#define NONE (0) +#define DISABLED (1 << 16) +#define ENABLED (0 << 16) +#define TRIGGER_EDGE (0 << 15) +#define TRIGGER_LEVEL (1 << 15) +#define POLARITY_HIGH (0 << 13) +#define POLARITY_LOW (1 << 13) +#define PHYSICAL_DEST (0 << 11) +#define LOGICAL_DEST (1 << 11) +#define ExtINT (7 << 8) +#define NMI (4 << 8) +#define SMI (2 << 8) +#define INT (1 << 8) + /* IO-APIC virtual wire mode configuration */ + /* mask, trigger, polarity, destination, delivery, vector */ + { 0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE}, + { 1, DISABLED, NONE}, + { 2, DISABLED, NONE}, + { 3, DISABLED, NONE}, + { 4, DISABLED, NONE}, + { 5, DISABLED, NONE}, + { 6, DISABLED, NONE}, + { 7, DISABLED, NONE}, + { 8, DISABLED, NONE}, + { 9, DISABLED, NONE}, + { 10, DISABLED, NONE}, + { 11, DISABLED, NONE}, + { 12, DISABLED, NONE}, + { 13, DISABLED, NONE}, + { 14, DISABLED, NONE}, + { 15, DISABLED, NONE}, + { 16, DISABLED, NONE}, + { 17, DISABLED, NONE}, + { 18, DISABLED, NONE}, + { 19, DISABLED, NONE}, + { 20, DISABLED, NONE}, + { 21, DISABLED, NONE}, + { 22, DISABLED, NONE}, + { 23, DISABLED, NONE}, + /* Be careful and don't write past the end... */ +}; + +static void setup_ioapic(unsigned long ioapic_base) +{ + int i; + unsigned long value_low, value_high; +// unsigned long ioapic_base = 0xfec00000; + volatile unsigned long *l; + struct ioapicreg *a = ioapicregvalues; + + l = (unsigned long *) ioapic_base; + + for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]); + i++, a++) { + l[0] = (a->reg * 2) + 0x10; + l[4] = a->value_low; + value_low = l[4]; + l[0] = (a->reg *2) + 0x11; + l[4] = a->value_high; + value_high = l[4]; + if ((i==0) && (value_low == 0xffffffff)) { + printk_warning("IO APIC not responding.\n"); + return; + } + printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n", + a->reg, a->value_low, a->value_high); + } +} + +// 0x7a or e3 +#define PREVIOUS_POWER_STATE 0x7A + +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 +#define SLOW_CPU_OFF 0 +#define SLOW_CPU__ON 1 + +#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON +#endif + +static void lpc_common_init(device_t dev) +{ + uint8_t byte; + uint32_t dword; + + /* IO APIC initialization */ + byte = pci_read_config8(dev, 0x74); + byte |= (1<<0); // enable APIC + pci_write_config8(dev, 0x74, byte); + dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14 + + setup_ioapic(dword); + +#if 1 + dword = pci_read_config32(dev, 0xe4); + dword |= (1<<23); + pci_write_config32(dev, 0xe4, dword); +#endif + +} + +static void lpc_slave_init(device_t dev) +{ + lpc_common_init(dev); +} + +static void rom_dummy_write(device_t dev){ + uint8_t old, new; + uint8_t *p; + + old = pci_read_config8(dev, 0x88); + new = old | 0xc0; + if (new != old) { + pci_write_config8(dev, 0x88, new); + } + // enable write + old = pci_read_config8(dev, 0x6d); + new = old | 0x01; + if (new != old) { + pci_write_config8(dev, 0x6d, new); + } + + /* dummy write */ + p = (uint8_t *)0xffffffe0; + old = 0; + *p = old; + old = *p; + + // disable write + old = pci_read_config8(dev, 0x6d); + new = old & 0xfe; + if (new != old) { + pci_write_config8(dev, 0x6d, new); + + } + +} +#if 0 +static void enable_hpet(struct device *dev) +{ + unsigned long hpet_address; + + pci_write_config32(dev,0x44, 0xfed00001); + hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe; + printk_debug("enabling HPET @0x%x\n", hpet_address); +} +#endif + +static void lpc_init(device_t dev) +{ + uint8_t byte; + uint8_t byte_old; + int on; + int nmi_option; + + lpc_common_init(dev); + +#if CK804_CHIP_REV==1 + if(dev->bus->secondary!=1) return; +#endif + +#if 0 + /* posted memory write enable */ + byte = pci_read_config8(dev, 0x46); + pci_write_config8(dev, 0x46, byte | (1<<0)); + +#endif + /* power after power fail */ + + on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + get_option(&on, "power_on_after_fail"); + byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); + byte &= ~0x40; + if (!on) { + byte |= 0x40; + } + pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); + printk_info("set power %s after power fail\n", on?"on":"off"); + + /* Throttle the CPU speed down for testing */ + on = SLOW_CPU_OFF; + get_option(&on, "slow_cpu"); + if(on) { + uint16_t pm10_bar; + uint32_t dword; + pm10_bar = (pci_read_config16(dev, 0x60)&0xff00); + outl(((on<<1)+0x10) ,(pm10_bar + 0x10)); + dword = inl(pm10_bar + 0x10); + on = 8-on; + printk_debug("Throttling CPU %2d.%1.1d percent.\n", + (on*12)+(on>>1),(on&1)*5); + } + +#if 0 +// default is enabled + /* Enable Port 92 fast reset */ + byte = pci_read_config8(dev, 0xe8); + byte |= ~(1 << 3); + pci_write_config8(dev, 0xe8, byte); +#endif + + /* Enable Error reporting */ + /* Set up sync flood detected */ + byte = pci_read_config8(dev, 0x47); + byte |= (1 << 1); + pci_write_config8(dev, 0x47, byte); + + /* Set up NMI on errors */ + byte = inb(0x70); // RTC70 + byte_old = byte; + nmi_option = NMI_OFF; + get_option(&nmi_option, "nmi"); + if (nmi_option) { + byte &= ~(1 << 7); /* set NMI */ + } else { + byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW + } + if( byte != byte_old) { + outb(0x70, byte); + } + + /* Initialize the real time clock */ + rtc_init(0); + + /* Initialize isa dma */ + isa_dma_init(); + + /* Initialize the High Precision Event Timers */ +// enable_hpet(dev); + + rom_dummy_write(dev); + +} + +static void ck804_lpc_read_resources(device_t dev) +{ + struct resource *res; + unsigned long index; + + /* Get the normal pci resources of this device */ + pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP + + /* Get Resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL */ + for (index = 0x60; index <= 0x68; index+=4) { // We got another 3. + pci_get_resource(dev, index); + } + compact_resources(dev); + + /* Add an extra subtractive resource for both memory and I/O */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + +} + +/** + * @brief Enable resources for children devices + * + * @param dev the device whos children's resources are to be enabled + * + * This function is call by the global enable_resources() indirectly via the + * device_operation::enable_resources() method of devices. + * + * Indirect mutual recursion: + * enable_childrens_resources() -> enable_resources() + * enable_resources() -> device_operation::enable_resources() + * device_operation::enable_resources() -> enable_children_resources() + */ +static void ck804_lpc_enable_childrens_resources(device_t dev) +{ + unsigned link; + uint32_t reg, reg_var[4]; + int i; + int var_num = 0; + + reg = pci_read_config32(dev, 0xa0); + + for (link = 0; link < dev->links; link++) { + device_t child; + for (child = dev->link[link].children; child; child = child->sibling) { + enable_resources(child); + if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) { + for(i=0;iresources;i++) { + struct resource *res; + unsigned long base, end; // don't need long long + res = &child->resource[i]; + if(!(res->flags & IORESOURCE_IO)) continue; + base = res->base; + end = resource_end(res); + printk_debug("ck804 lpc decode:%s, base=0x%08x, end=0x%08x\r\n",dev_path(child),base, end); + switch(base) { + case 0x3f8: // COM1 + reg |= (1<<0); break; + case 0x2f8: // COM2 + reg |= (1<<1); break; + case 0x378: // Parallal 1 + reg |= (1<<24); break; + case 0x3f0: // FD0 + reg |= (1<<20); break; + case 0x220: // Aduio 0 + reg |= (1<<8); break; + case 0x300: // Midi 0 + reg |= (1<<12); break; + } + if( base == 0x290 || base >= 0x400) { + if(var_num>=4) continue; // only 4 var ; compact them ? + reg |= (1<<(28+var_num)); + reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16); + } + } + } + } + } + pci_write_config32(dev, 0xa0, reg); + for(i=0;i +#include +#include +#include +#include +#include +#include +#include "ck804.h" + + +static void nic_init(struct device *dev) +{ + uint32_t dword, old; + uint32_t mac_h, mac_l; + int eeprom_valid = 0; + struct southbridge_nvidia_ck804_config *conf; + + static uint32_t nic_index = 0; + + + old = dword = pci_read_config32(dev, 0x30); + dword &= ~(0xf); + dword |= 0xf; + if(old != dword) { + pci_write_config32(dev, 0x30 , dword); + } + + conf = dev->chip_info; + + if(conf->mac_eeprom_smbus != 0) { +// read MAC address from EEPROM at first + struct device *dev_eeprom; + dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr); + + if(dev_eeprom) { + // if that is valid we will use that + unsigned char dat[6]; + int status; + int i; + for(i=0;i<6;i++) { + status = smbus_read_byte(dev_eeprom, i); + if(status < 0) break; + dat[i] = status & 0xff; + } + if(status >= 0) { + mac_l = 0; + for(i=3;i>=0;i--) { + mac_l <<= 8; + mac_l += dat[i]; + } + if(mac_l != 0xffffffff) { + mac_l += nic_index; + mac_h = 0; + for(i=5;i>=4;i--) { + mac_h <<= 8; + mac_h += dat[i]; + } + eeprom_valid = 1; + } + } + } + } +// if that is invalid we will read that from romstrap + if(!eeprom_valid) { + unsigned long mac_pos; + mac_pos = 0xffffffd0; // refer to romstrap.inc and romstrap.lds + mac_l = readl(mac_pos) + nic_index; + mac_h = readl(mac_pos + 4); + } + +// set that into NIC + pci_write_config32(dev, 0xa8, mac_l); + pci_write_config32(dev, 0xac, mac_h); + + nic_index++; + +#if CONFIG_PCI_ROM_RUN == 1 + pci_dev_init(dev);// it will init option rom +#endif + +} + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +static struct device_operations nic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = nic_init, + .scan_bus = 0, +// .enable = ck804_enable, + .ops_pci = &lops_pci, +}; +static struct pci_driver nic_driver __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_NIC, +}; +static struct pci_driver nic_bridge_driver __pci_driver = { + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE, +}; diff --git a/src/southbridge/nvidia/ck804/ck804_pci.c b/src/southbridge/nvidia/ck804/ck804_pci.c new file mode 100644 index 0000000000..34e2e9c970 --- /dev/null +++ b/src/southbridge/nvidia/ck804/ck804_pci.c @@ -0,0 +1,64 @@ +/* + * Copyright 2004 Tyan Computer + * by yhlu@tyan.com + */ + +#include +#include +#include +#include +#include +#include "ck804.h" + +static void pci_init(struct device *dev) +{ + + uint32_t dword; + + /* System error enable */ + dword = pci_read_config32(dev, 0x04); + dword |= (1<<8); /* System error enable */ + dword |= (1<<30); /* Clear possible errors */ + pci_write_config32(dev, 0x04, dword); + +#if 0 + word = pci_read_config16(dev, 0x48); + word |= (1<<0); /* MRL2MRM */ + word |= (1<<2); /* MR2MRM */ + pci_write_config16(dev, 0x48, word); +#endif + +#if 1 + dword = pci_read_config32(dev, 0x4c); + dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/ + pci_write_config32(dev, 0x4c, dword); +#endif + + dword = dev_root.resource[1].base & (0xffff0000UL); + printk_debug("dev_root mem base = 0x%010Lx\n", dev_root.resource[1].base); + + printk_debug("[0x50] <-- 0x%08x\n", dword); + pci_write_config32(dev, 0x50, dword); //TOM + +} + +static struct pci_operations lops_pci = { + .set_subsystem = 0, +}; + +static struct device_operations pci_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pci_init, + .scan_bus = pci_scan_bridge, +// .enable = ck804_enable, + .ops_pci = &lops_pci, +}; + +static struct pci_driver pci_driver __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_PCI, +}; + diff --git a/src/southbridge/nvidia/ck804/ck804_pcie.c b/src/southbridge/nvidia/ck804/ck804_pcie.c new file mode 100644 index 0000000000..3a2ec20a25 --- /dev/null +++ b/src/southbridge/nvidia/ck804/ck804_pcie.c @@ -0,0 +1,46 @@ +/* + * Copyright 2004 Tyan Computer + * by yhlu@tyan.com + */ + +#include +#include +#include +#include +#include +#include "ck804.h" + +static void pcie_init(struct device *dev) +{ + + /* Enable pci error detecting */ + uint32_t dword; + + /* System error enable */ + dword = pci_read_config32(dev, 0x04); + dword |= (1<<8); /* System error enable */ + dword |= (1<<30); /* Clear possible errors */ + pci_write_config32(dev, 0x04, dword); + +} + +static struct pci_operations lops_pci = { + .set_subsystem = 0, +}; + +static struct device_operations pcie_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pcie_init, + .scan_bus = pci_scan_bridge, +// .enable = ck804_enable, + .ops_pci = &lops_pci, +}; + +static struct pci_driver pcie_driver __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_PCI_E, +}; + diff --git a/src/southbridge/nvidia/ck804/ck804_reset.c b/src/southbridge/nvidia/ck804/ck804_reset.c new file mode 100644 index 0000000000..bd1bc5378c --- /dev/null +++ b/src/southbridge/nvidia/ck804/ck804_reset.c @@ -0,0 +1,40 @@ +/* + * Copyright 2004 Tyan Computer + * by yhlu@tyan.com + */ + +#include + +#define PCI_DEV(BUS, DEV, FN) ( \ + (((BUS) & 0xFF) << 16) | \ + (((DEV) & 0x1f) << 11) | \ + (((FN) & 0x7) << 8)) + +typedef unsigned device_t; + +static void pci_write_config32(device_t dev, unsigned where, unsigned value) +{ + unsigned addr; + addr = dev | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outl(value, 0xCFC); +} + +static unsigned pci_read_config32(device_t dev, unsigned where) +{ + unsigned addr; + addr = dev | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + return inl(0xCFC); +} + +#include "../../../northbridge/amd/amdk8/reset_test.c" + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9 */ + outb((0 <<3)|(0<<2)|(1<<1), 0xcf9); + outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); +} + diff --git a/src/southbridge/nvidia/ck804/ck804_sata.c b/src/southbridge/nvidia/ck804/ck804_sata.c new file mode 100644 index 0000000000..97744f6823 --- /dev/null +++ b/src/southbridge/nvidia/ck804/ck804_sata.c @@ -0,0 +1,176 @@ +/* + * Copyright 2004 Tyan Computer + * by yhlu@tyan.com + */ +#include +#include +#include +#include +#include +#include +#include "ck804.h" + + +static void sata_com_reset(struct device *dev, unsigned reset) +// reset = 1 : reset +// reset = 0 : clear +{ + uint32_t *base; + uint32_t dword; + int loop; + + base = (uint32_t *) pci_read_config32(dev, 0x24); + + printk_debug("base = %08x\r\n", base); + + if(reset) { + *(base + 4) = 0xffffffff; + *(base + 0x44) = 0xffffffff; + } + + dword = *(base +8); + dword &= ~(0xf); + dword |= reset; + + *(base + 8) = dword; + *(base + 0x48) = dword; + +#if 0 + udelay(1000); + dword &= ~(0xf); + *(base + 8) = dword; + *(base + 0x48) = dword; +#endif + + + + if(reset) return; + + dword = *(base+ 0); + printk_debug("*(base+0)=%08x\r\n",dword); + if(dword == 0x113) { + loop = 200000;// 2 + do { + dword = *(base + 4); + if((dword & 0x10000)!=0) break; + udelay(10); + } while (--loop>0); + printk_debug("loop=%d, *(base+4)=%08x\r\n",loop, dword); + } + + + dword = *(base+ 0x40); + printk_debug("*(base+0x40)=%08x\r\n",dword); + if(dword == 0x113) { + loop = 200000;//2 + do { + dword = *(base + 0x44); + if((dword & 0x10000)!=0) break; + udelay(10); + } while (--loop>0); + printk_debug("loop=%d, *(base+0x44)=%08x\r\n",loop, dword); + } + + +} + +static void sata_init(struct device *dev) +{ + + uint32_t dword; + + struct southbridge_nvidia_ck804_config *conf; + conf = dev->chip_info; + + dword = pci_read_config32(dev, 0x50); + /* Ensure prefetch is disabled */ + dword &= ~((1 << 15) | (1 << 13)); + if (conf->sata1_enable) { + /* Enable secondary SATA interface */ + dword |= (1<<0); + printk_debug("SATA S \t"); + } + if (conf->sata0_enable) { + /* Enable primary SATA interface */ + dword |= (1<<1); + printk_debug("SATA P \n"); + } +// write back + dword |= (1<<12); + dword |= (1<<14); + +#if 1 +// ADMA + dword |= (1<<16); + dword |= (1<<17); +#endif + +#if 1 +//DO NOT relay OK and PAGE_FRNDLY_DTXFR_CNT. + dword &= ~(0x1f<<24); + dword |= (0x15<<24); +#endif + pci_write_config32(dev, 0x50, dword); + +#if 1 +//SLUMBER_DURING_D3. + dword = pci_read_config32(dev, 0x7c); + dword &= ~(1<<4); + pci_write_config32(dev, 0x7c, dword); + + dword = pci_read_config32(dev, 0xd0); + dword &= ~(0xff<<24); + dword |= (0x68<<24); + pci_write_config32(dev, 0xd0, dword); + + dword = pci_read_config32(dev, 0xe0); + dword &= ~(0xff<<24); + dword |= (0x68<<24); + pci_write_config32(dev, 0xe0, dword); +#endif + + dword = pci_read_config32(dev, 0xf8); + dword |= 2; + pci_write_config32(dev, 0xf8, dword); + +#if 0 + dword = pci_read_config32(dev, 0xac); + dword &= ~((1<<13)|(1<<14)); + dword |= (1<<13)|(0<<14); + pci_write_config32(dev, 0xac, dword); + + sata_com_reset(dev, 1); // for discover some s-atapi device +#endif + +} + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, +// .enable = ck804_enable, + .init = sata_init, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static struct pci_driver sata0_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_SATA0, +}; + +static struct pci_driver sata1_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_SATA1, +}; diff --git a/src/southbridge/nvidia/ck804/ck804_smbus.c b/src/southbridge/nvidia/ck804/ck804_smbus.c new file mode 100644 index 0000000000..0fce134a1c --- /dev/null +++ b/src/southbridge/nvidia/ck804/ck804_smbus.c @@ -0,0 +1,102 @@ +/* + * Copyright 2004 Tyan Computer + * by yhlu@tyan.com + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include "ck804.h" +#include "ck804_smbus.h" + +static int lsmbus_recv_byte(device_t dev) +{ + unsigned device; + struct resource *res; + struct bus *pbus; + + device = dev->path.u.i2c.device; + pbus = get_pbus_smbus(dev); + + res = find_resource(pbus->dev, 0x20 + (pbus->link * 4)); + + return do_smbus_recv_byte(res->base, device); +} + +static int lsmbus_send_byte(device_t dev, uint8_t val) +{ + unsigned device; + struct resource *res; + struct bus *pbus; + + device = dev->path.u.i2c.device; + pbus = get_pbus_smbus(dev); + + res = find_resource(pbus->dev, 0x20 + (pbus->link * 4)); + + return do_smbus_send_byte(res->base, device, val); +} + +static int lsmbus_read_byte(device_t dev, uint8_t address) +{ + unsigned device; + struct resource *res; + struct bus *pbus; + + device = dev->path.u.i2c.device; + pbus = get_pbus_smbus(dev); + + res = find_resource(pbus->dev, 0x20 + (pbus->link * 4)); + + return do_smbus_read_byte(res->base, device, address); +} + +static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) +{ + unsigned device; + struct resource *res; + struct bus *pbus; + + device = dev->path.u.i2c.device; + pbus = get_pbus_smbus(dev); + + res = find_resource(pbus->dev, 0x20 + (pbus->link * 4)); + + return do_smbus_write_byte(res->base, device, address, val); +} +static struct smbus_bus_operations lops_smbus_bus = { + .recv_byte = lsmbus_recv_byte, + .send_byte = lsmbus_send_byte, + .read_byte = lsmbus_read_byte, + .write_byte = lsmbus_write_byte, +}; + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; +static struct device_operations smbus_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = scan_static_bus, +// .enable = ck804_enable, + .ops_pci = &lops_pci, + .ops_smbus_bus = &lops_smbus_bus, +}; +static struct pci_driver smbus_driver __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_SM, +}; + diff --git a/src/southbridge/nvidia/ck804/ck804_smbus.h b/src/southbridge/nvidia/ck804/ck804_smbus.h new file mode 100644 index 0000000000..079007836f --- /dev/null +++ b/src/southbridge/nvidia/ck804/ck804_smbus.h @@ -0,0 +1,202 @@ +/* + * Copyright 2004 Tyan Computer + * by yhlu@tyan.com + */ +#include + +#define SMBHSTSTAT 0x1 +#define SMBHSTPRTCL 0x0 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x2 +#define SMBHSTDAT0 0x4 +#define SMBHSTDAT1 0x5 + +/* Between 1-10 seconds, We should never timeout normally + * Longer than this is just painful when a timeout condition occurs. + */ +#define SMBUS_TIMEOUT (100*1000*10) + +static inline void smbus_delay(void) +{ + outb(0x80, 0x80); +} + +static int smbus_wait_until_ready(unsigned smbus_io_base) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + val = inb(smbus_io_base + SMBHSTSTAT); + if ((val & 0x1f) == 0) { + break; + } + if(loops == (SMBUS_TIMEOUT / 2)) { + outb((val & 0x1f),smbus_io_base + SMBHSTSTAT); + } + } while(--loops); + return loops?0:-2; +} + +static int smbus_wait_until_done(unsigned smbus_io_base) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + + val = inb(smbus_io_base + SMBHSTSTAT); + if ( (val & 0xff) != 0) { + break; + } + } while(--loops); + return loops?0:-3; +} +static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) +{ + unsigned char global_status_register; + unsigned char byte; +#if 0 +// Don't need, when you write to PRTCL, the status will be cleared automatically + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; + } +#endif + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD); + smbus_delay(); + /* set the command/address... */ + outb(0, smbus_io_base + SMBHSTCMD); + smbus_delay(); + /* byte data recv */ + outb(0x05, smbus_io_base + SMBHSTPRTCL); + smbus_delay(); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; + } + + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ + + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTDAT0); + + if (global_status_register != 0x80) { // lose check, otherwise it should be 0 + return -1; + } + return byte; +} +static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val) +{ + unsigned global_status_register; + +#if 0 +// Don't need, when you write to PRTCL, the status will be cleared automatically + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; + } +#endif + + outb(val, smbus_io_base + SMBHSTDAT0); + smbus_delay(); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); + smbus_delay(); + + outb(0, smbus_io_base + SMBHSTCMD); + smbus_delay(); + + /* set up for a byte data write */ + outb(0x04, smbus_io_base + SMBHSTPRTCL); + smbus_delay(); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; + } + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + + if (global_status_register != 0x80) { + return -1; + } + return 0; +} +static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) +{ + unsigned char global_status_register; + unsigned char byte; +#if 0 +// Don't need, when you write to PRTCL, the status will be cleared automatically + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; + } +#endif + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD); + smbus_delay(); + /* set the command/address... */ + outb(address & 0xff, smbus_io_base + SMBHSTCMD); + smbus_delay(); + /* byte data read */ + outb(0x07, smbus_io_base + SMBHSTPRTCL); + smbus_delay(); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; + } + + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ + + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTDAT0); + + if (global_status_register != 0x80) { // lose check, otherwise it should be 0 + return -1; + } + return byte; +} + + +static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val) +{ + unsigned global_status_register; + +#if 0 +// Don't need, when you write to PRTCL, the status will be cleared automatically + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; + } +#endif + + outb(val, smbus_io_base + SMBHSTDAT0); + smbus_delay(); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); + smbus_delay(); + + outb(address & 0xff, smbus_io_base + SMBHSTCMD); + smbus_delay(); + + /* set up for a byte data write */ + outb(0x06, smbus_io_base + SMBHSTPRTCL); + smbus_delay(); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; + } + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + + if (global_status_register != 0x80) { + return -1; + } + return 0; +} diff --git a/src/southbridge/nvidia/ck804/ck804_usb.c b/src/southbridge/nvidia/ck804/ck804_usb.c new file mode 100644 index 0000000000..a839b7e338 --- /dev/null +++ b/src/southbridge/nvidia/ck804/ck804_usb.c @@ -0,0 +1,36 @@ +/* + * Copyright 2004 Tyan Computer + * by yhlu@tyan.com + */ +#include +#include +#include +#include +#include +#include "ck804.h" + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +static struct device_operations usb_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, +// .enable = ck804_enable, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static struct pci_driver usb_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_USB, +}; + diff --git a/src/southbridge/nvidia/ck804/ck804_usb2.c b/src/southbridge/nvidia/ck804/ck804_usb2.c new file mode 100644 index 0000000000..c3d83684b5 --- /dev/null +++ b/src/southbridge/nvidia/ck804/ck804_usb2.c @@ -0,0 +1,44 @@ +/* + * Copyright 2004 Tyan Computer + * by yhlu@tyan.com + */ +#include +#include +#include +#include +#include +#include "ck804.h" + +static void usb2_init(struct device *dev) +{ + + uint32_t dword; + dword = pci_read_config32(dev, 0xf8); + dword |= 40; + pci_write_config32(dev, 0xf8, dword); +} + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +static struct device_operations usb2_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb2_init, +// .enable = ck804_enable, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static struct pci_driver usb2_driver __pci_driver = { + .ops = &usb2_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_USB2, +}; diff --git a/src/southbridge/nvidia/ck804/id.inc b/src/southbridge/nvidia/ck804/id.inc new file mode 100644 index 0000000000..438065a5c0 --- /dev/null +++ b/src/southbridge/nvidia/ck804/id.inc @@ -0,0 +1,16 @@ + + .section ".id", "a", @progbits + + .globl __id_start +__id_start: +vendor: + .asciz MAINBOARD_VENDOR +part: + .asciz MAINBOARD_PART_NUMBER +.long __id_end + 0x80 - vendor /* Reverse offset to the vendor id */ +.long __id_end + 0x80 - part /* Reverse offset to the part number */ +.long PAYLOAD_SIZE + ROM_IMAGE_SIZE /* Size of this romimage */ + .globl __id_end + +__id_end: +.previous diff --git a/src/southbridge/nvidia/ck804/id.lds b/src/southbridge/nvidia/ck804/id.lds new file mode 100644 index 0000000000..947a2f0c03 --- /dev/null +++ b/src/southbridge/nvidia/ck804/id.lds @@ -0,0 +1,6 @@ +SECTIONS { + . = (_ROMBASE + ROM_IMAGE_SIZE - 0x80) - (__id_end - __id_start); + .id (.): { + *(.id) + } +} diff --git a/src/southbridge/nvidia/ck804/romstrap.inc b/src/southbridge/nvidia/ck804/romstrap.inc new file mode 100644 index 0000000000..1810f7793d --- /dev/null +++ b/src/southbridge/nvidia/ck804/romstrap.inc @@ -0,0 +1,42 @@ +/* + * Copyright 2004 Tyan Computer + * by yhlu@tyan.com + */ + .section ".romstrap", "a", @progbits + + + .globl __romstrap_start +__romstrap_start: +rstables: + .long 0x2b16d065 + .long 0x0 + .long 0x0 + .long linkedlist + +linkedlist: + .long 0x0003001C // 10h + .long 0x08000000 // 14h + .long 0x00000000 // 18h + .long 0xFFFFFFFF // 1Ch + + .long 0xFFFFFFFF // 20h + .long 0xFFFFFFFF // 24h + .long 0xFFFFFFFF // 28h + .long 0xFFFFFFFF // 2Ch + + .long 0x81543266 // 30h, MAC address low 4 byte ---> keep it in 0xffffffd0 + .long 0x000000E0 // 34h, MAC address high 4 byte + + .long 0x002309CE // 38h, UUID low 4 byte + .long 0x00E08100 // 3Ch, UUID high 4 byte + +rspointers: + .long rstables // It will be 0xffffffe0 + .long rstables + .long rstables + .long rstables + + .globl __romstrap_end + +__romstrap_end: +.previous diff --git a/src/southbridge/nvidia/ck804/romstrap.lds b/src/southbridge/nvidia/ck804/romstrap.lds new file mode 100644 index 0000000000..5b69024629 --- /dev/null +++ b/src/southbridge/nvidia/ck804/romstrap.lds @@ -0,0 +1,6 @@ +SECTIONS { + . = (_ROMBASE + ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start); + .romstrap (.): { + *(.romstrap) + } +} -- cgit v1.2.3