From 8a13743569a8d1ac61b8a52d2dab621ff4041de2 Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Mon, 5 Oct 2015 08:00:51 -0700 Subject: x86 chipsets: Link non-code flow CHIPSET_BOOTBLOCK_INCLUDE files Non-code flow assembly stubs do not have to be included in bootblock.S, now that we have more freedom in bootblock linking. Rather than bringing these stubs to the config system, just link them in the bootblock. Note that we cannot fully remove CHIPSET_BOOTBLOCK_INCLUDE at this point, as some intel SOCs use this stub for code flow. objdump -h build/cbfs/fallback/bootblock.debug on a few random boards confirms that the appropriate sections are still included in the final binary. Change-Id: Id3f9ece14e399c1cc83090f407780c4a05a076f0 Signed-off-by: Alexandru Gagniuc Reviewed-on: https://review.coreboot.org/11856 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/southbridge/nvidia/ck804/Kconfig | 4 --- src/southbridge/nvidia/ck804/Makefile.inc | 1 + src/southbridge/nvidia/ck804/romstrap.S | 55 +++++++++++++++++++++++++++++++ src/southbridge/nvidia/ck804/romstrap.inc | 55 ------------------------------- src/southbridge/nvidia/mcp55/Kconfig | 4 --- src/southbridge/nvidia/mcp55/Makefile.inc | 1 + src/southbridge/nvidia/mcp55/romstrap.S | 55 +++++++++++++++++++++++++++++++ src/southbridge/nvidia/mcp55/romstrap.inc | 55 ------------------------------- 8 files changed, 112 insertions(+), 118 deletions(-) create mode 100644 src/southbridge/nvidia/ck804/romstrap.S delete mode 100644 src/southbridge/nvidia/ck804/romstrap.inc create mode 100644 src/southbridge/nvidia/mcp55/romstrap.S delete mode 100644 src/southbridge/nvidia/mcp55/romstrap.inc (limited to 'src/southbridge/nvidia') diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig index 42dce07b14..dbd24b73d1 100644 --- a/src/southbridge/nvidia/ck804/Kconfig +++ b/src/southbridge/nvidia/ck804/Kconfig @@ -42,8 +42,4 @@ config HPET_MIN_TICKS hex default 0xfa -config CHIPSET_BOOTBLOCK_INCLUDE - string - default "southbridge/nvidia/ck804/romstrap.inc" - endif diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc index 69dd4b271e..554a4407f0 100644 --- a/src/southbridge/nvidia/ck804/Makefile.inc +++ b/src/southbridge/nvidia/ck804/Makefile.inc @@ -22,5 +22,6 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_smbus.c bootblock-y += romstrap.ld +bootblock-y += romstrap.S endif diff --git a/src/southbridge/nvidia/ck804/romstrap.S b/src/southbridge/nvidia/ck804/romstrap.S new file mode 100644 index 0000000000..5a20107376 --- /dev/null +++ b/src/southbridge/nvidia/ck804/romstrap.S @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + .section ".romstrap", "a", @progbits + + + .align 16 + .globl __romstrap_start +__romstrap_start: +rstables: + .long 0x2b16d065 + .long 0x0 + .long 0x0 + .long linkedlist + +linkedlist: + .long 0x0003001C // 10h + .long 0x08000000 // 14h + .long 0x00000000 // 18h + .long 0xFFFFFFFF // 1Ch + + .long 0xFFFFFFFF // 20h + .long 0xFFFFFFFF // 24h + .long 0xFFFFFFFF // 28h + .long 0xFFFFFFFF // 2Ch + + .long 0x81543266 // 30h, MAC address low 4 byte ---> keep it in 0xffffffd0 + .long 0x000000E0 // 34h, MAC address high 4 byte + + .long 0x002309CE // 38h, UUID low 4 byte + .long 0x00E08100 // 3Ch, UUID high 4 byte + +rspointers: + .long rstables // It will be 0xffffffe0 + .long rstables + .long rstables + .long rstables + + .globl __romstrap_end + +__romstrap_end: +.previous diff --git a/src/southbridge/nvidia/ck804/romstrap.inc b/src/southbridge/nvidia/ck804/romstrap.inc deleted file mode 100644 index 5a20107376..0000000000 --- a/src/southbridge/nvidia/ck804/romstrap.inc +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - .section ".romstrap", "a", @progbits - - - .align 16 - .globl __romstrap_start -__romstrap_start: -rstables: - .long 0x2b16d065 - .long 0x0 - .long 0x0 - .long linkedlist - -linkedlist: - .long 0x0003001C // 10h - .long 0x08000000 // 14h - .long 0x00000000 // 18h - .long 0xFFFFFFFF // 1Ch - - .long 0xFFFFFFFF // 20h - .long 0xFFFFFFFF // 24h - .long 0xFFFFFFFF // 28h - .long 0xFFFFFFFF // 2Ch - - .long 0x81543266 // 30h, MAC address low 4 byte ---> keep it in 0xffffffd0 - .long 0x000000E0 // 34h, MAC address high 4 byte - - .long 0x002309CE // 38h, UUID low 4 byte - .long 0x00E08100 // 3Ch, UUID high 4 byte - -rspointers: - .long rstables // It will be 0xffffffe0 - .long rstables - .long rstables - .long rstables - - .globl __romstrap_end - -__romstrap_end: -.previous diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig index 666d3f8962..89aa45258a 100644 --- a/src/southbridge/nvidia/mcp55/Kconfig +++ b/src/southbridge/nvidia/mcp55/Kconfig @@ -42,8 +42,4 @@ config MCP55_PCI_E_X_3 int default 4 -config CHIPSET_BOOTBLOCK_INCLUDE - string - default "southbridge/nvidia/mcp55/romstrap.inc" - endif diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc index 74ef14cdbc..db275cc848 100644 --- a/src/southbridge/nvidia/mcp55/Makefile.inc +++ b/src/southbridge/nvidia/mcp55/Makefile.inc @@ -25,5 +25,6 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c endif bootblock-y += romstrap.ld +bootblock-y += romstrap.S endif diff --git a/src/southbridge/nvidia/mcp55/romstrap.S b/src/southbridge/nvidia/mcp55/romstrap.S new file mode 100644 index 0000000000..ff170a9927 --- /dev/null +++ b/src/southbridge/nvidia/mcp55/romstrap.S @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu for Tyan Computer. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + .section ".romstrap", "a", @progbits + + + .globl __romstrap_start +__romstrap_start: +rstables: + .long 0x2b16d065 + .long 0x0 + .long 0x0 + .long linkedlist + +linkedlist: + .long 0x0003001C // 10h + .long 0x08000000 // 14h + .long 0x00000000 // 18h + .long 0xFFFFFFFF // 1Ch + + .long 0xFFFFFFFF // 20h + .long 0xFFFFFFFF // 24h + .long 0xFFFFFFFF // 28h + .long 0xFFFFFFFF // 2Ch + + .long 0x81543266 // 30h, MAC address low 4 byte ---> keep it in 0xffffffd0 + .long 0x000000E0 // 34h, MAC address high 4 byte + + .long 0x002309CE // 38h, UUID low 4 byte + .long 0x00E08100 // 3Ch, UUID high 4 byte + +rspointers: + .long rstables // It will be 0xffffffe0 + .long rstables + .long rstables + .long rstables + + .globl __romstrap_end + +__romstrap_end: +.previous diff --git a/src/southbridge/nvidia/mcp55/romstrap.inc b/src/southbridge/nvidia/mcp55/romstrap.inc deleted file mode 100644 index ff170a9927..0000000000 --- a/src/southbridge/nvidia/mcp55/romstrap.inc +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Tyan Computer - * Written by Yinghai Lu for Tyan Computer. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - .section ".romstrap", "a", @progbits - - - .globl __romstrap_start -__romstrap_start: -rstables: - .long 0x2b16d065 - .long 0x0 - .long 0x0 - .long linkedlist - -linkedlist: - .long 0x0003001C // 10h - .long 0x08000000 // 14h - .long 0x00000000 // 18h - .long 0xFFFFFFFF // 1Ch - - .long 0xFFFFFFFF // 20h - .long 0xFFFFFFFF // 24h - .long 0xFFFFFFFF // 28h - .long 0xFFFFFFFF // 2Ch - - .long 0x81543266 // 30h, MAC address low 4 byte ---> keep it in 0xffffffd0 - .long 0x000000E0 // 34h, MAC address high 4 byte - - .long 0x002309CE // 38h, UUID low 4 byte - .long 0x00E08100 // 3Ch, UUID high 4 byte - -rspointers: - .long rstables // It will be 0xffffffe0 - .long rstables - .long rstables - .long rstables - - .globl __romstrap_end - -__romstrap_end: -.previous -- cgit v1.2.3