From 5692c5733633bfb8b23f1111de152eff0233b713 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 5 Oct 2010 13:40:31 +0000 Subject: - move EHCI_BAR_INDEX to ehci.h - it's constant as per EHCI spec 2.3.1 - move EHCI_BAR and EHCI_DEBUG_OFFSET to Kconfig to be set by USB debug port enabled southbridges - drop USB debug code includes from romstage.cs and use romstage-srcs in the build system instead Signed-off-by: Patrick Georgi Acked-by: Uwe Hermann git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/nvidia/ck804/Kconfig | 8 ++++++++ src/southbridge/nvidia/ck804/Makefile.inc | 3 +++ src/southbridge/nvidia/ck804/ck804.h | 1 + src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c | 11 +++++------ src/southbridge/nvidia/mcp55/Kconfig | 9 +++++++++ src/southbridge/nvidia/mcp55/Makefile.inc | 2 ++ src/southbridge/nvidia/mcp55/mcp55.h | 1 + src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c | 11 +++++------ 8 files changed, 34 insertions(+), 12 deletions(-) (limited to 'src/southbridge/nvidia') diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig index f0cfae7183..d4a8650708 100644 --- a/src/southbridge/nvidia/ck804/Kconfig +++ b/src/southbridge/nvidia/ck804/Kconfig @@ -8,3 +8,11 @@ config ID_SECTION_OFFSET hex default 0x80 if SOUTHBRIDGE_NVIDIA_CK804 +config EHCI_BAR + hex + default 0xfef00000 if SOUTHBRIDGE_NVIDIA_CK804 + +config EHCI_DEBUG_OFFSET + hex + default 0x98 if SOUTHBRIDGE_NVIDIA_CK804 + diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc index bceec85737..48f7713a8b 100644 --- a/src/southbridge/nvidia/ck804/Makefile.inc +++ b/src/southbridge/nvidia/ck804/Makefile.inc @@ -15,5 +15,8 @@ ramstage-y += ck804_reset.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ck804_fadt.c +romstage-y += ck804_enable_usbdebug.c + chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc chipset_bootblock_lds += $(src)/southbridge/nvidia/ck804/romstrap.lds + diff --git a/src/southbridge/nvidia/ck804/ck804.h b/src/southbridge/nvidia/ck804/ck804.h index fb1b8d80a0..7285d18d0e 100644 --- a/src/southbridge/nvidia/ck804/ck804.h +++ b/src/southbridge/nvidia/ck804/ck804.h @@ -4,5 +4,6 @@ #include "chip.h" void ck804_enable(device_t dev); +void ck804_enable_usbdebug(unsigned int port); #endif diff --git a/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c b/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c index f82196329e..3cccded343 100644 --- a/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c +++ b/src/southbridge/nvidia/ck804/ck804_enable_usbdebug.c @@ -22,8 +22,11 @@ */ #include +#include +#include #include #include +#include "ck804.h" #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 #define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE @@ -31,10 +34,6 @@ #define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif -#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ -#define EHCI_BAR_INDEX 0x10 -#define EHCI_DEBUG_OFFSET 0x98 - void set_debug_port(unsigned int port) { u32 dword; @@ -47,7 +46,7 @@ void set_debug_port(unsigned int port) pci_write_config32(dev, 0x74, dword); } -static void ck804_enable_usbdebug(unsigned int port) +void ck804_enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */ @@ -55,7 +54,7 @@ static void ck804_enable_usbdebug(unsigned int port) set_debug_port(port); /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig index 213b1755f9..6084b1ea44 100644 --- a/src/southbridge/nvidia/mcp55/Kconfig +++ b/src/southbridge/nvidia/mcp55/Kconfig @@ -6,3 +6,12 @@ config SOUTHBRIDGE_NVIDIA_MCP55 config ID_SECTION_OFFSET hex default 0x80 if SOUTHBRIDGE_NVIDIA_MCP55 + +config EHCI_BAR + hex + default 0xfef00000 if SOUTHBRIDGE_NVIDIA_MCP55 + +config EHCI_DEBUG_OFFSET + hex + default 0x98 if SOUTHBRIDGE_NVIDIA_MCP55 + diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc index 4388ca8e9a..a9dcf7f40f 100644 --- a/src/southbridge/nvidia/mcp55/Makefile.inc +++ b/src/southbridge/nvidia/mcp55/Makefile.inc @@ -15,5 +15,7 @@ driver-$(CONFIG_GENERATE_ACPI_TABLES) += mcp55_fadt.c ramstage-y += mcp55_reset.c +romstage-y += mcp55_enable_usbdebug.c + chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc chipset_bootblock_lds += $(src)/southbridge/nvidia/mcp55/romstrap.lds diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h index 687232f302..acb291a1d0 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.h +++ b/src/southbridge/nvidia/mcp55/mcp55.h @@ -29,4 +29,5 @@ void mcp55_enable(device_t dev); #else void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); #endif +void mcp55_enable_usbdebug(unsigned int port); #endif /* MCP55_H */ diff --git a/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c b/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c index f1f5c2ab11..e0b293c81a 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c +++ b/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c @@ -22,8 +22,11 @@ */ #include +#include +#include #include #include +#include "mcp55.h" #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE @@ -31,10 +34,6 @@ #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE #endif -#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */ -#define EHCI_BAR_INDEX 0x10 -#define EHCI_DEBUG_OFFSET 0x98 - void set_debug_port(unsigned int port) { u32 dword; @@ -47,7 +46,7 @@ void set_debug_port(unsigned int port) pci_write_config32(dev, 0x74, dword); } -static void mcp55_enable_usbdebug(unsigned int port) +void mcp55_enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */ @@ -55,7 +54,7 @@ static void mcp55_enable_usbdebug(unsigned int port) set_debug_port(port); /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); -- cgit v1.2.3