From 2ee6779a64922af755a35ce70f85f2d67b488557 Mon Sep 17 00:00:00 2001 From: Carl-Daniel Hailfinger Date: Wed, 1 Oct 2008 12:52:52 +0000 Subject: The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots of code to use it. That makes the code more readable and also less error-prone. Abuild tested. Signed-off-by: Carl-Daniel Hailfinger Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/nvidia/ck804/ck804_early_setup.c | 6 +++--- src/southbridge/nvidia/ck804/ck804_early_setup_car.c | 12 ++++++------ src/southbridge/nvidia/ck804/ck804_lpc.c | 3 ++- src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c | 14 +++++++------- src/southbridge/nvidia/mcp55/mcp55_lpc.c | 3 ++- 5 files changed, 20 insertions(+), 18 deletions(-) (limited to 'src/southbridge/nvidia') diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup.c b/src/southbridge/nvidia/ck804/ck804_early_setup.c index 6634161362..bbce8207de 100644 --- a/src/southbridge/nvidia/ck804/ck804_early_setup.c +++ b/src/southbridge/nvidia/ck804/ck804_early_setup.c @@ -102,7 +102,7 @@ static void ck804_early_set_port(void) #endif }; - setup_resource_map(ctrl_devport_conf, sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0])); + setup_resource_map(ctrl_devport_conf, ARRAY_SIZE(ctrl_devport_conf)); } @@ -121,7 +121,7 @@ static void ck804_early_clear_port(void) #endif }; - setup_resource_map(ctrl_devport_conf_clear, sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0])); + setup_resource_map(ctrl_devport_conf_clear, ARRAY_SIZE(ctrl_devport_conf_clear)); } @@ -324,7 +324,7 @@ static void ck804_early_setup(void) - setup_resource_map_x(ctrl_conf, sizeof(ctrl_conf)/sizeof(ctrl_conf[0])); + setup_resource_map_x(ctrl_conf, ARRAY_SIZE(ctrl_conf)); setup_ss_table(ANACTRL_IO_BASE+0x40, ANACTRL_IO_BASE+0x44, ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64); setup_ss_table(ANACTRL_IO_BASE+0xb0, ANACTRL_IO_BASE+0xb4, ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64); diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup_car.c b/src/southbridge/nvidia/ck804/ck804_early_setup_car.c index 729a47f178..ec18ffc8b6 100644 --- a/src/southbridge/nvidia/ck804/ck804_early_setup_car.c +++ b/src/southbridge/nvidia/ck804/ck804_early_setup_car.c @@ -105,12 +105,12 @@ static void ck804_early_set_port(unsigned ck804_num, unsigned *busn, unsigned *i for(j = 0; j < ck804_num; j++ ) { if(busn[j]==0) { //sb chain setup_resource_map_offset(ctrl_devport_conf, - sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]), + ARRAY_SIZE(ctrl_devport_conf), PCI_DEV(busn[j], 0, 0) , io_base[j]); continue; } setup_resource_map_offset(ctrl_devport_conf_b, - sizeof(ctrl_devport_conf_b)/sizeof(ctrl_devport_conf_b[0]), + ARRAY_SIZE(ctrl_devport_conf_b), PCI_DEV(busn[j], 0, 0) , io_base[j]); } } @@ -132,12 +132,12 @@ static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn, unsigned for(j = 0; j < ck804_num; j++ ) { if(busn[j]==0) { //sb chain setup_resource_map_offset(ctrl_devport_conf_clear, - sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]), + ARRAY_SIZE(ctrl_devport_conf_clear), PCI_DEV(busn[j], 0, 0) , io_base[j]); continue; } setup_resource_map_offset(ctrl_devport_conf_clear_b, - sizeof(ctrl_devport_conf_clear_b)/sizeof(ctrl_devport_conf_clear_b[0]), + ARRAY_SIZE(ctrl_devport_conf_clear_b), PCI_DEV(busn[j], 0, 0) , io_base[j]); } @@ -327,13 +327,13 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn, unsigned *io_b for(j=0; j #include #include +#include #include "ck804.h" #define CK804_CHIP_REV 2 @@ -82,7 +83,7 @@ static void setup_ioapic(unsigned long ioapic_base) l = (unsigned long *) ioapic_base; - for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]); + for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) { l[0] = (a->reg * 2) + 0x10; l[4] = a->value_low; diff --git a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c index 48218558ee..64ec785781 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c @@ -106,7 +106,7 @@ static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn, unsigned *d int j; for(j = 0; j < mcp55_num; j++ ) { setup_resource_map_offset(ctrl_devport_conf, - sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]), + ARRAY_SIZE(ctrl_devport_conf), PCI_DEV(busn[j], devn[j], 0) , io_base[j]); } } @@ -123,7 +123,7 @@ static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn, unsigned int j; for(j = 0; j < mcp55_num; j++ ) { setup_resource_map_offset(ctrl_devport_conf_clear, - sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]), + ARRAY_SIZE(ctrl_devport_conf_clear), PCI_DEV(busn[j], devn[j], 0) , io_base[j]); } @@ -327,23 +327,23 @@ static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn for(j=0; j1) ) { - setup_resource_map_x_offset(ctrl_conf_master_only, sizeof(ctrl_conf_master_only)/sizeof(ctrl_conf_master_only[0]), + setup_resource_map_x_offset(ctrl_conf_master_only, ARRAY_SIZE(ctrl_conf_master_only), PCI_DEV(busn[j], devn[j], 0), io_base[j]); } - setup_resource_map_x_offset(ctrl_conf_2, sizeof(ctrl_conf_2)/sizeof(ctrl_conf_2[0]), + setup_resource_map_x_offset(ctrl_conf_2, ARRAY_SIZE(ctrl_conf_2), PCI_DEV(busn[j], devn[j], 0), io_base[j]); } diff --git a/src/southbridge/nvidia/mcp55/mcp55_lpc.c b/src/southbridge/nvidia/mcp55/mcp55_lpc.c index f4df404e13..3cfcd57a71 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_lpc.c +++ b/src/southbridge/nvidia/mcp55/mcp55_lpc.c @@ -34,6 +34,7 @@ #include #include #include +#include #include "mcp55.h" #define NMI_OFF 0 @@ -106,7 +107,7 @@ static void setup_ioapic(unsigned long ioapic_base, int master) l = (unsigned long *) ioapic_base; - for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]); + for (i = 0; i < ARRAY_SIZE(ioapicregvalues); i++, a++) { l[0] = (a->reg * 2) + 0x10; l[4] = a->value_low; -- cgit v1.2.3